DATASHEET

ISL54063, ISL54064
®
Data Sheet
November 3, 2009
Negative Signal Swing, Sub-ohm, Dual
SPST with Click and Pop Elimination
Single Supply Switch
The Intersil ISL54063 and ISL54064 devices are a low
ON-resistance, low voltage, bi-directional, dual
single-pole/single-throw (SPST) analog switch. It is designed
to operate from a single +1.8V to +6.5V supply and pass
signals that swing down to 6.5V below the positive supply rail.
Targeted applications include battery powered equipment that
benefit from low rON (0.56Ω), low power consumption (20nA)
and fast switching speeds (tON = 55ns, tOFF = 18ns). The
digital inputs are 1.8V logic-compatible up to a +3V supply.
The ISL54063 and ISL54064 also features integrated circuitry
to eliminate click and pop noise to an audio speaker. The
ISL54063, ISL54064 are offered in a small form factor
package, alleviating board space limitations. It is available in a
tiny 10 Ld 1.8 x 1.4mm µTQFN or 10 Ld 3mmx3mm TDFN
package.
The ISL54063 is a committed dual single-pole/single-throw
(SPST) that consist of two normally open (NO) switches with
independent logic control. The ISL54064 is a committed dual
single-pole/single-throw (SPST) that consist of two normally
closed (NC) switches with independent logic control.
FN6582.1
Features
• Pb-free (RoHS Compliant)
• Negative Signal Swing (Max 6.5V below V+)
• Audio Click and Pop Elimination Circuitry
• ON-Resistance (rON)
- V+ = +4.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55Ω
- V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.57Ω
- V+ = +2.7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.82Ω
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8Ω
• rON Matching Between Channels . . . . . . . . . . . . . . . . .10mΩ
• rON Flatness Across Signal Range . . . . . . . . . . . . . . . .0.35Ω
• Low THD+N @ 32Ω Load . . . . . . . . . . . . . . . . . . . . . . 0.02%
• Single Supply Operation. . . . . . . . . . . . . . . . . +1.8V to +6.5V
• Low Power Consumption @ 3V (PD) . . . . . . . . . . . 24nW
• Fast Switching Action (V+ = +4.3V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23ns
• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >6kV
• Guaranteed Break-before-Make
TABLE 1. FEATURES AT A GLANCE
ISL54063
ISL54064
Number of Switches
2
2
• Low I+ Current when VINH is not at the V+ Rail
SW
SPST NO
SPST NC
4.3V rON
0.65Ω
0.65Ω
4.3V tON/tOFF
43ns/23ns
43ns/23ns
2.7V rON
0.9Ω
0.9Ω
2.7V tON/tOFF
55ns/18ns
55ns/18ns
1.8V rON
1.8Ω
1.8Ω
1.8V tON/tOFF
145ns/28ns
145ns/28ns
Packages
2.0
1.8
• 1.8V Logic Compatible (+3V supply)
10 Ld µTQFN, 10 Ld TDFN
ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
• Available in 10 Ld µTQFN 1.8x1.4mm and 10 Ld 3x3mm
TDFN
Applications
• Audio and Video Switching
• Battery powered, Handheld, and Portable Equipment
- MP3 and Multimedia Players
- Cellular/mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
• Portable Test and Measurement
ICOM = 100mA
V+ = 1.8V
• Medical Equipment
rON (Ω)
1.6
1.4
Related Literature
1.2
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
1.0
V+ = 2.7V
0.8
0.6
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
V+ = 4.5V
0.4
0.2
-6
-5
-4
-3
-2
1
-1 0
VCOM (V)
1
2
3
4
5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54063, ISL54064
Pinouts
(Note 1)
ISL54064
(10 LD TDFN)
TOP VIEW
ISL54063
(10 LD TDFN)
TOP VIEW
N.C. 4
GND 5
CLICK AND
POP
CIRCUITRY
8
COM1
9
N.C.
10
7 N.C.
NC1 4
6 V+
GND 5
7 NC2
CLICK AND
POP
CIRCUITRY
ISL54063
(10 LD µTQFN)
TOP VIEW
ISL54064
(10 LD µTQFN)
TOP VIEW
IN1
IN2
IN1
IN2
6
7
6
7
NO1
8 COM2
COM1 3
8 COM2
COM1 3
9 N.C.
N.C. 2
9 NO2
NO1 2
10 IN2
IN1 1
10 IN2
IN1 1
CLICK AND
POP
CIRCUITRY
5
NO2
4
COM2
3
N.C.
N.C.
8
COM1
NC1
5
N.C.
9
4
COM2
10
3
NC2
CLICK AND
POP
CIRCUITRY
1
2
1
GND
6 V+
GND
V+
2
V+
NOTE:
1. Switches Shown for INx = Logic “0”.
Truth Table
NOTE:
Pin Descriptions
INx
ISL54063
NOx to COMx
ISL54064
NCx to COMx
0
OFF
ON
1
ON
OFF
Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.
2
PIN
FUNCTION
V+
IC Power Supply (+1.8V to +6.5V). Decouple V+ to
ground by placing a 0.1µF capacitor at the V+ and GND
supply lines as near as the IC as possible.
GND
Ground Connection
INx
Digital Control Input
COM
Analog Switch Common Pin
NOx
Analog Switch Normally Open Pin
NCx
Analog Switch Normally Closed Pin
N.C.
No Connect
FN6582.1
November 3, 2009
ISL54063, ISL54064
Ordering Information
PART
NUMBER
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL54063IRTZ
(Note 3)
4063
-40 to +85
10 Ld 3x3 TDFN
L10.3x3A
ISL54063IRTZ-T
(Notes 2, 3)
4063
-40 to +85
10 Ld 3x3 TDFN (Tape and Reel)
L10.3x3A
ISL54063IRUZ-T
(Notes 2, 4)
T6
-40 to +85
10 Ld Thin µTQFN (Tape and Reel)
L10.1.8x1.4A
ISL54064IRTZ
(Note 3)
4064
-40 to +85
10 Ld 3x3 TDFN
L10.3x3A
ISL54064IRTZ-T
(Notes 2, 3)
4064
-40 to +85
10 Ld 3x3 TDFN (Tape and Reel)
L10.3x3A
ISL54064IRUZ-T
(Notes 2, 4)
T7
-40 to +85
10 Ld Thin µTQFN (Tape and Reel)
L10.1.8x1.4A
NOTES:
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3
FN6582.1
November 3, 2009
ISL54063, ISL54064
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7.0V
Input Voltages
NOx, NCx (Note 5) . . . . . . . . . . . . . . . . (V+ - 7V) to ((V+) + 0.5V)
INx (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Output Voltages
COMx (Note 5) . . . . . . . . . . . . . . . . . . . (V+ - 7V) to ((V+) + 0.5V)
Continuous Current NOx, NCx, or COMx . . . . . . . . . . . . . . ±300mA
Peak Current NOx, NCx, or COMx
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±500mA
ESD Rating:
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>400V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kV
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
10 Ld 3x3 TDFN Package (Notes 6, 8)
55
18
10 Ld µTQFN Package (Note 7) . . . . .
155
N/A
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Power Supply Range . . . . . . . . . . . . . . . . . . . . . . . . +1.8V to +6.5V
AUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
5. Signals on NC, NO, IN, or COM exceeding V+ or GND by the specified amount are clamped by internal diodes. Limit forward diode current to
maximum current ratings.
6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
7. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
8. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 9), Unless
Otherwise Specified.
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 10, 11)
TYP
MAX
(Notes 10, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
V+ = 4.5V, ICOM = 100mA, VNO or VNC = (V+ 6.5) to V+ (see Figure 4)
25
-
0.55
-
Ω
Full
-
0.68
-
Ω
rON Matching Between Channels,
ΔrON
V+ = 4.5V, ICOM = 100mA, VNO or VNC = Voltage
at max rON, (Note 13)
25
-
15
-
mΩ
Full
-
30
-
mΩ
rON Flatness, RFLAT(ON)
V+ = 4.5V, ICOM = 100mA, VNO or VNC = (V+ 6.5) to V+, (Note 12)
25
-
0.11
-
Ω
Full
-
0.14
-
Ω
COM ON Leakage Current,
ICOM(ON)
V+ = 5V, VCOM = -1.5V, 5V, VNO or VNC = Float
25
-
49
-
nA
Full
-
0.7
-
µA
ns
ON-Resistance, rON
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω,
CL = 35pF (see Figure 1)
25
-
35
-
Full
-
30
-
ns
25
-
10
-
ns
Turn-OFF Time, tOFF
V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω,
CL = 35pF (see Figure 1)
Full
-
15
-
ns
Charge Injection, Q
VG = 0V, RG = 0Ω, CL = 1.0nF (see Figure 2)
25
-
170
-
pC
OFF-Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(see Figure 3)
25
-
60
-
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 1MHz, VCOM = 1VRMS
(see Figure 5)
25
-
-75
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 0.5VP-P, RL = 32Ω
25
-
0.02
-
%
-3dB Bandwidth
VCOM = 1VRMS, RL = 50Ω, CL = 5pF
25
-
60
-
MHz
NO x or NCx OFF Capacitance,
COFF
f = 1MHz
25
-
36
-
pF
COMx ON Capacitance, CCOM(ON)
f = 1MHz (See Figure 6)
25
-
88
-
pF
4
FN6582.1
November 3, 2009
ISL54063, ISL54064
Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 9), Unless
Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 10, 11)
TYP
MAX
(Notes 10, 11) UNITS
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 5.5V, VIN = 0V or V+
25
-
0.02
0.1
µA
Full
-
2.5
-
µA
Full
-
-
0.8
V
Full
2.4
-
-
V
25
-0.1
-
0.1
µA
Full
-
0.89
-
µA
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Input Voltage High, VINH
Input Current, IINH, IINL
V+ = 5.5V, VIN = 0V or V+
Electrical Specifications - 4.3V Supply
PARAMETER
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 9),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 10, 11)
TYP
MAX
(Notes 10, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
ON-Resistance, rON
V+ = 4.3V, ICOM = 100mA, VNO or VNC =
(V+ - 6.5V) to V+, (See Figure 4)
rON Matching Between Channels,
ΔrON
V+ = 4.3V, ICOM = 100mA, VNO or VNC = Voltage
at max rON, (Note 13)
rON Flatness, RFLAT(ON)
V+ = 4.3V, ICOM = 100mA, VNO or VNC = (V+ 6.5V) to V+, (Note 12)
COM ON Leakage Current,
ICOM(ON)
V+ = 4.3V, VCOM = -1.2V, 4.3V, VNO or VNC = Float
25
-
0.57
-
Ω
Full
-
0.68
-
Ω
25
-
15
-
mΩ
Full
-
30
-
mΩ
25
-
0.1
-
Ω
Full
-
0.14
-
Ω
25
-0.1
-
0.1
µA
Full
-
1.1
-
µA
25
-
43
-
ns
Full
-
50
-
ns
25
-
23.1
-
ns
Full
-
23.2
-
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50Ω,
CL = 35pF (see Figure 1)
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50Ω,
CL = 35pF (see Figure 1)
Turn-OFF Time, tOFF
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2)
25
-
200
-
pC
OFF-Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(see Figure 3)
25
-
60
-
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 1MHz, VCOM = 1VRMS
(see Figure 5)
25
-
-75
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32Ω
25
-
0.04
-
%
-3dB Bandwidth
VCOM = 1VRMS, RL = 50Ω, CL = 5pF
25
-
60
-
MHz
NOx or NCx OFF Capacitance,
COFF
f = 1MHz
25
-
36
-
pF
COMx ON Capacitance, CCOM(ON)
f = 1MHz (see Figure 6)
25
-
88
-
pF
25
-
0.003
0.1
µA
Full
-
2.6
-
µA
25
-
0.89
12
µA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = +4.5V, VIN = 0V or V+
Positive Supply Current, I+
V+ = +4.2V, VIN = 2.85V
5
FN6582.1
November 3, 2009
ISL54063, ISL54064
Electrical Specifications - 4.3V Supply
PARAMETER
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 9),
Unless Otherwise Specified. (Continued)
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 10, 11)
TYP
MAX
(Notes 10, 11) UNITS
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Full
-
-
0.5
V
Input Voltage High, VINH
Full
1.6
-
-
V
25
-0.5
-
0.5
µA
Full
-
0.5
-
µA
Input Current, IINH, IINL
V+ = 4.5V, VIN = 0V or V+
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 9),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
ON-Resistance, rON
V+ = 2.7V, ICOM = 100mA, VNO or VNC =
(V+ -6.5V) to V+ (see Figure 4 )
rON Matching Between Channels,
ΔrON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage
at max rON, (Note 13)
rON Flatness, RFLAT(ON)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = (V+ 6.5V) to V+, (Notes 12, 14)
25
-
0.82
-
Ω
Full
-
0.94
-
Ω
25
-
10
-
mΩ
Full
-
30
-
mΩ
25
-
0.35
0.5
Ω
Full
-
0.4
0.55
Ω
25
-
50
-
ns
Full
-
60
-
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω,
CL = 35pF (see Figure 1)
Turn-OFF Time, tOFF
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω,
CL = 35pF (see Figure 1)
25
-
27
-
ns
Full
-
35
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2)
25
-
94
-
pC
OFF-Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(see Figure 3)
25
-
60
-
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 1MHz, VCOM = 1VRMS
(see Figure 5)
25
-
-75
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 0.5VP-P, RL = 32Ω
25
-
0.04
-
%
-3dB Bandwidth
VCOM = 1VRMS, RL = 50Ω, CL = 5pF
25
-
60
-
MHz
NOx or NCx OFF Capacitance,
COFF
f = 1MHz
25
-
36
-
pF
COMx ON Capacitance, CCOM(ON)
f = 1MHz (see Figure 6)
25
-
88
-
pF
Input Voltage Low, VINL
25
-
-
0.5
V
Input Voltage High, VINH
25
1.4
-
-
V
25
-0.5
-
0.5
µA
Full
-
0.4
-
µA
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 3.3V, VIN = 0V or V+
6
FN6582.1
November 3, 2009
ISL54063, ISL54064
Electrical Specifications - 1.8V Supply
PARAMETER
Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 9),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
V+ = 1.8V, ICOM = 100mA, VNO or VNC =
(V+ -6.5V) to V+ (see Figure 4)
ON-Resistance, rON
25
-
1.87
-
Ω
Full
-
1.97
-
Ω
25
-
16
-
mΩ
Full
rON Matching Between Channels,
ΔrON
V+ = 1.8V, ICOM = 100mA, VNO or VNC = Voltage
at max rON, (Note 13)
-
30
-
mΩ
rON Flatness, RFLAT(ON)
V+ = 1.8V, ICOM = 100mA, VNO or
VNC = (V+ -6.5V) to V+, (Note 12)
25
-
1.34
-
Ω
Full
-
1.43
-
Ω
V+ = 1.8V, VNO or VNC = 1.8V, RL = 50Ω,
CL = 35pF (see Figure 1)
25
-
145
-
ns
Full
-
150
-
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.8V, VNO or VNC = 1.8V, RL = 50Ω,
CL = 35pF (see Figure 1)
25
-
20
-
ns
Full
-
22
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2)
25
-
40
-
pC
-3dB Bandwidth
VCOM = 1VRMS, RL = 50Ω, CL = 5pF
25
-
60
-
MHz
NOx or NCx OFF Capacitance,
COFF
f = 1MHz (see Figure 6)
25
-
36
-
pF
COMx ON Capacitance, CCOM(ON)
f = 1MHz (see Figure 6)
25
-
88
-
pF
25
-
-
0.4
V
Turn-OFF Time, tOFF
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
25
1.0
-
-
V
Input Current, IINH, IINL
V+ = 2.0V, VIN = 0V or V+
25
-0.5
-
0.5
µA
Input Current, IINH, IINL
V+ = 2.0V, VIN = 0V or V+
Full
-
0.38
-
µA
Input Voltage High, VINH
NOTES:
9. VIN = input voltage to perform proper function.
10. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
12. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range.
13. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value, between NC1 and NC2 or between NO1 and NO2.
14. Limits established by characterization and are not production tested.
7
FN6582.1
November 3, 2009
ISL54063, ISL54064
Test Circuits and Waveforms
V+
V+
LOGIC
INPUT
tr < 5ns
tf < 5ns
50%
C
0V
tOFF
SWITCH
INPUT VNO
SWITCH
INPUT
COM
IN
VOUT
90%
SWITCH
OUTPUT
VOUT
NO OR NC
90%
LOGIC
INPUT
CL
35pF
RL
50Ω
GND
0V
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO or NC) -----------------------R L + r ON
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
RG
SWITCH
OUTPUT
VOUT
C
NO OR NC
VOUT
COM
ΔVOUT
VG
GND
IN
CL
V+
ON
ON
LOGIC
INPUT
LOGIC
INPUT
OFF
0V
Q = ΔVOUT x CL
Repeat test for all switches.
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
C
V+
C
*50Ω SOURCE
SIGNAL
GENERATOR
rON = V1/100mA
NO OR NC
NO OR NC
IN
0V OR V+
VNX
100mA
IN
V1
0V OR V+
COM
ANALYZER
GND
COM
RL
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 3. OFF-ISOLATION TEST CIRCUIT
8
Repeat test for all switches.
FIGURE 4. rON TEST CIRCUIT
FN6582.1
November 3, 2009
ISL54063, ISL54064
Test Circuits and Waveforms (Continued)
V+
V+
C
C
*50Ω SOURCE
SIGNAL
GENERATOR
COM
NO1 OR NC1
50Ω
COM1
IN
INX
0V OR V+
NO OR NC
NC2 OR NO2
COM2
ANALYZER
0V OR V+
IMPEDANCE
ANALYZER
GND
NC
GND
RL
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 6. CAPACITANCE TEST CIRCUIT
FIGURE 5. CROSSTALK TEST CIRCUIT
INx
VDC
0V
220µF
NCx
VINx*
0V
VDC
tD
tD
CLICK AND POP
CIRCUITRY
*VINx waveform for Click and Pop Elimination on NOx terminal.
COMx
RL
220µF
For Click and Pop Elimination on NCx terminal invert VINx.
NOx
VDC
tD = 200ms measured at 50% points.
FIGURE 7A. CLICK AND POP WAVEFORM
FIGURE 7B. CLICK AND POP TEST CIRCUIT
FIGURE 7. CLICK AND POP ELIMINATION
Detailed Description
The ISL54063 and ISL54064 are bidirectional, dual single
pole-single throw (SPST) analog switches that offers precise
switching from a single 1.8V to 6.5V supply with low
ON-resistance (0.83Ω), high speed operation (tON = 55ns,
tOFF = 18ns) and negative signal swing capability. The
device is especially well suited for portable battery powered
equipment due to its low operating supply voltage (1.8V), low
power consumption (20nA), and a tiny 1.8mmx1.4mm µTQFN
package or a 3mmx3mm TDFN package. The low
ON-resistance and rON flatness provide very low insertion
loss and signal distortion for applications that require signal
switching with minimal interference by the switch.
The ISL54063 is a normally open (NO) SPST analog switch.
The ISL54064 is a normally closed (NC) SPST analog
switch.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
9
which might permanently damage the IC. The ISL54063 and
ISL54064 contains ESD protection diodes on each pin of the
IC (see Figure 8). These diodes connect to either a +Ring or
-Ring for ESD protection. To prevent forward biasing the
ESD diodes to the +Ring, V+ must be applied before any
input signals, and the input signal voltages must remain
between recommended operating range.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a logic pin or switch terminal goes
above the V+ rail.
Logic inputs can be protected by adding a 1kΩ resistor in
series with the logic input (see Figure 8). The resistor limits
the input current below the threshold that produces
permanent damage.
FN6582.1
November 3, 2009
ISL54063, ISL54064
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low rON switch. Alternatively, connecting
external Schottky diodes from the V+ rail to the signal pins
will shunt the fault current through the Schottky diode
instead of through the internal ESD diodes, thereby
protecting the switch. These Schottky diodes must be sized
to handle the expected fault current..
V+
+RING
VCOMx
VNOx
OR
VNCx
CLAMP
1kΩ
LOGIC
INPUTS
GND
-RING
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL54063 and ISL54064 construction is typical of most
single supply CMOS analog switches which have two supply
pins: V+ and GND. V+ and GND provide the CMOS switch
bias and sets their analog voltage limits. Unlike switches with
a 5.5V maximum supply voltage, the ISL54063 and
ISL54064 have a 6.5V maximum supply voltage providing
plenty of head room for the 10% tolerance of 5V supplies
due to overshoot and noise spikes.
The minimum recommended supply voltage is 1.8V. It is
important to note that the input signal range, switching times,
and ON-resistance degrade at lower supply voltages. Refer
to the “Electrical Specifications” tables, beginning on page 4,
and “Typical Performance Curves”, beginning on page 11,
for details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to V+ and
GND signals levels to drive the analog switch gate terminals.
A high frequency decoupling capacitor placed as close to the
V+ and GND pin as possible is recommended for proper
operation of the switch. A value of 0.1µF is highly
recommended.
Negative Signal Swing Capability
The ISL54063 and ISL54064 contains circuitry that allows
the analog switch signal to swing below ground. The device
has an analog signal range of 6.5V below V+ up to the V+
rail (see Figure 14) while maintaining low rON performance.
For example, if V+ = 5V, then the analog input signal range is
from -1.5V to +5V. If V+ = 2.7V then the range is from -3.8V
to +2.7V.
10
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.45V VOLMAX
and 1.35V VOHMIN) over a supply range of 1.8V to 3.3V
(see Figure 16). At 3.3V the VIL level is 0.5V maximum. This
is still below the 1.8V CMOS guaranteed low output
maximum level of 0.45V, but noise margin is reduced. At
3.3V the VIH level is 1.4V minimum. While this is above the
1.8V CMOS guaranteed high output minimum of 1.35V
under most operating conditions the switch will recognize
this as a valid logic high.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation. The ISL54063 and
ISL54064 have been designed to minimize the supply
current whenever the digital input voltage is not driven to the
supply rails (0V to V+). For example driving the device with
2.85V logic high while operating with a 4.2V supply the
device draws only 1µA of current.
High-Frequency Performance
In 50Ω systems, the ISL54063 and ISL54064 have an ON
switch -3dB bandwidth of 60MHz (see Figure 19). The
frequency response is very consistent over a wide V+ range,
and for varying analog signal levels.
An OFF switch acts like a capacitor across the open
terminals and AC couples higher frequencies, resulting in
signal feed-through from a switch’s input to its output.
Off-Isolation is the resistance to this feed-through. Crosstalk
indicates the amount of feed-through from one switch
channel to another switch channel. Figure 20 details the high
Off-Isolation and Crosstalk rejection provided by this part. At
100kHz, Off-Isolation is about 60dB in 50Ω systems,
decreasing approximately 20dB per decade as frequency
increases. At 1MHz, Crosstalk is about -75dB in 50Ω
systems, decreasing approximately 20dB per decade as
frequency increases.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin, V+ and GND. One of these
diodes conducts if any analog signal exceeds the
recommended analog signal range.
Virtually all the analog switch leakage current comes from
the ESD diodes and reversed biased junctions in the switch
cell. Although the ESD diodes on a given signal pin are
identical and therefore fairly well balanced, they are reverse
biased differently. Each is biased to either the +Ring or -Ring
and the analog input signal. This means their leakages will
vary as the signal varies. The difference in the two diode
leakages to the +Ring or -Ring and the reverse biased
junctions at the internal switch cell constitutes the
analog-signal-path leakage current.
FN6582.1
November 3, 2009
ISL54063, ISL54064
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
1.00
2.0
ICOM = 100mA
1.8
V+ = 4.5V
ICOM = 100mA
0.95
V+ = 1.8V
0.90
0.85
1.6
0.80
0.75
rON (Ω)
rON (Ω)
1.4
1.2
1.0
0.65
0.60
T = +25°C
0.55
V+ = 2.7V
0.8
T = +85°C
0.70
0.50
0.6
T = -40°C
0.45
V+ = 4.5V
0.40
0.4
0.35
0.2
-6
-5
-3
-4
-2
0
-1
1
2
3
4
0.30
5
-3
-2
0
-1
1
VCOM (V)
VCOM (V)
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
2
3
4
5
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
1.25
1.00
0.95
V+ = 4.3V
ICOM = 100mA
0.90
V+ = 2.7V
ICOM = 100mA
1.15
0.85
1.05
0.80
0.95
0.70
rON (Ω)
rON (Ω)
0.75
T = +85°C
0.65
0.60
T = +25°C
0.55
0.85
0.75
0.65
T = +85°C
0.55
T = +25°C
0.50
T = -40°C
0.45
0.40
0.45
0.35
0.30
-3
-2
0
-1
1
2
3
4
0.35
-5
5
T = -40°C
-4
-3
0
-1
VCOM (V)
-2
VCOM (V)
2
3
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
2.2
6
V+ = 1.8V
2.0
ANALOG SIGNAL RANGE (V)
1.4
1.2
1.0
0.8
T = +85°C
T = +25°C
-5
2
1
0
-1
-2
-3
SIGNAL MIN
-5
T = -40°C
6
3
-4
0.4
0.2
SIGNAL MAX
4
1.6
0.6
4
5
ICOM = 100mA
1.8
rON (Ω)
1
-4
-3
-2
-1
VCOM (V)
0
1
2
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
11
3
-6
1.5
2.0
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
6.0
FIGURE 14. ANALOG SIGNAL RANGE vs SUPPLY VOLTAGE
FN6582.1
November 3, 2009
ISL54063, ISL54064
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
700
V+ = 5.5V
650
ABSOLUTE VALUES
600
550
500
VINH AND VINL (V)
V+ = 4.5V
Q (pC)
450
400
350
V+ = 3.3V
300
250
200
150
100
V+ = 2.0V
50
0
-5
-4
-3
-2
-1
0
1
VCOM (V)
2
3
4
5
6
FIGURE 15. CHARGE INJECTION vs SWITCH VOLTAGE
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.5
VINH
VINL
2.0
2.5
3.0
V+ (V)
3.5
40
T = -40°C
140
T = -40°C
35
T = +25°C
T = +25°C
T = +85°C
100
25
tOFF (ns)
30
tON (ns)
120
80
20
60
15
40
10
20
5
1.8
3.3
4.5
T = +85°C
0
5.5
1.8
3.3
4.5
5.5
V+ (V)
V+ (V)
FIGURE 17. TURN - ON TIME vs SUPPLY VOLTAGE
FIGURE 18. TURN - OFF TIME vs SUPPLY VOLTAGE
0
V+ = 1.8V TO 5.5V
-10
V+ = 1.8V TO 5.5V
-20
RL = 50Ω
VIN = 1VRMS @ 0VDC OFFSET
-1
-30
-2
CROSSTALK (dB)
NORMALIZED GAIN (dB)
4.5
FIGURE 16. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
160
0
4.0
-3
-4
-5
-40
-50
OFF-ISOLATION
-60
CROSSTALK
-70
-80
-90
RL = 50Ω
VIN = 1VRMS @ 0VDC OFFSET
1k
10k
100k
1M
10M
FREQUENCY (Hz)
-100
100M
FIGURE 19. FREQUENCY RESPONSE
12
1G
-110
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 20. CROSSTALK AND OFF-ISOLATION
FN6582.1
November 3, 2009
ISL54063, ISL54064
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
Die Characteristics
0.05
SUBSTRATE POTENTIAL (POWERED UP):
GND (DFN Paddle Connection: Tie to GND or Float)
707mVRMS
0.04
TRANSISTOR COUNT:
360mVRMS
THD+N (%)
432
0.03
PROCESS:
Submicron CMOS
177mVRMS
0.02
0.01
V+ = 3.3V
VBIAS = 0VDC
RL =32Ω
0
20
100
200
1k
2k
FREQUENCY (Hz)
10k
20k
FIGURE 21. TOTAL HARMONIC DISTORTION vs FREQUENCY
13
FN6582.1
November 3, 2009
ISL54063, ISL54064
Thin Dual Flat No-Lead Plastic Package (TDFN)
L10.3x3A
2X
0.10 C A
A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
MILLIMETERS
2X
0.10 C B
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
E
A3
6
INDEX
AREA
TOP VIEW
B
//
A
C
SEATING
PLANE
0.08 C
b
0.20
0.25
0.30
5, 8
D
2.95
3.0
3.05
-
D2
2.25
2.30
2.35
7, 8
E
2.95
3.0
3.05
-
E2
1.45
1.50
1.55
7, 8
e
0.50 BSC
-
k
0.25
-
-
-
L
0.25
0.30
0.35
8
A3
SIDE VIEW
D2
(DATUM B)
0.10 C
0.20 REF
7
8
N
10
2
Nd
5
3
Rev. 3 3/06
D2/2
NOTES:
6
INDEX
AREA
1
2
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
NX k
3. Nd refers to the number of terminals on D.
(DATUM A)
4. All dimensions are in millimeters. Angles are in degrees.
E2
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N
N-1
NX b
8
e
(Nd-1)Xe
REF.
BOTTOM VIEW
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
0.10 M C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
CL
NX (b)
(A1)
L1
5
9 L
e
SECTION "C-C"
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
14
FN6582.1
November 3, 2009
ISL54063, ISL54064
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
6
INDEX AREA
A
L10.1.8x1.4A
B
N
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
MILLIMETERS
E
SYMBOL
2X
MIN
NOMINAL
MAX
NOTES
0.10 C
1
2X
2
0.10 C
TOP VIEW
0.45
0.50
0.55
-
A1
-
-
0.05
-
A3
0.10 C
C
A
0.05 C
A
0.127 REF
0.15
0.20
0.25
5
D
1.75
1.80
1.85
-
E
1.35
1.40
1.45
-
e
SEATING PLANE
A1
SIDE VIEW
(DATUM A)
PIN #1 ID
NX L
1
NX b 5
10X
0.10 M C A B
0.05 M C
2
L1
5
(DATUM B)
7
-
b
0.40 BSC
-
L
0.35
0.40
0.45
L1
0.45
0.50
0.55
-
N
10
2
Nd
2
3
Ne
3
3
θ
0
-
12
4
Rev. 3 6/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
e
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
BOTTOM VIEW
4. All dimensions are in millimeters. Angles are in degrees.
NX (b)
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
CL
(A1)
5
L
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
SECTION "C-C"
e
8. Maximum allowable burrs is 0.076mm in all directions.
TERMINAL TIP
C C
2.20
1.00
0.60
1.00
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
0.50
1.80
0.40
0.20
0.20
0.40
10 LAND PATTERN
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
15
FN6582.1
November 3, 2009
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