DATASHEET

ISL54406
Features
The Intersil ISL54406 is a Dual SPST (Single Pole/Single
Throw) switch that provides a very low distortion audio
path for a stereo headphone or high impedance line-in
load. This path can be interrupted to provide >110dB of
off-isolation for signal muting purposes into 32Ω or high
impedance loads such as consumer entertainment
system line-inputs, MP3 docking systems for powered
speaker or automotive entertainment system in-line or
cassette interfaces. Recovery from muting is instant
even with very large DC blocking capacitors.
• Single Supply Operation (VDD) . . . . +2.7V to +5.0V
• Negative Signal Swing Capability . . . . . . . . . . . -1.5V
• Low THD
- THD+N at 1mW into 32Ω Load. . . . . . . . . <0.02%
• Click and Pop Elimination . . . . . . . . . . . . . . . >60dB
• Audio Muting . . . . . . . . . . . . . . . . . . . . . . >110dB
• Low Power Consumption. . . . . . 21µW with 3V supply
• Low Power Shutdown Mode
• 1.8V Logic Compatible
The ISL54406 also has comprehensive Click and Pop
elimination measures to prevent these artifacts from
occurring in the load due to system power-up/powerdown, codec enable/disable, headphone hot plug in,
and audio muting on/off situations. The Click and Pop
elimination is effective into low and high impedance
loads and requires no external timing components to
deal with DC blocking capacitors placed between the
single supply codec and the load.
• Available in 10 Ld TDFN (3mmx3mm) or tiny
10 Ld (1.8mmx1.4mm) µTQFN Package
• Pb-Free (RoHS Compliant)
Applications
• Consumer Entertainment Systems
• MP3 and other Personal Media Players
• Cellular/Mobile Phones
The ISL54406 is available in a 10 Ld TDFN (3mmx3mm)
or a tiny 10 Ld µTQFN (1.8mmx1.4mm) ultra-thin
package. It operates over a temperature range of -40 to
+85°C.
• PDA’s
• Audio Switching and Muting
Related Literature*(see page 14)
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”.
• Application Note AN1368 “ISL54406EVAL1Z
Evaluation Board User’s Manual”
Application Block Diagram
3.3V
0.1µF
µCONTROLLER
VDD
LOGIC
CONTROL
LOUT
CLICK AND POP
CIRCUITRY
ISL54406
1
SEL2
LIN
ROUT
July 14, 2010
FN6578.1
SEL1
AUDIO
CODEC
RIN
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54406
Stereo Click and Pop Eliminator with Audio Muting
ISL54406
Pin Configurations
(Note 1)
ISL54406
(10 Ld 1.8x1.4 µTQFN)
TOP VIEW
ISL54406
(10 Ld 3x3 TDFN)
TOP VIEW
VDD
1
SEL2
2
LOUT
3
ROUT
4
GND
PD
LOGIC
CONTROL
LSHUNT
CLICK
AND
POP
10
SEL1
9
N.C.
N.C.
8
8
N.C.
SEL1
9
7
LIN
VDD 10
6
5
RSHUNT
N.C.
LIN
7
6
LOGIC
CONTROL
LSHUNT
1
RIN
CLICK
AND
POP
SEL2
5
RIN
4
GND
3
ROUT
RSHUNT
2
LOUT
NOTE:
1. ISL54406 Switches Shown for SEL1 = Logic “1” and SEL2 = Logic “1”.
Truth Table
Pin Descriptions
ISL54406
ISL54406
SEL2
SEL1
LIN/
RIN
LSHUNT/
RSHUNT
CLICK
AND POP
0
0
OFF
OFF
Inactive
0
1
OFF
ON
Active
TDFN
µTQFN
NAME
MODE
1
10
VDD
Power Supply
FUNCTION
Shutdow
n
2
1
SEL2
Logic Control 2
3
2
LOUT
Audio Left Output
Click and
Pop
4
3
ROUT
Audio Right Output
5
4
GND
IC Ground Connection
1
0
OFF
ON
Inactive
Mute
6
5
RIN
Audio Right Input
1
1
ON
OFF
Inactive
Audio
7
6
LIN
Audio Left Input
8, 9
7, 8
N.C.
No Connection
10
9
SEL1
Logic Control 1
PD
-
PD
SEL1 and SEL2: Logic “0” when ≤ 0.5V, Logic “1” when ≥
1.4V
2
Thermal Pad. Tie to
Ground or Float
FN6578.1
July 14, 2010
ISL54406
Ordering Information
PART
NUMBER
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL54406IRUZ-T (Notes 2, 3)
6
-40 to +85
10 Ld 1.8x1.4 µTQFN
L10.1.8x1.4A
ISL54406IRTZ (Note 4)
4406
-40 to +85
10 Ld 3x3 TDFN
L10.3x3A
ISL54406IRTZ-T (Notes 2, 4)
4406
-40 to +85
10 Ld 3x3 TDFN
L10.3x3A
ISL54406EVAL1Z
Evaluation Board
NOTES:
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL54406. For more information on MSL please
see techbrief TB363.
3
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ISL54406
Absolute Maximum Ratings
Thermal Information
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 5.5V
Input Voltages
LIN, RIN (Note 6). . . . . . . . . . . . . . -2V to ((VDD) + 0.3V)
SEL1 (Note 6) . . . . . . . . . . . . . . . -0.3V to ((VDD) + 0.3V)
SEL2 (Note 6) . . . . . . . . . . . . . . . -0.3 to ((VDD) + 0.3V)
Output Voltages
LOUT, ROUT (Note 6) . . . . . . . . . . . -2V to ((VDD) + 0.3V)
Continuous Current . . . . . . . . . . . . . . . . . . . . . . ±150mA
Peak Current
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . ±300mA
ESD Rating:
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . >5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . >300V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . >1.5kV
Latch-up Tested per JEDEC; Class II Level A . . . . . at +85°C
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
10 Ld µTQFN (Note 7, 8) . . . . . . . .
160
105
10 Ld TDFN (Notes 9, 10) . . . . . . .
55
18
Maximum Junction Temperature (Plastic Package). . +150°C
Maximum Storage Temperature Range. . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
6. Signals on LIN, RIN, LOUT, ROUT, SEL1, and SEL2 exceeding VDD or GND by specified amount are clamped. Limit current to
maximum current ratings.
7. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
8. For θJC, the “case temp” location is taken at the package top center.
9. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
10. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.0V, GND = 0V, VSELx_H = 1.4V,
VSELx_L= 0.5V, (Notes 11), Unless Otherwise Specified
Boldface limits apply over the operating temperature range,
-40°C to +85°C.
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 12, 13) TYP (Notes 12, 13) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Input Signal Range,
VANALOG
VDD = 3.3V, VSEL2 = 1.4V, VSEL1 = 1.4V
Full
-1.5
-
1.5
V
ON-Resistance, rON
VDD = 3.0V, VSEL2 = 1.4V, VSEL1 = 1.4V
IXOUT = 40mA, VLIN or VRIN = -0.85V to
0.85V, (See Figure 2, Note 16)
+25
-
2.5
2.8
Ω
Full
-
-
4.0
Ω
VDD = 3.0V, VSEL2 = 1.4V, VSEL1 = 1.4V
IXOUT = 40mA, VLIN or VRIN = -0.85V to
0.85V, (Notes 14, 16)
+25
-
2
-
mΩ
Full
-
-
rON Matching Between
Channels, ΔrON
VDD = 3.0V, VSEL2 = 1.4V, VSEL1 = 1.4V
IXOUT = 40mA, VLIN or VRIN = Voltage at
max rON over signal range of -0.85V to
0.85V, (Note 15, 16)
+25
-
0.09
0.25
Ω
Full
-
-
0.35
Ω
Discharge Pull-Down
Resistance, RL, RR
VDD = 3.6V, VSEL2 = 1.4V, VSEL1= 1.4V ,
VROUT or VLOUT = -0.85V, 0.85V. Measure
current through the discharge pull down
resistor and calculate resistance value.
+25
-
240
-
kΩ
Click and Pop Discharge
Resistance
VDD = 3.0V, VSEL2 = 0V, VSEL1= 1.4V,
VINL or V INR = -0.85V, 0.85V. Measure
current through the Click and Pop
discharge resistance and calculate
resistance value.
+25
-
35
-
Ω
rON Flatness, rFLAT(ON)
4
mΩ
FN6578.1
July 14, 2010
ISL54406
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.0V, GND = 0V, VSELx_H = 1.4V,
VSELx_L= 0.5V, (Notes 11), Unless Otherwise Specified (Continued)
Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 12, 13) TYP (Notes 12, 13) UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
VDD = 2.7V, VSEL1= 2.7V, RL = 50Ω,
CL = 10pF, (See Figure 1)
+25
-
5
-
µs
Turn-OFF Time, tOFF
VDD = 2.7V, VSEL1= 2.7V, RL = 50Ω,
CL = 10pF, (See Figure 1)
+25
-
45
-
ns
OFF-Isolation, Mute Mode
VDD = 3.0V, VSEL2 = 0V, VSEL1= 3.0V,
VLIN or VRIN = 0.707VRMS, RL = 32Ω,
f = 20Hz to 20kHz, (See Figure 3).
+25
-
110
-
dB
VDD = 3.0V, VSEL2 = 0V, VSEL1= 3.0V,
VLIN or VRIN = 0.707VRMS, RL = 20kΩ,
f = 20Hz to 20kHz, (See Figure 3).
+25
-
110
-
dB
Crosstalk
RIN to LOUT, LIN to ROUT
VDD = 3.0V, VSEL2 = 3.0V, VSEL1= 3.0V,
RL = 32Ω, f = 20Hz to 20kHz, VLIN or
VRIN = 0.707VRMS (2VP-P),
(See Figure 4)
+25
-
-90
-
dB
Total Harmonic Distortion
VDD = 3.0V, f = 20Hz to 20kHz,
VSEL2 = 3.0V, VSEL1 = 3.0V, VLIN or
VRIN = 0.36VRMS (1VP-P), RL = 32Ω
+25
-
0.03
-
%
VDD = 3.0V, f = 20Hz to 20kHz,
VSEL2 = 3.0V, VSEL1 = 3.0V, VLIN or
VRIN = 0.707VRMS (2VP-P), RL = 32Ω
+25
-
0.06
-
%
VDD = 3.0V, VSEL1= 3.0V, VSEL2 = 0V to
3.0V DC step, RL = 20kΩ, VINL or
VINR = 0VDC to 1.5VDC step
(see Figure 6)
+25
-
>60
-
dB
VDD = 3.0V, VSEL1= 3.0V, VSEL2 = 0V to
3.0V DC step, RL = 32Ω, VINL or
VINR = 0VDC to 1.5VDC step
(see Figure 6)
+25
-
>70
-
dB
Power Supply Range, VDD
Full
2.7
3.6
V
Positive Supply Current, IDD VDD = 3.6V, VSEL2 = 1.4V, VSEL1 = 1.4V
+25
-
7
10
µA
Full
-
-
15
µA
25
-
-
50
nA
Click and Pop Reduction
(Note 17)
POWER SUPPLY CHARACTERISTICS
Shutdown Current, ISHDN
VDD = 3.6V, VSEL2 = Float, VSEL1 = Float
DIGITAL INPUT CHARACTERISTICS
SELx Voltage Low, VSELx_L
VDD = 2.7V to 3.6V
Full
-
-
0.5
V
SELx Voltage High, VSELx_H
VDD = 2.7V to 3.6V
Full
1.4
-
-
V
Input Low Current, ISEL2L,
ISEL1L
VDD = 3.6V, VSEL2 = 0V or Float,
VSEL1 = 0V or Float
Full
-20
2
20
nA
5
FN6578.1
July 14, 2010
ISL54406
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.0V, GND = 0V, VSELx_H = 1.4V,
VSELx_L= 0.5V, (Notes 11), Unless Otherwise Specified (Continued)
Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
TEMP
MIN
MAX
(°C) (Notes 12, 13) TYP (Notes 12, 13) UNITS
TEST CONDITIONS
Input High Current, ISEL2H,
ISEL1H
VDD = 3.6V, VSEL2 = 3.6V, VSEL1 = 3.6V
Full
-2
1
2
µA
SEL1 Pull-Down Resistor,
RSEL1
VDD = 3.6V, VSEL2 = 3.6V, VSEL1 = 0V
Full
-
4
-
MΩ
SEL2 Pull-Down Resistor,
RSEL2
VDD = 3.6V, VSEL2 = 0V, VSEL1 = 3.6V
Full
-
4
-
MΩ
NOTES:
11. VSELx = Input voltage to perform proper function.
12. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this
data sheet.
13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
14. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal
range.
15. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel
with lowest max rON value.
16. Limits established by characterization and are not production tested.
17. Click and Pop Reduction specifications are limited by test equipment.
Test Circuits and Waveforms
VDD
VSEL2H
LOGIC
INPUT
VSEL2L
tr < 20ns
tf < 20ns
50%
VLIN/RIN
SWITCH
INPUT
tOFF
SEL1
VLOUT/ROUT
IN
OUT
SEL2
SWITCH
INPUT VINPUT
VOUT
90%
SWITCH
OUTPUT
0.1µF
90%
VSEL2
GND
RL
50Ω
CL
10pF
0V
tON
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
----------------------V OUT = V
(INPUT) R + r
L
ON
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
6
FN6578.1
July 14, 2010
ISL54406
Test Circuits and Waveforms (Continued)
VDD
VDD
0.1µF
Repeat test for all switches.
rON = V1/40mA
SEL2
SIGNAL
GENERATOR
SEL1
LIN OR RIN
0.1µF
LOUT OR
ROUT
LIN OR RIN
ANALYZER
VDD
VIN
RL
SEL1
SEL2
V1
40mA
0V OR
FLOAT
LOUT OR
ROUT
GND
GND
FIGURE 2. rON TEST CIRCUIT
FIGURE 3. OFF ISOLATION CIRCUIT
VDD
0.1µF
SEL1
SIGNAL
GENERATOR
LOUT OR
ROUT
LIN OR RIN
32Ω
SEL2
VDD
ROUT OR
LOUT
RIN OR LIN
ANALYZER
GND
0Ω
RL
FIGURE 4. CROSSTALK TEST CIRCUIT
3.0V
0.1µF
0VDC TO 3VDC STEP
1Hz
VDD
SEL1
SEL2
LOUT
CLICK
AND
POP
ROUT
20kΩ
LIN
RIN
220µF
VINL
VINR
220µF
32Ω
GND
0V TO 1.5V
DC STEP OR
1.5V TO 0V
DC STEP
1Hz
SEL2 Waveform: Rising Edge @ 100ms after 0V to 1.5V DC Step
Falling Edge @ 100ms before 1.5V to 0V DC Step
*See Figures 18 and 19
FIGURE 5. CLICK AND POP TEST CIRCUIT #1
7
FN6578.1
July 14, 2010
ISL54406
Test Circuits and Waveforms (Continued)
FLOAT FLOAT
SEL1 SEL2
0V TO 3.0V
DC STEP OR
3.0V TO 0V
DC STEP
1Hz
VDD
LOUT
LIN
CLICK
AND
POP
ROUT
20kΩ
220µF
RIN
220µF
20kΩ
1.5V
GND
Power Supply Turn-On/Turn-Off Click and Pop Transient Test
*See Figure 17
FIGURE 6. CLICK AND POP TEST CIRCUIT #2
8
FN6578.1
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ISL54406
Application Block Diagram
3.3V
0.1µF
VDD
SEL1
LOGIC CONTROL
4MΩ
LSHUNT
220kΩ
RIGHT
SPEAKER
4MΩ
6Ω
LOUT
LEFT
SPEAKER
LIN
CLICK AND POP
CIRCUITRY
ROUT
µCONTROLLER
SEL2
220µF
220µF
AUDIO
CODEC
RIN
220kΩ
6Ω
RSHUNT
GND
Detailed Description
The ISL54406 device is a dual single pole-single throw
(SPST) analog switch that operates from a single DC
power supply in the range of +2.7V to +5V. It was
designed to function as a transient suppressor to
eliminate Click and Pop noise on headphones. It comes in
a 10 Ld (3mmx3mm) TDFN or a tiny 10 Ld
(1.8mmx1.4mm) µTQFN package for use in MP3 players,
PDAs, cellphones, and other personal media players.
The part consist of a pair of 2.5Ω audio switches. The
audio switches can accept signals that swing below
ground by as much as -1.5V. They were designed to pass
audio left and right stereo signals that are ground
referenced with minimal distortion.
The ISL54406 was specifically designed for MP3 players,
personal media players and cellphone applications that
require but do not have Click and Pop elimination. See
“Application Block Diagram” on page 9.
The ISL54406 contains logic control pins SEL1 and SEL2
that will determine the state of the switch. See the “Truth
Table” on page 2 for a description of each state. A
detailed description of the audio switches are provided in
the section that follows.
Audio Switches
The two 2.5Ω audio switches (L, R) are designed to pass
signals that swing 1.5V above and below ground.
Crosstalk between the audio switches is -90dB over the
audio band. These switches have excellent off-isolation of
110dB over the audio bandwidth with a 32Ω load.
Over a signal range of ±1V (0.707VRMS) with VDD >
2.7V, these switches have an extremely low rON
resistance variation (0.03Ω). They can pass ground
referenced audio signals with very low distortion
(<0.04% THD+N) when delivering 4mW into a 32Ω
9
ISL54406
headphone speaker load. See Figures 10, 11, 12 and 13
for THD+N performance curves.
The audio drivers should be connected at the LIN and RIN
side of the switch and the speaker loads should be
connected at the LOUT and ROUT side of the switch for
proper Click and Pop elimination. The switches have Click
and Pop circuitry on the LIN and RIN side that is activated
when the SEL1 pin is driven High and SEL2 pin is driven
Low. The audio switches are turned OFF in this state. The
ISL54406 should be put in this mode before powering down
or powering up of the audio source drivers. The high
off-isolation of the audio switches along with the Click and
Pop circuitry will prevent the transients generated during
power-up and power-down of the audio source from getting
through to the headphones, thus eliminating Click and Pop
noise in the headphones. The audio switches are turned ON
and the Click and Pop circuitry disabled whenever SEL1 and
SEL2 is driven High.
ISL54406 Operation
The discussion that follows will describe using the
ISL54406 in the “Application Block Diagram” on page 9.
LOGIC CONTROL
The state of the ISL54406 device is determined by the
logic level at the SEL1 and SEL2 pins. The part has four
states or modes of operation. The Audio Playback Mode,
Audio Mute Mode, Click and Pop Mode, and Shutdown
Mode. Refer to “Truth Table” on page 2 for the logic state
of each mode of operation. The SEL1 and SEL2 pins are
internally pulled low through 4MΩ resistors to ground and
can be left floating to pull the logic pins Low.
Logic Control Voltage Levels:
SEL1 and SEL2 = Logic “0” (Low) when ≤ 0.5V or
Floating.
SEL1 and SEL2 = Logic “1” (High) when ≥ 1.4V
FN6578.1
July 14, 2010
ISL54406
Audio Playback Mode
If the SEL1 and SEL2 pins are Logic “1”, the device will be
in the Audio Playback mode. In Audio Playback mode the
LIN (left) and RIN (right) 2.5Ω audio switches are
connected to LOUT and ROUT respectively, and the audio
Click and Pop circuitry is inactive (high impedance).
When headphones are connected to the LOUT and ROUT
outputs of the ISL54406, the audio source drives the
headphones with low distortion audio.
Audio Mute Mode
If SEL1 is Logic “0” and SEL2 is Logic “1”, the device will
be in the Audio Mute Mode. In Audio Mute Mode the
audio switches are OFF (high impedance), the audio Click
and Pop shunt circuitry is OFF (high impedance), and the
LOUT and ROUT pins are shorted through 6Ω resistors to
ground. Off Isolation performance in Audio Mute Mode
gives a 110 dB signal reduction across a 32Ω load when
driving with a 0.707VRMS signal at the switch input.
Click and Pop Mode
Note: Click and Pop Mode should not be used for audio
muting applications. In Click and Pop Mode, a low
impedance (35Ω) path to ground at the LIN/RIN inputs
will degrade Off Isolation performance (see Figure 14).
If SEL1 is Logic “1” and SEL2 is Logic “0”, the device will
go into Click and Pop Mode. This mode is optimal when
powering up or down the audio sources. In Click and Pop
Mode the audio in-line 2.5Ω switches are OFF (high
impedance). The LOUT and ROUT pins are shorted
through 6Ω resistors to ground and the LIN and RIN are
shunted through 35Ω resistors to ground (Click and Pop
circuitry is active).
Before powering down or powering up of the audio
source drivers, the ISL54406 should be put in the Click
and Pop Mode. In Click and Pop Mode, transients
generated at the LIN and RIN pins due to a DC step
voltage at the audio drivers will not pass through the
ISL54406 audio switches, preventing Click and Pop noise
to the load.
Shutdown Mode
If SEL1 and SEL2 pins are Logic “0”, the device will enter
a low powered Shutdown (SHDN) Mode. In SHDN, the
audio switches are OFF, the 6Ω path is high impedance,
the Click and Pop circuitry is inactive, and the device will
draw a typical supply current of 5nA.
Note: When the logic inputs are floated, the ISL54406
will automatically be placed in SHDN mode due to the
internal 4MΩ pull down resistors on the logic pins.
Note: In Shutdown Mode, the Off-Isolation of the audio
switch degrades in performance compared to Audio Mute
10
Mode. In SHDN, the negative charge pumps that permit
the signal to swing below ground are turned off to reduce
power consumption, thus any negative signal swing at
the LIN and RIN will appear at the LOUT and ROUT pins.
The device should not be placed into SHDN when the
source is still active or for high Off-Isolation performance.
CLICK AND POP OPERATION
Single supply audio sources are biased at a DC offset
that generates transients during power on/off of the
source. This DC transient is coupled into the load through
a blocking capacitor (see “Application Block Diagram” on
page 9). When the source is off and suddenly turned on
with a DC offset, the capacitor will develop a voltage
across it that is equal to the DC offset. If the switch is in
Audio mode when this occurs, a transient discharge will
occur in the speaker, generating a Click and Pop noise.
Proper elimination of Click and Pop transients requires
that the ISL54406 be placed in Click and Pop Mode
before the audio source is turned on or off. This allows
any transients generated by the source to be discharged
through the Click and Pop circuitry first. With a typical DC
blocking capacitor of 220µF and the Click and Pop
circuitry designed to have a resistance of 35Ω, allowing a
100ms dead-time for discharging a transient before
placing the switch in Audio mode will eliminate the DC
transient generated by the blocking capacitor.
Note: The ISL54406 should not be brought into Audio
Playback Mode directly from Shutdown Mode and vice
versa. A DC transient may occur at the LOUT/ROUT pins
when brought from Shutdown directly to Audio Playback
mode. The recommended procedure is to place the
ISL54406 into Mute mode for at least 100ms when
entering or leaving Audio Playback mode.
Power supply considerations
The power supply connected at VDD and GND provides
power to the ISL54406 part. In a typical application VDD
will be in the range of +2.7V to +5.0V and will be
connected to the battery or LDO of the MP3 player or
cellphone. A 0.1µF local decoupling capacitor should be
placed near the VDD pin of the IC to eliminate power
supply transients.
Before power-up and power-down of the ISL54406 part,
the SEL1 and SEL2 logic control pins should be driven to
Logic “0” or left floating. In a high impedance state, 4MΩ
internal pull down resistors on the SEL1 and SEL2 pins
will set the ISL54406 logic pins to “0”. This will put the
switch in the SHDN state which turns all switches OFF
and deactivates the Click and Pop circuitry which will
minimize power supply currents and increase battery life.
FN6578.1
July 14, 2010
ISL54406
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified
2.61
4.0
IOUT = 40mA
3.8
3.4
IOUT = 40mA
3.2
VDD = 3.0
2.59
rON (Ω)
rON (Ω)
+85°C
3.6
VDD = 2.7
2.60
VDD = 3.3
2.58
VDD = 3.0V
3.0
2.8
2.6
+25°C
2.4
2.2
2.57
2.0
VDD = 3.6
1.8
2.56
-1.0 -0.8 -0.6 -0.4 -0.2
0
0.2
0.4
0.6
0.8
-40°C
1.6
-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2
1.0
VOUT (V)
VOUT (V)
FIGURE 7. ON-RESISTANCE vs SWITCH VOLTAGE vs
SUPPLY VOLTAGE
0.068
FIGURE 8. ON-RESISTANCE vs SWITCH VOLTAGE vs
TEMPERATURE
0.10
RLOAD = 32Ω
VLOAD = 0.707VRMS
0.066
1.06VRMS
0.884VRMS
0.08
VDD = 3.0V
0.707VRMS
VDD = 3.3V
VDD = 2.7V
0.062
THD+N (%)
THD+N (%)
0.064
VDD = 3.6V
0.060
20
200
2k
FREQUENCY (Hz)
RLOAD = 32Ω
VDD = 3V
RMS VOLTAGES AT LOAD
200
2k
FREQUENCY (Hz)
20k
FIGURE 10. THD+N vs SIGNAL LEVELS vs FREQUENCY
RLOAD = 32Ω
FREQUENCY = 1kHz
VDD = 3V
0.10
0.10
0.08
RLOAD = 32Ω
FREQUENCY = 1kHz
VDD = 3V
0.08
0.06
THD+N (%)
THD+N (%)
0.354VRMS
20
20k
FIGURE 9. THD+N vs SUPPLY VOLTAGE vs FREQUENCY
0.20
0.04
0.02
0.058
0.056
0.06
0.04
0.02
0.06
0.04
0.03
0.02
0.01
0.01
0.003
0.12 0.23 0.35 0.47 0.58 0.70 0.82 0.93 1.05 1.16
OUTPUT VOLTAGE (VRMS)
FIGURE 11. THD+N vs OUTPUT VOLTAGE
11
0.008
1
2
3
4
5
6
7
8
9
10
20
30
OUTPUT POWER (mW)
FIGURE 12. THD+N vs OUTPUT POWER
FN6578.1
July 14, 2010
ISL54406
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified (Continued)
0
NORMALIZED GAIN (dB)
-40
GAIN (dB)
-0.5
-1.0
-1.5
-2.0
20
VDD = 3V
RL = 32Ω
VIN = 0.707 VRMS
100 200
-60
-80
-100
MUTE MODE
-120
-140
500
1k
10k 20k
2k
CLICK AND POP MODE
-160
RL = 32Ω
VIN = 0.2VP-P TO 2VP-P
500 1k 2k
100 200
FREQUENCY (Hz)
20
FREQUENCY (Hz)
5k
10k 20k
FIGURE 14. OFF-ISOLATION
FIGURE 13. INSERTION LOSS
-40
1V/DIV
VDD
-80
VOLTAGE (V)
NORMALIZED GAIN (dB)
-60
-100
-120
-140
-160
20
VIN = 1.5V
SEL1 = SEL2 = 0V
VOUT
RL = 32Ω
VIN = 0.2VP-P TO 2VP-P
100 200
500
1k
2k
5k
10k 20k
TIME (s) 200ms/DIV
FREQUENCY (Hz)
FIGURE 15. CROSSTALK
12
FIGURE 16. POWER-UP/POWER-DOWN CLICK AND
POP TRANSIENT
FN6578.1
July 14, 2010
ISL54406
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified (Continued)
SEL2
SEL2
2V/DIV
2V/DIV
VINR
VOLTAGE (V)
VOLTAGE (V)
VINL
VLIN
200mV/DIV
VLOUT
200mV/DIV
VRIN
200mV/DIV
VROUT
200mV/DIV
TIME (s) 100ms/DIV
FIGURE 17. 20kΩ CLICK AND POP REDUCTION
TIME (s) 100ms/DIV
FIGURE 18. 32Ω CLICK AND POP REDUCTION
Die Characteristics
SUBSTRATE AND TDFN THERMAL PAD
POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
98
PROCESS:
Submicron CMOS
13
FN6578.1
July 14, 2010
ISL54406
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
06/4/10
FN6578.1
On page 3, added evaluation board part number to “Ordering Information” table.
On page 4 in “Thermal Information”, changed µTQFN theta JC value from 62 to 105.
Added Notes 7 and 8 to reference uTQFN package.
On page 5, changed “Shutdown Current, ISHDN” limit from 5nA to 50nA.
Converted to new Intersil template. Changes include:
Added Note 5 to “Ordering Information” on page 3.
“Pin Descriptions” on page 2, updated to show the thermal pad.
“Absolute Maximum Ratings” on page 4, added latch-up level.
Added boldface limits text in conditions of Spec Table and bolded Min
and Max over-temp Limits
Updated Over-temp Note to meet standard verbiage
Added “Products” on page 14.
Added “Revision History” on page 14.
5/28/08
FN6578.0
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL54406
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at
http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN6578.1
July 14, 2010
ISL54406
L10.1.8x1.4A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 3/10
1.80
B
6
PIN #1 ID
A
1
1
1.40
3
10
0.50
6 PIN 1
INDEX AREA
9 X 0.40
2
10X 0.20 4
0.10 M C A B
0.05 M C
0.70
8
5
0.10
7
2X
4X 0.30
6
6X 0.40
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
MAX. 0.55
C
SEATING PLANE
0.08 C
(9 X 0.60)
1
(10X 0.20)
(4X 0.30)
3
10
8
(0.70)
SIDE VIEW
(0.70)
C
5
6
0 .1 27 REF
7
(6X 0.40)
PACKAGE OUTLINE
0-0.05
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
JEDEC reference MO-255.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
15
FN6578.1
July 14, 2010
ISL54406
Thin Dual Flat No-Lead Plastic Package (TDFN)
L10.3x3A
2X
0.10 C A
A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
MILLIMETERS
2X
0.10 C B
E
B
//
A
C
SEATING
PLANE
D2
(DATUM B)
6
INDEX
AREA
0.10 C
0.08 C
A3
SIDE VIEW
7
8
MAX
NOTES
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
0.20 REF
b
0.20
0.25
1
0.30
5, 8
D
2.95
3.0
3.05
-
D2
2.25
2.30
2.35
7, 8
E
2.95
3.0
3.05
-
E2
1.45
1.50
1.55
7, 8
e
0.50 BSC
-
k
0.25
-
-
-
L
0.25
0.30
0.35
8
N
10
2
Nd
5
3
Rev. 4 8/09
NOTES:
2
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
NX k
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
E2
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N
N-1
NX b
e
(Nd-1)Xe
REF.
BOTTOM VIEW
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
0.10 M C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
CL
NX (b)
NOMINAL
D2/2
(DATUM A)
8
MIN
A3
6
INDEX
AREA
TOP VIEW
SYMBOL
(A1)
L1
5
9 L
( 2.30 )
e
SECTION "C-C"
C C
( 2.00 )
TERMINAL TIP
FOR ODD TERMINAL/SIDE
( 10X 0.50)
(1.50)
( 2.90 )
Pin 1
(8x 0.50)
( 10X 0.25)
TYPICAL RECOMMENDED LAND PATTERN
16
FN6578.1
July 14, 2010
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