DATASHEET

NS
DESIG
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DED F CEMENT PA
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M
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NOT R MENDED R 603 April 24, 2009
Data Sheet
M
ISL98
R EC O
4-Channel Integrated LCD Supply
Features
The ISL97651 represents a high power, integrated LCD
supply IC targeted at large panel LCD displays. The
ISL97651 integrates a high power, 4.4A boost converter for
AVDD generation, an integrated VON charge pump, a VOFF
charge pump driver, VON slicing circuitry and a buck
regulator with 2A switch for logic generation.
• 4V to 5.5V input supply
The ISL97651 have been designed for ease of layout and
low BOM cost. Supply sequencing is integrated for both
AVDD -> VOFF -> VON and AVDD/VOFF -> VON sequences.
The TFT power sequence uses a separate enable to the
logic buck regulator for maximum flexibility.
Peak efficiencies are 90% for boost and 92% for buck while
operating from a 4V to 5.5V input supply. The current mode
buck offers superior line and load regulation. Available in the
36 Ld QFN package, the ISL97651 is specified for ambient
operation over the -40°C to +105°C temperature range.
ISL97651
FN7493.3
• AVDD boost up to 20V, with integrated 4.4A FET
• Integrated VON charge pump, up to 34VOUT
• VOFF charge pump driver, down to -18V
• VLOGIC buck down to 1.2V, with integrated 2A FET
• Automatic start-up sequencing
- AVDD -> VOFF -> VON or AVDD/VOFF -> VON
- Independent logic enable
• VON slicing
• Thermally enhanced thin QFN package (6mmx6mm)
• Pb-free (RoHS compliant)
Applications
• LCD monitors (15”+)
Pinout
• LCD-TVs (40”+)
• Industrial/medical LCD displays
28 NC
29 CDEL
• Notebook displays (up to 16”)
30 ENL
31 DELB
32 CM1
33 VIN2
34 FBB
35 EN
36 NC
ISL97651
(36 LD TQFN)
TOP VIEW
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
VIN1 1
27 AGND
LX1 2
26 PGND1
LX2 3
25 PGND2
ISL97651ARTZ-TK ISL976 51ARTZ 36 Ld 6x6 TQFN L36.6x6
24 VINL
NOTES:
CB 4
THERMAL
PAD
LXL 5
23 NOUT
VSUP 6
22 PGND3
1
ISL976 51ARTZ 36 Ld 6x6 TQFN L36.6x6
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
NC 18
C2+ 17
C2- 16
C1+ 15
19 FBP
C1- 14
CTL 9
POUT 13
20 VREF
COM 12
CM2 8
DRN 11
21 FBN
NC 10
FBL 7
ISL97651ARTZ-T
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006-2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL97651
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Maximum Pin Voltages, All Pins Except Below . . . . . . . . . . . . . 6.5V
LX1, LX2, VSUP, NOUT, DELB, C1-, C2- . . . . . . . . . . . . . . . . .24V
C1- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14V
CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13V
DRN, COM, POUT, C1+, C2+ . . . . . . . . . . . . . . . . . . . . . . . . .36V
CB-VINL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
Thermal Resistance
JA (°C/W)
JC (°C/W)
6x6 QFN Package (Notes 3, 4) . . . . . .
30
2.5
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Power Dissipation
TA 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3W
TA = +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8W
TA = +85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.3W
TA = +100°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.8W
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Input Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . . . . . 4V to 5.5V
Boost Output Voltage Range, AVDD . . . . . . . . . . . . . . . . . . . . +20V
VON Output Range, VON . . . . . . . . . . . . . . . . . . . . . . +15V to +32V
VOFF Output Range, VOFF . . . . . . . . . . . . . . . . . . . . . . -15V to -5V
Logic Output Voltage Range, VLOGIC . . . . . . . . . . . +1.5V to +3.3V
Input Capacitance, CIN . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 x 10µF
Boost Inductor, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH to 10µH
Output Capacitance, COUT . . . . . . . . . . . . . . . . . . . . . . . . 2 x 22µF
Buck Inductor, L2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH to 10µH
Operating Ambient Temperature Range . . . . . . . . -40°C to +105°C
Operating Junction Temperature . . . . . . . . . . . . . . -40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
VIN = 5V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over-temperature from -40°C to +105°C; Parameters
with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY PINS
VIN
Supply Voltage (VIN1 and VIN2)
4
5
5.5
V
VINL
Logic Supply Voltage
4
5
5.5
V
VSUP
Charge Pumps and VON Slice
Positive Supply
4
20
V
IVIN
Quiescent Current into VIN
Enabled, No switching
3
mA
Disabled
10
µA
1.0
mA
Disabled
10
µA
Enabled, No switching and VPOUT = VSUP
0.5
mA
Disabled
10
µA
IINL
ISUP
Logic Supply Current
VSUP Supply Current
Enabled, No switching
0.4
VLOR
Undervoltage Lockout Threshold
VIN rising
2.0
2.75
2.9
V
VLOF
Undervoltage Lockout Threshold
VIN falling
1.9
2.2
2.5
V
VREF
Reference Voltage
TA = +25°C
1.19
1.205
1.235
V
1.187
1.205
1.238
V
1010
1200
1400
kHz
20
V
fOSC
Oscillator Frequency
AVDD BOOST DMax, Maximum Duty Cycle: Minimum 84%
VBOOST
Boost Output Range
ILX
LX Leakage Current
LX = 0V and 24V
-10
.01
10
µA
IBOOST
Boost Switch Current
Current limit
4.4
4.8
6.3
A
2
1.25*VIN
FN7493.3
April 24, 2009
ISL97651
Electrical Specifications
PARAMETER
VIN = 5V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over-temperature from -40°C to +105°C; Parameters
with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested. (Continued)
DESCRIPTION
EFFBOOST
Peak Efficiency
rDS(ON)
Switch ON-Resistance
VBOOST/VIN
Line Regulation
VBOOST/IOUT
Load Regulation
VFBB
Boost Feedback Voltage
CONDITIONS
MIN
See graphs and component
recommendations
ACCBOOST
AVDD Output Accuracy
TA = +25°C
tSS
Soft-start Period for AVDD
CDEL = 220nF
MAX
90
UNIT
%
70
100
m
0.4
1.5
%/V
0.1
0.5
%
1.192
1.205
1.218
V
1.188
1.205
1.222
V
+1.5
%
PI mode, R1 = 10k and C3 = 4.7nF over a
load range of 0mA to 300mA (tested),
0-ILIMIT_ONSET (by design)
TA = +25°C
TYP
-1.5
9.6
ms
VLOGIC BUCK
DMAX_buck typical maximum duty cycle = 0.85*(VINL-ILOAD*0.3) ILOAD_min, Minimum 1mA for VINL-VBUCK >1.5V, 5mA otherwise
VBUCK
Buck Output Voltage
Output current = 0.5A
VREF
ILXL
LX Leakage Current
LX = 0V and 18V
-10
.01
IBUCK
Buck Switch Current
Current limit
2.0
2.7
A
EFFBUCK
Peak Efficiency
See graphs and component
recommendations
92
%
RDS-ONBK
Switch ON-Resistance
VBUCK/VIN
Line Regulation
VBUCK/IOUT
Load Regulation
VFBL
FBL Regulation Voltage
PI mode, R1 = 2k and C3 = 4.7nF over a
load range of 0mA to 300mA (tested),
0-ILIMIT_ONSET (by design)
4
V
10
µA
200
455
m
0.1
1
%/V
0.04
0.5
%
IDRVL = 1mA, TA = +25°C
1.176
1.2
1.224
V
IDRVL = 1mA
1.174
1.2
1.226
V
+2
%
ACCLOGIC
VLOGIC Output Accuracy
TA = +25°C
tSS(L)
Soft-Start Period for V(Logic)
C(VREF) = 220nF (Note - no soft-start if EN
asserted HIGH before ENB)
-2
0.5
ms
NEGATIVE (VOFF) CHARGE PUMP
VOFF
VOFF Output Voltage Range
2X Charge Pump
ILOAD_NCP_MIN
External Load Driving Capability
VSUP > 5V
rON(NOUT)H
High-Side Driver ON-Resistance at
NOUT
I(NOUT) = +60mA
10

rON(NOUT)L
Low-Side Driver ON-Resistance at
NOUT
I(NOUT) = -60mA
5

IPU(NOUT)LIM
Pull-up Current Limit in NOUT
V(NOUT) = 0V to V(SUP) - 0.5V
IPD(NOUT)LIM
Pull-down Current Limit in NOUT
V(NOUT) = 0.36V to V(VSUP)
I(NOUT)LEAK
Leakage Current in NOUT
V(FBN) < 0 or EN = LOW
VFBN
FBN Regulation Voltage
IDRVN = 0.2mA, TA = +25°C
0.173
IDRVN = 0.2mA
0.171
ACCN
VOFF Output Accuracy
D_NCP_max
Max Duty Cycle of the Negative
Charge Pump
rPD(FBN)OFF
Pull-Down Resistance, Not Active
3
IOFF = 1mA, TA = +25°C
-VSUP+1.4V
0
30
60
mA
270
-200
mA
-60
mA
2
µA
0.203
0.233
V
0.203
0.235
V
+3
%
-2
-3
50
I(FBN) = 500µA
2
V
3
%
4
k
FN7493.3
April 24, 2009
ISL97651
Electrical Specifications
PARAMETER
VIN = 5V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over-temperature from -40°C to +105°C; Parameters
with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested. (Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
34
V
POSITIVE (VON) CHARGE PUMP
VON
VON Output Voltage Range
2X or 3X Charge Pump
ILOAD_PCP_MIN
External Load Driving Capability
VON = 25V (2X Charge Pump)
20
mA
VON = 34V (3X Charge Pump)
20
mA
VSUP + 2V
rON(VSUP_SW)
ON-Resistance of VSUP Input Switch I(SWITCH) = +40mA
10
17

rON(C1/2-)H
High-Side Driver ON-Resistance at
C1- and C2-
I(C1/2-) = +40mA
10
20

rON(C1/2-)L
Low-Side Driver ON-Resistance at
C1- and C2-
I(C1/2-) = -40mA
4
7

IPU(VSUP_SW)
Pull-Up Current Limit in VSUP Input
Switch
V(C2+) = 0V to V(SUP) - 0.4V - V(DIODE)
IPU(C1/2-)
Pull-Up Current Limit in C1- and C2- V(C1/2-) = 0V to V(VSUP) - 0.4V
IPD(C1/2-)
Pull-Down Current Limit in C1- and
C2-
V(C1/2-) = 0.2V to V(VSUP)
I(POUT)LEAK
Leakage Current in POUT
EN = LOW
VFBP
FBP Regulation Voltage
IDRVP = 0.2mA, TA = +25°C
1.176
IDRVP = 0.2mA
1.172
ACCP
VON Output Accuracy
D_PCP_max
Max Duty Cycle of the Positive
Charge Pump
V(DIODE)
Internal Schottky Diode Forward
Voltage
ION = 1mA, TA = +25°C
40
100
mA
40
100
mA
-100
-40
mA
5
µA
1.2
1.224
V
1.2
1.228
V
+2
%
-5
-2
50
I(DIODE) = +40mA
600
%
850
mV
ENABLE INPUTS
VHI-EN
Enable “HIGH”
2.2
V
VLO_EN
Enable “LOW”
IEN_pd
Enable Pin Pull-Down Current
VHI-ENL
Logic Enable “HIGH”
VLO-ENL
Logic Enable “LOW”
0.8
V
IENL_pd
Logic Enable Pin Pull-Down Current VENL > VLO_ENL
25
µA
100
200
µA
CTL = AGND, sequence complete
90
120
µA
VEN > VLO_EN
0.8
V
25
µA
2.2
V
VON SLICE Positive Supply = V(POUT)
I(POUT)_SLICE
VON slice Current from POUT Supply CTL = VDD, sequence complete
rON(POUT-COM)
ON-Resistance between POUT COM
CTL = VDD, sequence complete
5
10

rON(DRN-COM)
ON-Resistance between DRN COM
CTL = ACGND, sequence complete
30
60

rON_COM
ON-Resistance between COM and
PGND3
During start-up sequence
500
1500

VLO
CTL Input LOW Voltage
VIN = 4V to 5.5V
0.8
V
VHI
CTL Input HIGH Voltage
VIN = 4V to 5.5V
4
200
2.2
V
FN7493.3
April 24, 2009
ISL97651
Electrical Specifications
PARAMETER
VIN = 5V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over-temperature from -40°C to +105°C; Parameters
with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested. (Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
FAULT DETECTION THRESHOLDS
T_off
Thermal Shut-Down (latched and
reset by power cycle or EN cycle)
Temperature rising
150
°C
Vth_AVDD(FBB)
AVDD Boost Short Detection
V(FBB) falling less than
0.9
V
Vth_VLOGIC(FBL)
VLOGIC Buck Short Detection
V(FBL) falling less than
0.9
V
Vth_POUT(FBP)
POUT Charge Pump Short Detection V(FBP) falling less than
0.9
V
Vth_NOUT(FBN)
NOUT Charge Pump Short Detection V(FBN) rising more than
0.4
V
tFD
Fault Delay Time to Chip Turns Off
CDEL = 220nF
52
ms
80
ms
START-UP SEQUENCING
tSTART-UP
Enable to AVDD Start Time
CDEL = 220nF
IDELB_ON
DELB Pull-Down Current or
Resistance when Enabled by the
Start-Up Sequence
VDELB > 0.9V
36
50
70
µA
VDELB < 0.9V
1000
1326
1750

IDELB_OFF
DELB Pull-Down Current or
Resistance when Disabled
VDELB < 20V
500
nA
tVOFF
AVDD to VOFF
CDEL = 220nF
9
ms
tVON
VOFF to VON Delay
CDEL = 220nF
20
ms
tVON-SLICE
VON to VON-SLICE Delay
CDEL = 220nF
17
ms
Typical Performance Curves
0.10
100
VIN = 5V, AVDD = 15V
AVDD LOAD REGULATION (%)
0.05
EFFICIENCY (%)
80
VIN = 5V, AVDD = 15V
60
40
20
0
0
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
-0.35
0
200
400
600
800
IOUT (mA)
FIGURE 1. AVDD EFFICIENCY vs IOUT
5
1000
0
200
400
600
800
IOUT (mA)
1000
1200
FIGURE 2. AVDD LOAD REGULATION vs IOUT
FN7493.3
April 24, 2009
ISL97651
Typical Performance Curves (Continued)
L1 = 10µH, COUT = 40µF, CM1 = 4.7nF, RM1
CH1 = AVDD(200mV/DIV), CH2 = IAVDD(200mA/DIV)
100
VLOGIC EFFICIENCY (%)
90
80
VIN = 5V, VLOGIC = 3.3V
70
60
50
40
30
20
10
0
0
500
1000
1500
2000
OUTPUT CURRENT (mA)
1ms/DIV
FIGURE 3. AVDD TRANSIENT RESPONSE
FIGURE 4. VLOGIC EFFICIENCY vs OUTPUT CURRENT
L2 = 6.8µH, COUT = 30µF, CM2 = 4.7nF, RM2
0.1
CH1 = VLOGIC(50mV/DIV), CH2 = ILOGIC(200mA/DIV)
VLOGIC LOAD REGULATION (%)
VIN = 5V, VLOGIC = 3.3V
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
500
1000
1500
2000
2500
OUTPUT CURRENT (mA)
1ms/DIV
FIGURE 5. VLOGIC LOAD REGULATION vs OUTPUT CURRENT
FIGURE 6. VLOGIC TRANSIENT RESPONSE
0
VLOGIC LOAD REGULATION (%)
VON LOAD REGULATION (%)
0
-0.05
-0.10
-0.15
VON = 25V
-0.20
-0.25
-0.30
-0.35
0
10
20
30
ION (mA)
40
50
FIGURE 7. VON LOAD REGULATION vs ION
6
60
VIN = 5V, VLOGIC = 3.3V
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
-0.08
-0.09
-0.10
0
200 400 600 800 1000 1200 1400 1600 1800 2000
OUTPUT CURRENT(mA)
FIGURE 8. VLOGIC LOAD REGULATION vs OUTPUT
CURRENT
FN7493.3
April 24, 2009
ISL97651
Typical Performance Curves (Continued)
CH1 = COM(10V/DIV), CH2 = CTL(2V/DIV)
CH1 = CDLY, CH2 = VREF, CH3 = VLOGIC, CH4 = VON,
R1 = AVDD, R2 = AVDD_DELAY, R3 = VOFF
4ms/DIV
FIGURE 9. VON-SLICE CIRCUIT OPERATION
7
FIGURE 10. START-UP SEQUENCE
FN7493.3
April 24, 2009
ISL97651
Pin Descriptions
PIN NUMBER
PIN NAME
1
VIN1
Input voltage, connect to pin 33 (VIN2)
2
LX1
Internal boost switch connection
3
LX2
Internal boost switch connection
4
CB
Logic buck, boost strap pin
5
LXL
Buck converter output
6
VSUP
7
FBL
Logic buck feedback pin
8
CM2
Buck compensation network pin
9
CTL
Input control for VON slice output
10, 18, 28, 36
NC
No connect. Connect to die pad and GND for improved thermal efficiency.
11
DRN
Lower reference voltage for VON slice output
12
COM
VON slice output: when CTL = 1, COM is connected to SRC through a 5 resistor; when CTL = 0, COM
is connected to DRN through a 30 resistor.
13
POUT
Positive charge pump out
14
C1-
Charge pump capacitor 1, negative connection
15
C1+
Charge pump capacitor 1, positive connection
16
C2-
Charge pump capacitor 2, negative connection
17
C2+
Charge pump capacitor 2, positive connection
19
FBP
Positive charge pump feedback pin
20
VREF
21
FBN
22
PGND3
23
NOUT
24
VINL
25, 26
PGND2, 1
27
AGND
Signal ground pin
29
CDEL
Delay capacitor for start up sequencing, soft-start and fault detection timers.
30
ENL
31
DELB
Open drain NFET output to drive optional AVDD delay PFET
32
CM1
Boost compensation network pin
33
VIN2
Input voltage, connect to pin 1 (VIN1)
34
FBB
Boost feedback pin
35
EN
Enable for Boost, charge pumps and VON slice (independent of ENL).
(Exposed Die Plate)
N/A
Connect exposed die plate on rear of package to ACGND and the PGND1, 2 pins. See “Layout
Recommendation” on page 18 for PCB layout thermal considerations.
8
DESCRIPTION
Positive supply for charge pumps
Reference voltage
Negative charge pump feedback pin
Power ground for VOFF, VON and VON slice
Negative charge pump output
Logic buck supply voltage
Boost power grounds
Buck enable for VLOGIC output
FN7493.3
April 24, 2009
ISL97651
Block Diagram
VREF
SAWTOOTH
GENERATOR
CM1
FBB
+
VOLTAGE
FEEDBACK
SLOPE
COMPENSATION
VREF
REFERENCE
AND
BIAS
UVLO COMPARATOR
CONTROL
LOGIC

+
LX1
LX2
BUFFER
THRESHOLDS
AND BIAS
RSENSE
PGND1
PGND2
CURRENT
FEEDBACK
0.75VREF
1.2MHz
OSCILLATOR
PGND3
CURRENT LIMIT
COMPARATOR
VIN1, VIN2
ACGND
CURRENT LIMIT
THRESHOLD
SEQUENCE
AND
FAULT CONTROL
EN
CDEL
DELB
ENL
VINL
CB
NOUT
CONTROL
VSUP
LXL
NOUT
CONTROL
LOGIC
FBN
CURRENT
LIMIT
COMPARATOR
+
BUFFER
CURRENT FEEDBACK
+
0.2V
FBL
+

VREF
SLOPE
COMPENSATION
CURRENT LIMIT
THRESHOLD
UVLO COMPARATOR
CM2
VOLTAGE
FEEDBACK
SAWTOOTH
GENERATOR
+
0.4V
UVLO
COMPARATOR
0.75 VREF
+
FBP
+
POUT
CONTROL
0.75 VREF
VSUP
+
VREF
POUT
VSUP
C1-
C1+
POUT C2+
C2-
DRN
CTL
COM
FIGURE 11. BLOCK DIAGRAM
9
FN7493.3
April 24, 2009
ISL97651
Typical Application Diagram
6.8µF
R18
4.7
4.7nF
15V
R3
55k
C2
40µF
VIN1
C1
2.2µ
C3
AVDD_DELAY
AVDD
D1
L1
VIN
R4
300k
C4
OPEN
C5
1µF
VIN2
R1
LX1
CM1
10k
PGND1
LX2
R17*
FBB
R5
BOOST
PGND2
C18*
ENB
DELB
EN
CDEL
C6
0.22µF
500k
VREF
FBN
PGND3
5k
R20
BIAS
AND
SEQUENCE
CONTROL
C20
820p
C11
220nF
R6
40k
R7
VOFF CP
NOUT
328k
D2
C12
D3
C13
470nF
VSUP
C1+
POUT
C1VON CP
C2+
C8
220nF
-8V
VOFF
220nF
C7
220nF
C19
100p
C2-
C21
100p
R8
983k
FBP
R9
50k
C22 2.2nF
DRN
+25V
VON
C14
470nF
R12
R10
68k
R11
C15
0.1µF
VON SLICE
CTL
COM
1k
VON SLICE
R13
100k
VINL
TO GATE
DRIVER IC
CB
C10
10µF
C9
4.7nF
R2
C16
1µF
CM2
LXL
BUCK
2k
D4
ENL
FBL
AGND
L2
6.8µH
3.3V
VLOGIC
R14
2k
R15
C17
20µF
1.2k
*Open component positions.
10
FN7493.3
April 24, 2009
ISL97651
Applications Information
The ISL97651 provides a complete power solution for TFT
LCD applications. The system consists of one boost
converter to generate the AVDD voltage for column drivers,
one buck converter to provide voltage to logic circuit in the
LCD panel, one integrated VON charge pump and one VOFF
linear-regulator controller to provide the voltage to row
drivers. This part also integrates VON-slice circuit which can
help to optimize the picture quality. With the high output
current capability, this part is ideal for big screen LCD TV
and monitor panel application.
The integrated boost converter and buck converter operate
at 1.2MHz which can allow the use of multilayer ceramic
capacitors and low profile inductor which result in low cost,
compact and reliable system. The logic output voltage is
independently enabled to give flexibility to the system
designers.
This restricts the maximum output current (average) based
on Equation 3:
I L
V IN
I OMAX =  I LMT – --------  --------
2  VO
(EQ. 3)
Where IL is peak to peak inductor ripple current, and is set
by Equation 4:
V IN D
I L = ---------  ----L
fS
(EQ. 4)
where fS is the switching frequency (1.2MHz).
Table 1 gives typical values (margins are considered 10%,
3%, 20%, 10% and 15% on VIN, VO, L, fS and IOMAX:
TABLE 1. MAXIMUM OUTPUT CURRENT CALCULATION
VIN (V)
VO (V)
L (µH)
FS (MHz)
IOMAX (mA)
Boost Converter
4
9
6.8
1.2
1661
The boost converter is a current mode PWM converter
operating at a fixed frequency of 1.2MHz. It can operate in
both discontinuous conduction mode (DCM) at light load and
continuous mode (CCM). In continuous current mode,
current flows continuously in the inductor during the entire
switching cycle in steady state operation. The voltage
conversion ratio in continuous current mode is given by
Equation 1:
4
12
6.8
1.2
1173
4
15
6.8
1.2
879
5
9
6.8
1.2
2077
5
12
6.8
1.2
1466
5
15
6.8
1.2
1099
V BOOST
1
------------------------ = ------------1–D
V IN
(EQ. 1)
Where D is the duty cycle of the switching MOSFET
Figure 11 shows the functional block diagram of the boost
regulator. It uses a summing amplifier architecture consisting
of gm stages for voltage feedback, current feedback and
slope compensation. A comparator looks at the peak
inductor current cycle by cycle and terminates the PWM
cycle if the current limit is reached.
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 60k is recommended.
The boost converter output voltage is determined by
Equation 2:
 R3 + R5 
V BOOST = --------------------------  V REF
R5
(EQ. 2)
The current through the MOSFET is limited to a minimum of
4.4APEAK (maximum values can be up to 6.3APEAK.
11
Boost Converter Input Capacitor
An input capacitor is used to suppress the voltage ripple
injected into the boost converter. A ceramic capacitor with
capacitance larger than 10µF is recommended. The voltage
rating of input capacitor should be larger than the maximum
input voltage. Examples of recommended capacitors are
given in Table 2 below.
TABLE 2. BOOST CONVERTER INPUT CAPACITOR
RECOMMENDATION
CAPACITOR
SIZE
VENDOR
PART NUMBER
10µF/16V
1206
TDK
C3216X7R1C106M
10µF/10V
0805
Murata
GRM21BR61A106K
22µF/10V
1210
Murata
GRB32ER61A226K
Boost Inductor
The boost inductor is a critical component which influences
the output voltage ripple, transient response, and efficiency.
Values of 3.3µH to 10µH are to match the internal slope
compensation. The inductor must be able to handle without
saturating the following average and peak current:
IO
I LAVG = ------------1–D
I L
I LPK = I LAVG + -------2
(EQ. 5)
FN7493.3
April 24, 2009
ISL97651
Table 5 shows some selections of output capacitors.
Some inductors are recommended in Table 3.
TABLE 3. BOOST INDUCTOR RECOMMENDATION
INDUCTOR
DIMENSIONS
(mm)
VENDOR
CAPACITOR
PART NUMBER
6.8µH/
12.95x9.4x5.21 Coilcraft
4.6APEAK
DO3316P-682ML
10µH/
5.5APEAK
10x10x5
CDR10D48MNNP-100NC
5.2µH/
4.55APEAK
10x10.1x3.8
Sumida
TABLE 5. BOOST OUTPUT CAPACITOR RECOMMENDATION
SIZE
VENDOR
PART NUMBER
10µF/25V
1210 TDK
C3225X7R1E106M
10µF/25V
1210 Murata
GRM32DR61E106K
PI Loop Compensation (Boost Converter)
Cooper
CD1-5R2
Bussmann
Rectifier Diode (Boost Converter)
A high-speed diode is necessary due to the high switching
frequency. Schottky diodes are recommended because of
their fast recovery time and low forward voltage. The reverse
voltage rating of this diode should be higher than the
maximum output voltage. The rectifier diode must meet the
output current and peak inductor current requirements.
Table 4 shows some recommendations for boost converter
diode.
TABLE 4. BOOST CONVERTER RECTIFIER DIODE
RECOMMENDATION
VR/IAVG
RATING
PACKAGE
SS23
30V/2A
SMB
Fairchild
Semiconductor
MBRS340
40V/3A
SMC
International
Rectifier
SL23
30V/2A
SMB
Vishay
Semiconductor
VENDOR
Output Capacitor
The output capacitor supplies the load directly and reduces
the ripple voltage at the output. Output ripple voltage
consists of two components: the voltage drop due to the
inductor ripple current flowing through the ESR of output
capacitor, and the charging and discharging of the output
capacitor.
s
An RC network across feedback resistor R5 may be required
to optimize boost stability when AVDD voltage is set to less
than 12V. This network reduces the internal voltage
feedback used by the IC. This RC network sets a pole in the
control loop. This pole is set to approximately fp = 10kHz for
COUT = 10µF and fp = 4kHz for COUT = 30µF. Alternatively,
adding a small capacitor (20pF to 100pF) in parallel with R5
(i.e. R17 = short) may help to reduce AVDD noise and
improve regulation, particularly if high value feedback
resistors are used.
1
1 –1
R17 =   ------------------------- – ----------
  0.1  R5  R3 
1
C18 = ------------------------------------------------------ 2  3.142  fp  R5 
(EQ. 7)
(EQ. 8)
Cascaded MOSFET Application
IO
V O – V IN
1
V RIPPLE = I LPK  ESR + ------------------------  ----------------  ---f
C
V
OUT
The stability can be examined by repeatedly changing the
load between 100mA and a max level that is likely to be
used in the system being used. The AVDD voltage should be
examined with an oscilloscope set to AC 100mV/div and the
amount of ringing observed when the load current changes.
Reduce excessive ringing by reducing the value of the
resistor in series with the CM1 pin capacitor.
Boost Converter Feedback Resistors and
Capacitor
DIODE
O
The boost converter of ISL97651 can be compensated by a
RC network connected from CM1 pin to ground. C3 = 4.7nF
and R1 = 10k RC network is used in the demo board. A
higher resistor value can be used to lower the transient
overshoot - however, this may be at the expense of stability
to the loop.
(EQ. 6)
For low ESR ceramic capacitors, the output ripple is
dominated by the charging and discharging of the output
capacitor. The voltage rating of the output capacitor should
be greater than the maximum output voltage.
An 20V N-channel MOSFET is integrated in the boost
regulator. For the applications where the output voltage is
greater than 20V, an external cascaded MOSFET is needed,
as shown in Figure 12. The voltage rating of the external
MOSFET should be greater than AVDD.
Note: Capacitors have a voltage coefficient that makes their
effective capacitance drop as the voltage across then
increases. COUT in Equation 6 assumes the effective value
of the capacitor at a particular voltage and not the
manufacturer’s stated value, measured at 0V.
12
FN7493.3
April 24, 2009
ISL97651
VIN
AVDD
potential for noise being coupled into the feedback pin. A
resistor network in the order of 1k is recommended.
Buck Converter Input Capacitor
The capacitor should support the maximum AC RMS current
which happens when D = 0.5 and maximum output current.
LX1, LX2
FBB
INTERSIL
ISL97651
I ACRMS  C IN  =
D   1 – D   IO
(EQ. 13)
Where IO is the output current of the buck converter. Table 6
shows some recommendations for input capacitor.
TABLE 6. INPUT CAPACITOR (BUCK) RECOMMENDATION
FIGURE 12. CASCADED MOSFET TOPOLOGY FOR HIGH
OUTPUT VOLTAGE APPLICATIONS
Buck Converter
The buck converter is the step down converter, which
supplies the current to the logic circuit of the LCD system.
The ISL97651 integrates an 20V N-Channel MOSFET to
save cost and reduce external component count. In the
continuous current mode, the relationship between input
voltage and output voltage is shown in Equation 9:
V LOGIC
---------------------- = D
V IN
(EQ. 9)
Where D is the duty cycle of the switching MOSFET.
Because D is always less than 1, the output voltage of buck
converter is lower than input voltage.
The peak current limit of buck converter is set to 2A, which
restricts the maximum output current (average) based on the
Equation 10:
I OMAX = 2A – I pp
(EQ. 10)
Where IPP is the ripple current in the buck inductor as the
Equation 11:
V LOGIC
I pp = ----------------------   1 – D 
L  fs
(EQ. 11)
Where L is the buck inductor, fs is the switching frequency
(1.2MHz).
CAPACITOR
SIZE
VENDOR
PART NUMBER
10µF/16V
1206 TDK
C3216X7R1C106M
10µF/10V
0805 Murata
GRM21BR61A106K
22µF/16V
1210
Murata
C3225X7R1C226M
Buck Inductor
An inductor value in the range 3.3µH to 10µH is
recommended for the buck converter. Besides the
inductance, the DC resistance and the saturation current
should also be considered when choosing buck inductor.
Low DC resistance can help maintain high efficiency, and the
saturation current rating should be at least 2A. Table 7
shows some recommendations for buck inductor.
TABLE 7. BUCK INDUCTOR RECOMMENDATION
INDUCTOR
DIMENSIONS
(mm)
VENDOR
PART NUMBER
4.7µH/2.7APEAK
5.7x5.0x4.7
Murata
LQH55DN4R7M01K
6.8µH/3APEAK
7.3x6.8x3.2
TDK
RLF7030T-6R8M2R8
10µH/2.4APEAK 12.95x9.4x3.0 Coilcraft
DO3308P-103
Rectifier Diode (Buck Converter)
A Schottky diode is recommended due to fast recovery and
low forward voltage. The reverse voltage rating should be
higher than the maximum input voltage. The peak current
rating is 2A, and the average current should be as the
Equation 14:
I AVG =  1 – D *I o
Feedback Resistors
(EQ. 14)
The buck converter output voltage is determined by the
Equation 12:
Where IO is the output current of buck converter. Table 8
shows some diode recommended.
TABLE 8. BUCK RECTIFIER DIODE RECOMMENDATION
R 14 + R 15
V LOGIC = ---------------------------  V REF
R 15
(EQ. 12)
Where R14 and R15 are the feedback resistors of buck
converter to set the output voltage current drawn by the
resistor network should be limited to maintain the overall
converter efficiency. The maximum value of the resistor
network is limited by the feedback input bias current and the
13
DIODE
VR/IAVG
RATING
PACKAGE
PMEG2020EJ
20V/2A
SOD323F
Philips Semiconductors
SS22
20V/2A
SMB
Fairchild Semiconductor
VENDOR
FN7493.3
April 24, 2009
ISL97651
Output Capacitor (Buck Converter)
Four 10µF or two 22µF ceramic capacitors are
recommended for this part. The overshoot and undershoot
will be reduced with more capacitance, but the recovery time
will be longer.
TABLE 9. BUCK OUTPUT CAPACITOR RECOMMENDATION
CAPACITOR
SIZE
VENDOR
PART NUMBER
10µF/6.3V
0805 TDK
C2012X5R0J106M
10µF/6.3V
0805 Murata
GRM21BR60J106K
22µF/6.3V
1210 TDK
C3216X5R0J226M
100µF/6.3V
1206 Murata
GRM31CR60J107M
PI Loop Compensation (Buck Converter)
The buck converter of ISL97651 can be compensated by a
RC network connected from CM2 pin to ground. C9 = 4.7nF
and R2 = 2k RC network is used in the demo board. The
larger value resistor can lower the transient overshoot,
however, at the expense of stability of the loop.
The stability can be optimized in a similar manner to that
described in “PI Loop Compensation (Boost Converter)” on
page 12.
Bootstrap Capacitor (C16)
This capacitor is used to provide the supply to the high driver
circuitry for the buck MOSFET. The bootstrap supply is
formed by an internal diode and capacitor combination. A
1µF is recommended for ISL97651. A low value capacitor
can lead to overcharging and in turn damage the part.
If the load is too light, the on-time of the low side diode may
be insufficient to replenish the bootstrap capacitor voltage. In
this case, if VIN - VBUCK < 1.5V, the internal MOSFET pullup device may be unable to turn-on until VLOGIC falls.
Hence, there is a minimum load requirement in this case.
The minimum load can be adjusted by the feedback
resistors to FBL.
The pumps use pulse width modulation to adjust the pump
period, depending on the load present. The pumps can
provide 30mA for VOFF and 20mA for VON.
The positive charge pump can generate double or triple
VSUP voltage depending on the configuration of C2+ and
C2- pins. If the C2+ pin connects to C1+, it is the voltage
doubler, and if C2+ connects C2- via a capacitor, it
configured a voltage tripler.
Positive Charge Pump Design Consideration
The positive charge pump integrates all the diodes (D1, D2
and D3 shown in the block diagram in Figure 13) required for
x2 (VSUP doubler) and x3 (VSUP tripler) modes of operation.
During the chip start-up sequence the mode of operation is
automatically detected when the charge pump is enabled.
With both C7 and C8 present, the x3 mode of operation is
detected. With C7 present, C8 open and with C1+ shorted to
C2+, the x2 mode of operation will be detected.
Due to the internal switches to VSUP (M1, M2 and M3),
POUT is independent of the voltage on VSUP until the charge
pump is enabled. This is important for TFT applications
where the negative charge pump output voltage (VOFF) and
AVDD supplies need to be established before POUT.
The maximum POUT charge pump current can be estimated
from Equation 15 assuming a 50% switching duty:
I MAX  2x   min of 50mA or
2  V SUP – 2  V DIODE  2  I MAX  – V  V ON 
----------------------------------------------------------------------------------------------------------------------  0.95A
 2   2  R ONH + R ONL  
(EQ. 15)
I MAX  3x   min of 50mA or
3  V SUP – 3  V DIODE  2  I MAX  – V  V ON 
----------------------------------------------------------------------------------------------------------------------  0.95V
 2   3  R ONH + 2  R ONL  
Note: VDIODE (2 • IMAX) is the on-chip diode voltage as a
function of IMAX and VDIODE (40mA) < 0.7V.
The bootstrap capacitor can only be charged when the
higher side MOSFET is off. If the load is too light which can
not make the on time of the low side diode be sufficient to
replenish the boot strap capacitor, the MOSFET can’t turn
on. Hence there is minimum load requirement to charge the
bootstrap capacitor properly.
In voltage doubler configuration, the maximum VON is as
given by Equation 16:
Linear-Regulator Controllers (VON and VOFF)
V ON_MAX(3x) = 3   V SUP – V DIODE  – 2  I OUT   3  r ONH + 2  r ONL 
The ISL97651 include 2 independent charge pumps (see
Figure 13). The negative charge pump inverters the VSUP
voltage and provides a regulated negative output voltage.
The positive charge pump doubles or triples the VSUP
voltage and provides a regulated positive output voltage.
The regulation of both the negative and positive charge
pumps is generated by internal comparator that senses the
output voltage and compares it with the internal reference.
14
V ON_MAX(2x) = 2   V SUP – V DIODE  – 2  I OUT   2  r ONH + r ONL 
(EQ. 16)
For Voltage Tripler:
(EQ. 17)
VON output voltage is determined by Equation 18:
R 8

V ON = V FBP   1 + -------
R

9
(EQ. 18)
FN7493.3
April 24, 2009
ISL97651
External Connections
and Components
x2 Mode
x3 Mode
Both
VSUP
M2
C1C7
M4
C1+
VSUP
M1
Control
D3
D2
D1
1.2MHz
POUT
C14
0.9V
VSUP
C2+
Error
M3
VREF
C8
C2-
FB
C21
R8
M5
FBP
C22
R9
FIGURE 13. VON FUNCTION DIAGRAM
Negative Charge Pump Design Consideration
The negative charge pump consists of an internal switcher
M1, M2 which drives external steering diodes D2 and D3 via
a pump capacitor (C12) to generate the negative VOFF
supply. An internal comparator (A1) senses the feedback
voltage on FBN and turns on M1 for a period up to half a
CLK period to maintain V(FBN) in regulated operation at
0.2V. External feedback resistor R6 is referenced to VREF.
Faults on VOFF which cause VFBN to rise to more than 0.4V,
are detected by comparator (A2) and cause the fault
detection system to start a fault ramp on CDLY pin which will
cause the chip to power down if present for more than the
time TFD (see "Electrical Specification" on page 2 and also
Figure 15).
R6 and R7 in the “Typical Application Diagram” on page 10
determine VOFF output voltage.
R7
R7
V OFF = V FBN   1 + -------- – V REF   --------
 R6

R6
(EQ. 20)
Improving Charge Pump Noise Immunity
Depending on PCB layout and environment, noise pick-up at
the FBP and FBN inputs, which may degrade load regulation
performance, can be reduced by the inclusion of capacitors
across the feedback resistors (e.g. in the “Typical Application
Diagram” on page 10, C21 and C22 for the positive charge
pump). Set R6 • C20 = R7 • C19 with C19 ~ 100pF.
The maximum VOFF output voltage of a single stage charge
pump is:
V OFF_MAX  2x  = – V SUP+ V DIODE+ 2 I OUT  r ON NOUT H +r ON  NOUT L
(EQ. 19)
15
FN7493.3
April 24, 2009
ISL97651
VREF
A2
C19
100pF
VSUP
VDD
FAULT
0.4V
FBN
C20
820pF
R6
40k
A1
R7
328k
0.2V
1.2MHz
STOP
M2
CLK
NOUT
C12
220nF
D2
VOFF (-8V)
D3
PWM
CONTROL
EN
C13
470nF
M1
PGND
FIGURE 14. NEGATIVE CHARGE PUMP BLOCK DIAGRAM
VON Slice Circuit
Start-Up Sequence
The VON Slice Circuit functions as a three way multiplexer,
switching the voltage on COM between ground, DRN and SRC,
under control of the start-up sequence and the CTL pin.
Figure 15 shows a detailed start up sequence waveform. For
a successful power up, there should be 6 peaks at VCDLY.
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
During the start-up sequence, COM is held at ground via an
NDMOS FET, with ~1k impedance. Once the start-up
sequence has completed, CTL is enabled and acts as a
multiplexer control such that if CTL is low, COM connects to
DRN through a 30internal MOSFET, and if CTL is high,
COM connects to POUT internally via a 5MOSFET.
The slew rate of start-up of the switch control circuit is mainly
restricted by the load capacitance at COM pin as
Equation 21:
Vg
V
-------- = ----------------------------------- R i  R L   C L
t
(EQ. 21)
RWhere Vg is the supply voltage applied to DRN or voltage
at POUT, which range is from 0V to 36V. Ri is the resistance
between COM and DRN or POUT including the internal
MOSFET rDS(On), the trace resistance and the resistor
inserted, RL is the load resistance of switch control circuit,
and CL is the load capacitance of switch control circuit.
In the “Typical Application Diagram” on page 10, R10, R11
and C15 give the bias to DRN based on Equation 22:
V ON  R 11 +AVDD  R 10
V DRN = --------------------------------------------------------------R 10 + R 11
And R12 can be adjusted to adjust the slew rate.
16
(EQ. 22)
When the input is higher than 2.75V; if either EN or ENL is H,
VREF turns on. If ENL is H, VLOGIC turns on. If EN is H, an
internal current source starts to charge CCDLY to an upper
threshold using a fast ramp followed by a slow ramp. Several
more ramps follow, during which time the device checks for
fault conditions. If a fault is found, the sequence is halted.
Initially the boost is not enabled so AVDD rises to
VIN - VDIODE through the output diode. Hence, there is a step
at AVDD during this part of the start up sequence. If this step is
not desirable, an external PMOS FET can be used to delay
the output until the boost is enabled internally. The delayed
output appears at AVDD.
AVDD soft-starts at the beginning of the third ramp. The softstart ramp depends on the value of the CDLY capacitor. The
range of CDLY capacitor value is from 10nF to 220nF. For
CDLY of 220nF, the soft-start time is ~8ms.
VOFF turns on at the start of the fourth peak, at the same time
DELB gate goes low to turn on the external PMOS to
generate a delayed AVDD output.
VON is enabled at the beginning of the sixth ramp.
Once the start-up sequence is complete, the voltage on the
CDLY capacitor remains at 1.15V until either a fault is detected
or the EN pin is disabled. If a fault is detected, the voltage on
CDLY rises to 2.4V at which point the chip is disabled until the
power is cycled or enable is toggled.
FN7493.3
April 24, 2009
ISL97651
AVDD_delay Generation Using DELB
across the source and gate, hence M0 will be off. Please
note that the maximum leakage of DELB in this period is
500nA. To avoid any mis-trigger, the maximum value of R4
should be less than:
DELB pin is an open drain internal N-FET output used to
drive an external optional P-FET to provide a delayed AVDD
supply which also has no initial pedistal voltage (see
Figure 15 and compare the AVDD and AVDD_delayed
curves). When the part is enabled, the N-FET is held off until
CDLY reaches the 4th peak in the start-up sequence. During
this period, the voltage potential of the source and gate of
the external P-FET (M0 in application diagram) should be
almost the same due to the presence of the resistor (R4)
V GS  th _min(M0)
R 4_max  -------------------------------------------500nA
CHIP DISABLED
VOFF, DELB ON
VON SOFT-START
FAULT DETECTED
Where VGS(th)_min(M0) is the minimum value of gate
threshold voltage of M0.
AVDD SOFT-START
VREF, VLOGIC ON
(EQ. 23)
VCDLY
VIN
EN
VREF
VBOOST
(AVDD)
tSTART-UP
tSS
VLOGIC
VOFF
tVOFF
DELAYED
VBOOST
(AVDD_delay)
tVON
VON
VON SLICE
tVON-SLICE
START-UP SEQUENCE
TIMED BY CDLY
NOTE: Not to scale
NORMAL
OPERATION
FAULT
PRESENT
FIGURE 15. START-UP SEQUENCE
17
FN7493.3
April 24, 2009
ISL97651
After CDLY reaches the 4th peak, the internal N-FET is
turned-on and produces an initial current output of
IDELB_ON1 (~50µA). This current allows the user to control
the turn-on inrush current into the AVDD_delay supply
capacitors by a suitable choice of C4. This capacitor can
provide extra delay and also filter out any noise coupled into
the gate of M0, avoiding spurious turn-on, however, C4 must
not be so large that it prevents DELB reaching 0.6V by the
end of the start-up sequence on CDLY, else a fault time-out
ramp on CDLY will start. A value of 22nF is typically required
for C4. The 0.6V threshold is used by the chip's fault
detection system and if V(DELB) is still above 0.6V at the
end of the power sequencing then a fault time-out ramp will
be initiated on CDLY.
When the voltage at DELB falls below ~0.6V it's current is
increased to IDELB_ON2 (~1.4mA) to firmly pull the DELB
voltage to ground.
If the maximum VGS voltage of M0 is less than the AVDD
voltage being used, then a resistor may be inserted between
the DELB pin and the gate of M0 such that it's potential
divider action with R4 ensures the gate/source stays below
VGS(M0)max. This additional resistor allows much larger
values of C4 to be used, and hence longer AVDD delay,
without affecting the fault protection on DELB.
Component Selection for Start-up Sequencing and
Fault Protection
The CREF capacitor is typically set at 220nF and is required
to stabilize the VREF output. The range of CREF is from
22nF to 1µF and should not be more than five times the
capacitor on CDEL to ensure correct start-up operation.
The CDEL capacitor is typically 220nF and has a usable
range from 47nF minimum to several microfarads – only
limited by the leakage in the capacitor reaching µA levels.
CDEL should be at least 1/5 of the value of CREF (see
above). Note with 220nF on CDEL the fault time-out will be
typically 50ms and the use of a larger/smaller value will vary
this time proportionally (e.g., 1µF will give a fault time-out
period of typically 230ms).
Over-Temperature Protection
An internal temperature sensor continuously monitors the
die temperature. In the event that the die temperature
exceeds the thermal trip point of +150°C, the device will shut
down. Operation with die temperatures between +125°C and
+150°C can be tolerated for short periods of time, however,
in order to maximize the operating life of the IC, it is
recommended that the effective continuous operating
junction temperature of the die should not exceed +125°C.
Layout Recommendation
The device’s performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
There are some general guidelines for layout:
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
2. Place VREF and VDC bypass capacitors close to the pins.
3. Reduce the loop with large AC amplitudes and fast slew
rate.
4. The feedback network should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point.
6. The exposed die plate, on the underneath of the
package, should be soldered to an equivalent area of
metal on the PCB. This contact area should have multiple
via connections to the back of the PCB as well as
connections to intermediate PCB layers, if available, to
maximize thermal dissipation away from the IC.”
7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track
and ground plane area connected to the exposed die
plate should be maximized and spread out as far as
possible from the IC. The bottom and top PCB areas
especially should be maximized to allow thermal
dissipation to the surrounding air.
8. Minimize feedback input track lengths to avoid switching
noise pick-up.
A demo board is available to illustrate the proper layout
implementation.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
18
FN7493.3
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ISL97651
Package Outline Drawing
L36.6x6
36 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 08/08
6.00
6
PIN #1 INDEX AREA
32x 0.50
A
B
36
28
6
27
6.00
PIN 1
INDEX AREA
1
4.15 +0.10/-0.15
4X 4.00
9
19
(4X)
0.15
10
18
36X 0.55 ± 0.10
36X 0.25 +0.05/-.07 4
0.10 M C A B
BOTTOM VIEW
TOP VIEW
( 5.65 )
( 4.15)
Exp. Dap.
SEE DETAIL "X"
( 5.65 )
0.10 C
Max 0.80
C
( 32x 0.50)
0.08 C
( 4.15)
Exp. Dap.
SIDE VIEW
(36X .25)
C
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
( 4X 4.00)
(36X 0.75)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
1. Dimensions are in millimeters.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
19
FN7493.3
April 24, 2009
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