DATASHEET

OD U C T
ETE PR EMENT PART
L
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S
B
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NDED R 602
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REC
ISL98
Data Sheet
December 13, 2006
4-Channel TFT-LCD Supply
Features
The ISL97522 represents a 4-channel supply control IC for
use in large panel TFT-LCD displays. Supporting inputs from
4.5V to 13V, the ISL97522 includes a boost controller to
achieve the required AVDD output voltage. Both VON and
VOFF are generated using off-chip charge-pumps which are
then post regulated using on-board LDO controllers.
• 4.5V to 13V input
The logic supply is generated using an internal nonsynchronous buck controller. This controller runs at 180° out
of phase with the AVDD supply to minimize input noise.
The AVDD, VOFF, and VON outputs are automatically
sequenced as AVDD, VOFF, and VON. By using an optional
external series transistor with AVDD (Q1), the start-up
sequence can be adjusted to VOFF, AVDD and then VON. A
VON slicing circuit is also included to reduce LCD flicker.
The ISL97522 also incorporates a fault protection circuit that
can disable the IC and turn off all outputs when an output
short is detected. (Note that to protect AVDD a single
external transistor is required).
Ordering Information
• Buck controller for logic output
• VON slicing circuit
• Fully fault-protected
• Programmable sequence
• 1MHz switching frequency
• 38 Ld QFN package
• Pb-free plus anneal available (RoHS compliant)
Applications
• LCD-TVs (up to 50”+)
• LCD monitors (15”+)
• Industrial/medical LCD displays
Pinout
PKG.
DWG. #
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
32 VCC2
33 CDLY
34 CTL
13”
38 Ld QFN L38.5x7B
(4k pcs)
35 ENL
ISL97522IRZ-T
36 DRN
13”
38 Ld QFN L38.5x7B
(1k pcs)
ISL97522
(38 LD QFN)
TOP VIEW
37 COM
TAPE & PACKAGE
REEL (Pb-Free)
ISL97522IRZ-TK ISL 97522IRZ
DRVN 1
31 FBP
DELB 2
30 VREF
29 ACGND
FBN 3
28 NC
VCC1 4
27 DRVP
FBB 5
ISADJB 6
26 NC
THERMAL
PAD
ILADJB 7
25 VDCP
CINTB 8
24 VDC
DRVB 9
23 ISADJL
PGNDB 10
22 CINTL
VHIB 11
21 ILADJL
1
PGNDP 19
DRVL 18
LX 17
VHIL 16
20 PBL
ISINB 13
NC 12
EN 15
ISL 97522IRZ
• Regulated LDOs for VOFF and VON
VIN 14
PART
MARKING
FN7445.0
• Boost controller for AVDD
38 SRC
PART NUMBER
(Note)
ISL97522
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas LLC
Copyright Intersil Americas LLC 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL97522
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Maximum Pin Voltages, all pins except below. . . . . . . . 6.5V
VIN,EN,ENL,LX,VHIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25V
VDELB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
VDRVP, VSINB, SRC, COM, DRN . . . . . . . . . . . . . . . . . . . . . . .36V
VDRVN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20V
Thermal Resistance
JA (°C/W)
JC (°C/W)
33
4.5
38 Ld QFN Package (Notes 1, 2). . . . .
Operating Conditions
Input Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 13V
Boost Output Voltage Range, AVDD . . . . . . . . . . . . . . +15V to +25V
VON Output Range, VON . . . . . . . . . . . . . . . . . . . . . . . +15V to +32V
VOFF Output Range, VON . . . . . . . . . . . . . . . . . . . . . . . . -15V to -5V
Input Capacitance, CIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2x10µF
Boost Inductor, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH to 10µH
Output Capacitance, COUT . . . . . . . . . . . . . . . . . . . . . . . . . . 4x10µF
Buck Inductor, L2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH to 10µH
Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VIN = 5V, AVDD = 15V, VON = 20V, VOFF = -9V, VLOGIC = 3V, Over Temperature from -40°C to +85°C
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
13.2
V
GENERAL
VIN
Input Voltage
IS
Sum Quiescent Current into Vin
4.5
FOSC
Oscillator Frequency
VREF
Reference Voltage
EN = 0, ENL = 0
3
mA
EN = ENL = 1, switching
15
mA
TA = +25°C
850
1000
1100
kHz
1.192
1.215
1.235
V
1.190
1.215
1.237
V
1.195
1.208
1.221
V
1.193
1.208
1.223
V
0.85
0.9
0.95
V
19
25
%
AVDD
VFBB
Feedback Reference Voltage
VF_FBB
FBB Fault Trip Point
DMIN
Minimum Duty Cycle
DMAX
Maximum Duty Cycle
Eff
TA = +25°C
VFBB falling
86
%
Boost Efficiency
90
%
IFBB
FBB Input Bias Current
25
nA
RLINEB
Line Regulation
CINT = 2.2nF, VIN = 4.5V to12V, IO =100mA
0.01
0.25
%/V
RLOADB
Load Regulation
CINT = 2.2nF, VIN = 5V, IAVDD = 100mA to
350mA
0.03
0.25
%
RONB
Gate Drive on Resistance
Pull-up
3.6

Pull-down
1.9

2
80
FN7445.0
December 13, 2006
ISL97522
Electrical Specifications
PARAMETER
IPEAKB
VIN = 5V, AVDD = 15V, VON = 20V, VOFF = -9V, VLOGIC = 3V, Over Temperature from -40°C to +85°C
DESCRIPTION
Peak Drive Current
CONDITION
MIN
TYP
MAX
UNIT
Source
600
mA
Sink
900
mA
IISADJB
ISADJB Output Current
RSADJB = 30k
10
15
25
µA
IILADJB
ILADJB Output Current
RLADJB = 30k
10
17
25
µA
FBP Regulation Voltage
IDRVP = 0.2mA,TA = +25°C
1.176
1.2
1.224
V
IDRVP = 0.2mA
1.174
1.2
1.226
V
0.82
0.87
0.92
V
VON LDO
VFBP
VF_FBP
FBP Fault Trip Point
VFBP falling
IFBP
FBP Input Bias Current
VFBP = 1.35V
150
RLOADP
VON Load Regulation
I(VON) = 0mA to 20mA
0.5
IDRVP
DRVP Sink Current Max
VFBP = 1.1V, VDRVP = 25V
IL_DRVP
DRVP Leakage Current
VFBP = 1.5V, VDRVP = 35V
FBN Regulation Voltage
IDRVN = 0.2mA,TA = +25°C
2
nA
0.75
4
%
mA
0.3
2
µA
0.186
0.213
0.24
V
IDRVN = 0.2mA
0.183
0.213
0.243
V
0.45
0.5
0.55
V
VOFF LDO
VFBN
VF_FBN
FBN Fault Trip Point
VFBN rising
IFBN
FBNInput Bias Current
VFBN = 0.2V
40
RLOADN
VOFF Load Regulation
I(VOFF) = 0mA to 20mA
0.4
IDRVN
DRVN Source Current Max
VFBN = 0.3V, VDRVN = -6V
IL_DRVN
DRVN Leakage Current
VFBN = 0V, VDRVN = -20V
FBL Regulation Voltage
TA = 25°C
2
nA
0.85
4
%
mA
0.4
5
µA
1.178
1.2
1.222
V
1.176
1.2
1.224
V
VLOGIC
VFBL
DMIN
Minimum Duty Cycle
20
%
DMAX
Maximum Duty Cycle
85
%
EFFL
Logic Buck Efficiency
90
%
IFBL
FBL Input Bias Current
20
nA
ILINEL
VLOGIC Line Regulation
CINT = 2.2nF, VIN = 5V to 12V
0.03
0.25
%/V
ILOADL
VLOGIC Load Regulation
CINT = 2.2nF, ILOGIC = 100mA to 450mA
0.1
0.5
%
RONL
Gate Drive on Resistance
Pull-up
3.6

Pull-down
1.9

Source
600
mA
Sink
900
mA
IPEAKL
Peak Drive Current
IISADJL
ISADJB Output Current
RSADJB = 30k
15
µA
IILADJL
ILADJB Output Current
RLADJB = 30k
17
µA
VON -SLICE CIRCUIT
ILEAKCTL
CTL Input Leakage Current
CTL = AGND or VIN
tDrise
CTL to OUT Rising Prop Delay
1k from DRN to 8V, VCTL = 0V to 3V step,
no load on OUT, measured from VCTL = 1.5V
to OUT = 20%
3
-1
1
100
µA
ns
FN7445.0
December 13, 2006
ISL97522
Electrical Specifications
PARAMETER
VIN = 5V, AVDD = 15V, VON = 20V, VOFF = -9V, VLOGIC = 3V, Over Temperature from -40°C to +85°C
DESCRIPTION
tDfall
CTL to OUT Falling Prop Delay
VSRC
SRC Input Voltage Range
ISRC
SRC Input Current
CONDITION
MIN
TYP
MAX
100
1k from DRN to 8V, VCTL = 3V to 0V step,
no load on OUT, measured from VCTL = 1.5V
to OUT = 80%
UNIT
ns
30
V
Start-up sequence not completed
0.2
1.25
mA
Start-up sequence completed
150
250
µA
RONSRC
SRC On Resistance
Start-up sequence completed
5
14

RONDRN
DRN On Resistance
Start-up sequence completed
30
60

RONCOM
COM to GND On Resistance
Start-up sequence not completed
1000
1800

tON
Turn On Delay
CDLY = 0.22µF
30
ms
tSS
Soft-start Time
CDLY = 0.22µF
2
ms
tDEL1
Delay Between AVDD and VOFF
CDLY = 0.22µF
10
ms
tDEL2
Delay Between VON and VOFF
CDLY = 0.22µF
17
ms
tDEL3
Delay Between VOFF and Delayed
VBOOST
CDLY = 0.22µF
10
ms
IDELB_ON
DELB Pull-Down Current or Resistance VDELB > 0.9V
when Enabled by the Start-Up
VDELB < 0.9V
Sequence
400
SEQUENCING
IDELB_OFF
35
50
65
µA
1.2
1.6
2
K
500
nA
DELB Pull-Down Current or Resistance VDELB < 20V
when Disabled
FAULT DETECTION
TFAULT
Fault Time Out
OT
Over-temperature Threshold
CDLY = 0.22µF
50
ms
140
°C
LOGIC
VHI
Logic High Threshold
VLO
Logic Low Threshold
ILOW
Logic Low Bias Current
IHIGH
Logic High Bias Current
4
2.2
V
0.8
0.1
16
23
V
µA
30
µA
FN7445.0
December 13, 2006
ISL97522
Typical Performance Curves
100
0
90
-0.2
70
LOAD REGULATION (%)
EFFICIENCY (%)
80
VIN = 5V, AVDD = 12V
60
50
40
VIN = 12V, AVDD = 17V
30
20
VIN = 5V, AVDD = 12V
-0.6
-0.8
-1
-1.2
-1.4
-1.6
10
0
VIN = 12V, AVDD = 17V
-0.4
0
500
1000
1500
2000
-1.8
2500
0
500
2000
2500
100
17.04
90
17.02
80
EFFICIENCY (%)
17
AVDD(V)
1500
FIGURE 2. BOOST AVDD LOAD REGULATION
FIGURE 1. BOOST AVDD EFFICIENCY
VO = 17V
16.98
16.96
16.94
16.92
70
VIN = 5V, VLOGIC = 3V
60
50
VIN = 12V, VLOGIC = 3V
40
30
20
16.9
10
0
16.88
0
2
4
6
8
10
12
14
0
16
500
1000
1500
2000
2500
ILOGIC (mA)
VIN (V)
FIGURE 4. BUCK VLOGIC EFFICIENCY
FIGURE 3. BOOST AVDD LINE REGULATION
0
19.75
19.74
-0.2
VON = 20V
19.73
VIN = 5V, VLOGIC = 3V
-0.4
19.72
VON (V)
LOAD REGULATION (%)
1000
IAVDD (mA)
IAVDD (mA)
-0.6
VIN = 12V, VLOGIC = 3V
-0.8
19.71
19.7
19.69
19.68
-1
19.67
-1.2
0
500
1000
1500
2000
2500
ILOGIC (mA)
FIGURE 5. BUCK VLOGIC LOAD REGULATION
5
19.66
0
5
10
15
20
25
IVON (mA)
FIGURE 6. VON LOAD REGULATION
FN7445.0
December 13, 2006
ISL97522
Typical Performance Curves
(Continued)
-8.875
VOFF (V)
-8.880
VOFF = -9V
-8.885
CH1 = COM (10V/DIV)
-8.890
-8.895
-8.900
-8.905
CH2 = CTL (2V/DIV)
0
5
10
15
IVOFF (mA)
20
FIGURE 7. VOFF LOAD REGULATION
25
FIGURE 8. 4ms/DIV VON SLICE CIRCUIT OPERATION
CDLY
CDLY
EN
AVDD
AVDD
VOFF
VLOGIC
VON
FIGURE 9. START-UP SEQUENCE
FIGURE 10. START-UP SEQUENCE
AVDD (BOOST)
VLOGIC (BOOST MODE)
IIN
IIN
FIGURE 11. IN RUSH CURRENT
6
FIGURE 12. IN RUSH CURRENT
FN7445.0
December 13, 2006
ISL97522
Typical Performance Curves
(Continued)
VLOGIC (BUCK MODE)
AVDD (BUCK)
IIN
IIN
FIGURE 13. IN RUSH CURRENT
7
FIGURE 14. IN RUSH CURRENT
FN7445.0
December 13, 2006
ISL97522
Pin Descriptions
PIN #
PIN NAME
PIN DESCRIPTION
1
DRVN
Negative LDO base drive; open drain of an internal P-Channel MOSFET.
2
DELB
Active low control output for optional delay control for external AVDD P-Channel FET; when fault is detected, this pin
goes to high.
3
FBW
Negative LDO voltage feedback input pin; regulates to 0.2V nominal.
4
VCC1
Supply input, connect to VIN.
5
FBB
6
ISADJB
Current feedback adjust for AVDD.
7
ILADJB
With a resistor connected from this pin to GND sets the current limit of the external N-channel FET for AVDD.
8
CINTB
AVDD integrator output, connect 2.2nF to analog GND.
9
DRVB
Gate driver output for the external N-Channel switch.
10
PGNDB
11
VHIB
12
NC
13
ISINB
14
VIN
Main supply input.
15
EN
Enable pin; high enable, low disabled.
16
VHIL
VLOGIC boost strap mode.
17
LX
VLOGIC switch connection.
18
DRVL
19
PGNDP
20
FBL
21
ILADJL
With resistor connected from this pin to GND sets the current limit of the external N-channel FET.
22
CINTL
VLOGIC integrator output, connect 2.2nF to analog GND.
23
ISADJL
Current feedback adjust for VLOGIC.
24
VDC
25
VDCP
26
NC
27
DRVP
28
NC
29
ACGND
30
VREF
31
FBP
Positive LDO voltage feedback input pin; regulates to 1.2V nominal.
32
CC2
Supply input, connect to VIN.
33
CDLY
With a capacitor connect from this pin to GND, sets the delay time for start-up sequence and fault detection timeout.
34
CTL
Input control for switch output.
35
ENL
Enable pin for VLOGIC high enable; low disabled.
36
DRN
Lower reference voltage for switch output.
37
COM
Switch output; when CTL = 1, COM is connected to SRC through a 15 resistor, when CT: = 0, COM is connected
to DRN through a 30 resistor.
38
SRC
Upper reference voltage for switch output.
AVDD regulator voltage feedback input pin; regulates to 1.2V nominal.
Power GND for AVDD.
Internal Drive of Boost controller, Connect to VDCP.
Sense the drain voltage of the external N-channel FET and connected to the internal current limit comparator.
Gate driver output for external N-channel switch.
Power GND.
VLOGIC regulator voltage feedback pin; regulates to 1.2V nominal.
Positive supply for all internal analog circuits.
Positive supply for external N-Channel FET gate drives.
Positive LDO base drive; open drain of an internal N-Channel MOSFET.
Low noise signal ground.
Bandgap voltage bypass terminal; bypass with a 0.1µF to analog GND; can be used as charge pump reference.
8
FN7445.0
December 13, 2006
ISL97522
Typical Application Diagram
VN
D11
D21
C25
0.1µF
C24
C11
0.1µF
0.1µF
D1
L1 6.8µH
VBOOST
VIN
C2
ION FX3
10µFX2
VIN
DRVB
R20 30k
ISADJB
R19 30k
ILADJB
BOOST
CONTROLLER
VDCP
C23
4.7µF
R2
140k
ISINB
C30
4.7NF R10 10k CINTB
C1
INTERNAL
SUPPLY
POWER ON
SEQUENCING
CDLY
C7
220nF
VOFF LDO
CONTROL
INPUT
VSW
FAULT
PROTECTION
VON SLICE
CLOCK/
TIMING
R12
237k
R23
1k
R11
12k
TO GATE DRIVER
R21
R22
68k
L2
6.8µF
C3
D2
10µFX4F
DRVL
PGNDB
VLOGIC
R12
210k
C32
100nF
FBL
BUCK
CONTROLLER
R13
118k
VHIL
C28
0.47µ
ACGND
R15 30k
25V
VON
C15
1µF
Q11
LX
PGNDP
C27
4.7nF
COM
DRN
ENL
R28
10k
VP
R4
3k
FBP
VIN Q2
VCCL
C20
4.7µF
R21 20k
SRC
DELB
-8V
VOFF
R22
104k
FBN
DRVP
CTL
R8
300k
VSW
Q21
R3
3k
C25
1µF
VCC2
VN
VREF
VON LDO
C9
0.01µF
12k
VDCP
EN
R29
10k
C16
0.01µF
R1
DRVN
C24
4.7µF
15V
AVDD
Q3
Q1
FBB
VHIB
VDC
R9
1M
VP
ISADJL
CINTL
R17 2k
ILADJL
R16 30k
9
FN7445.0
December 13, 2006
ISL97522
Applications Information
AVDD Converter
The ISL97522 provides a multiple output power supply
solution for TFT-LCD applications. The system consists of a
high efficiency boost controller, two low cost linear-regulator
controllers (VON and VOFF) and a buck reglator (VLOGIC).
The main boost converter is a current mode PWM controller
operating at a fixed frequency. The 1MHz switching
frequency enables the use of low profile inductor and
multilayer ceramic capacitors, which results in a compact,
low-cost power system for LCD panel design.
Table 1 below lists the recommended components.
TABLE 1. RECOMMENDED COMPONENTS
DESIGNATION
DESCRIPTION
C1, C2, C3
10µF, 16V, X7R ceramic capacitor (1206)
TDK C3216X7R1C106M
C20
4.7µF, 16V X5R ceramic capacitor (1206)
TDK C3216X5R1A475K
C15
1µF, 25V X7R ceramic capacitor (1206)
TDK C3216X7R1E105K
D1
1A 20V low leakage schottky rectifier (CASE
457-04) ON SEMI MBRM120ET3
D11, D12, D21
200mA 30V schottky barrier diode (SOT-23)
Fairchild BAT54S
L1
6.8mH 4.6A inductor
Coilcraft DO3316P-682ML
Q1,Q2
6.3A 30V single N-Channel logic level
PowerTrench MOSFET (SOT-23)
Fairchild FDC655AN
Q3
-2A -30V single P-Channel logic level
PowerTrench MOSFET (SuperSOT-3)
Fairchild FDN360P
Q11
200mA 40V PNP amplifier (SOT-23)
Fairchild MMBT3906
Q21
200mA 40V NPN amplifier (SOT-23)
Fairchild MMBT3904
The AVDD converter can operate in continuous or
discontinuous inductor current mode. The ISL97522 is
designed for continuous current mode, but it can also
operate in discontinuous current mode at light load. In
continuous current mode, current flows continuously in the
inductor during the entire switching cycle in steady state
operation. The voltage conversion ratio in continuous current
mode is given by (in boost mode):
A VDD
1
---------------- = ------------1–D
V IN
where D is the duty cycle of switching MOSFET.
Figure 15 shows the function diagram of the boost controller.
It uses a summing amplifier architecture consisting of GM
stages for voltage feedback, current feedback and slope
compensation. A comparator looks at the peak inductor
current cycle by cycle and terminates the PWM cycle if the
current limit is reached.
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 200k is
recommended. The boost converter output voltage is
determined by the following equation:
R1 + R2
A VDD = ---------------------  V FBB
R1
10
(EQ. 1)
(EQ. 2)
FN7445.0
December 13, 2006
ISL97522
VREF
VIN
REFERENCE
GENERATOR
OSCILLATOR
SLOPE
COMPENSATION
OSC

VBOOST
PWM
LOGIC
CONTROLLER
DRVB
BUFFER
ISADJ
FBB
CINTB
GM
AMPLIFIER
ISIN
CURRENT
AMPLIFIER
SHUTDOWN
& STARTUP
CONTROL
UVLO
COMPARATOR
CURRENT
LIMIT REF
GENERATOR
ILADJ
CURRENT LIMIT
COMPARATOR
FIGURE 15. FUNCTION DIAGRAM OF THE BOOST CONTROLLER
The internal current limit circuitry is shown in Figure 16. The
circuit senses the voltage across the RDS(ON) when the
MOSFET is on; then compare it to the internal voltage
reference to realize the current limit. The internal voltage
reference is generated by a 10mA current and any additional
current set at ILADJB pin flowing through an 8k resistor.
The voltage reference is based on the following equation:
 V ILADJB

V THRESHOLD =  ------------------------ + 10A  8K
 R1

VDD
LX
ISINB
10µA
-
(EQ. 3)
VREF
1k
Where VILADJB is the voltage at pin ILADJ.
Where VISAD is the voltage at pin ISAD.
+
R1
8k
LOGIC
CONTROLLER
DRVB
ILADJB
V ISAD = V REF – V BE – 1K  I SAD
V ISAD
I SAD = ----------------R1
(EQ. 4)
FIGURE 16. CURRENT LIMIT BLOCK DIAGRAM
Hence the maximum output current is determined by the
following equation:
Where VBE  0.7V
The external resistor R1 should be chosen in the order of
100K to generate µA of current.
V IN
 V THRESHOLD I L
I OMAX =  --------------------------------------- – --------   --------
R
2
VO

DSON
(EQ. 5)
Where IL is the peak to peak inductor ripple current, and is
set by:
V IN D
I L = ---------  ----L
fS
11
(EQ. 6)
FN7445.0
December 13, 2006
ISL97522
fS is the switching frequency; D is the duty cycle.
V O – V IN
D = -----------------------VO
Boost Inductor
(EQ. 7)
To overcome the variation in external LX driver RDS(ON) , an
input is provided (ILADJ) to accommodate 5 different bands
of RDS(ON) by using 5 different selection resistors. Internally,
the ILADJ resistor adjusts two things:
A 6.8µH inductor is recommended. The inductor must be
able to handle the following average and peak current:
IO
I LAVG = ------------1–D
(EQ. 8)
I L
I LPK = I LAVG + -------2
(EQ. 9)
BOOST MOSFET
1.the current limit;
2.the current feedback being used.
This keeps the dc-dc loop stable and the current limit the
same over a wide range of external drive FETs.
Alternatively, the current limit can be changed for the same
FET by varying the resistor. This would affect the stability of
the system somewhat (because the current feedback
changes) but be selected appropriately to accommodated
the change. The integrator loop should keep the load
regulation within limits as long as it doesn't run out of
dynamic adjustment range when current feedback gets
larger than intended. This could be determined by
measuring how close to the upper clamp limit the voltage on
the Cint pin voltage gets under maximum load current.
Due to the parasitic inductance of the trace, the MOSFET
will experience spikes higher that the output voltage when
the MOSFET turns off. Thus, a MOSFET with enough
voltage margin is needed.
The RDS(ON) of the MOSFET is critical for power dissipation
and current limit. A MOSFET with low RDS(ON) is desired to
get high efficiency and output current, but very low RDS(ON)
will reduce the loop stability. A MOSFET with 20m to 50m
RDS(ON) is recommended. Some recommended MOSFETs
are shown in Table 2.
TABLE 2. RECOMMENDED MOSFETs
PART
NUMBER
MANUFACTURER
FEATURE
FDC655AN
Fairchild
Semiconductor
6.3A, 30V, RDS(ON) = 23m
Here are the resistor settings on ILADJ which select the five
RDS(ON) ranges:
FDS4488
7.9A, 30V, RDS(ON) = 22m
1/ 0ohms (Cfb factor 1, "Cfb" are the relative current
feedback factors)
Fairchild
Semiconductor
Si7844DP
Vishay
10A, 30V, RDS(ON) = 22m
SI6928DQ
Vishay
20A, 30V, RDS(ON) = 30m
2/ 30K
(Cfb factor 1/1.8)
3/ 83K
(Cfb factor 1/3.3)
Rectifier Diode
4/ 182K (Cfb factor 1/5.7)
5/ >370K (Cfb factor 1/10)
1/ sets maximum internal current feedback and minimum
ILimit, used for low Ron fets.
5/ sets minimum internal current feedback and maximum
ILimit, used for large Ron fets.
The Current limit factors should be the inverse of the Cfb
values.
Input Capacitor
The input capacitor is used to supply the current to the
converter. It is recommended that CIN be larger than 10µF.
The reflected ripple voltage will be smaller with larger CIN.
The voltage rating of input capacitor should be larger than
maximum input voltage.
12
A high-speed diode is desired due to the high switching
frequency. Schottky diodes are recommended because of
their fast recovery time and low forward voltage. The rectifier
diode must meet the output current and peak inductor
current requirements.
Output Capacitor
The output capacitor supplies the load directly and reduces
the ripple voltage at the output. Output ripple voltage consists
of two components: the voltage drop due to the inductor ripple
current flowing through the ESR of output capacitor, and the
charging and discharging of the output capacitor.
IO
V O – V IN
1
V RIPPLE = I LPK  ESR + ------------------------  ----------------  ----VO
C OUT f S
(EQ. 10)
For low ESR ceramic capacitors, the output ripple is
dominated by the charging and discharging of the output
capacitor. The voltage rating of the output capacitor should
be greater than the maximum output voltage.
FN7445.0
December 13, 2006
ISL97522
PI mode CINT (C23) and RINT (R10)
The IC is designed to operate with a minimum C23 capacitor
of 4.7nF and a minimum C2 (effective) = 10µF.
Note that, for high voltage AVDD, the voltage coefficient of
ceramic capacitors (C2) reduces their effective capacitance
greatly; a 16V 10µF ceramic can drop to around 3µF at 15V.
To improve the transient load response of AVDD in PI mode,
a resistor may be added in series with the C23 capacitor. The
larger the resistor the lower the overshoot but at the expense
of stability of the converter loop - especially at high currents.
With L = 10µH, AVDD = 15V, C23 = 4.7nF, C2 (effective)
should have a capacitance of greater than 10µF. RINT (R7)
can have values up to 5k for C2 (effective) up to 20µF and
up to 10K for C2 (effective) up to 30µF.
Larger values of RINT (R7) may be possible if maximum
AVDD load currents less than the current limit are used. To
ensure AVDD stability, the IC should be operated at the
maximum desired current and then the transient load
response of AVDD should be used to determine the
maximum value of RINT
Operation of the DELB Output Function
An open drain DELB output is provided to allow the boost
output voltage, developed at C2 (see application diagram),
to be delayed via an external switch (Q3) to a time after the
VBOOST supply and negative VOFF charge pump supply
have achieved regulation during the start-up sequence
shown in Figure 21. This then allows the AVDD and VON
supplies to start-up from 0V instead of the normal offset
voltage of VIN-VDIODE (D1) if Q3 were not present.
When DELB is activated by the start-up sequencer, it sinks
50µA allowing a controlled turn-on of Q3 and charge-up of
C9. C16 can be used to control the turn-on time of Q3 to
reduce inrush current into C9. The potential divider formed
by R9 and R8 can be used to limit the VGS voltage of Q3 if
required by the voltage rating of this device. When the
voltage at DELB falls to less than 0.6V, the sink current is
increased to ~1.2mA to firmly pull DELB to 0V.
The voltage at DELB is monitored by the fault protection
circuit so that if the initial 50µA sink current fails to pull DELB
below ~0.6V after the start-up sequencing has completed,
then a fault condition will be detected and a fault time-out
ramp will be initiated on the CDEL capacitor (C7).
Linear-Regulator Controllers (VON, VOFF)
The ISL97522 includes two independent linear-regulator
controllers, in which one is a positive output voltage (VON),
and one is negative. The VON and VOFF linear-regulator
13
controller function diagrams are shown in Figures 17,
and 18, respectively.
AVDD
ISINB
0.1µF
LDO_ON
0.9V
PG_LDOP
+
-
36V
ESD
CLAMP
CP (TO 36V)
RBP
3k
0.1µF
VON (TO 35V)
DRVP
FBP
RP1
CON
RP2
+
GMP
1 : Np
FIGURE 17. VON FUNCTION BLOCK DIAGRAM
Calculation of the Linear Regulator Base-Emitter
Resistors ( RBP and RBN)
For the pass transistor of the linear regulator, low frequency
gain (Hfe) and unity gain freq. (fT) are usually specified in the
datasheet. The pass transistor adds a pole to the loop transfer
function at fp = fT/Hfe. Therefore, in order to maintain phase
margin at low frequency, the best choice for a pass device is
often a high frequency low gain switching transistor. Further
improvement can be obtained by adding a base-emitter resistor
RBE (RBP, RBL, RBN in the Functional Block Diagram), which
increase the pole frequency to: fp = fT*(1+ Hfe *re/RBE)/Hfe,
where re = KT/qIc. So choose the lowest value RBE in the
design as long as there is still enough base current (IB) to
support the maximum output current (IC).
We will take as an example the VON linear regulator. If a
Fairchild MMBT3906 PNP transistor is used as the external pass
transistor, Q11 in the application diagram, then for a maximum VON
operating requirement of 50mA the data sheet indicates HFE_min =
30.
The base-emitter saturation voltage is: Vbe_max = 0.7V.
For the ISL97522, the minimum drive current is:
I_DRVP_min = 2mA.
The minimum base-emitter resistor, RBP, can now be
calculated as:
RBP_min = VBE_max/(I_DRVP_min - Ic/Hfe_min) =
0.7V/(2mA - 50mA/30) = 2.1k
This is the minimum value that can be used - so, we now
choose a convenient value greater than this minimum value;
say 3K. Larger values may be used to reduce quiescent
current, however, regulation may be adversely affected, by
supply noise if RBP is made too high in value.
FN7445.0
December 13, 2006
ISL97522
ISINB
Refer to Typical Application Diagram, the output voltages of
VON, VOFF, and VLOGIC are determined by Equations 11
and 12:
0.1µF
CP (TO -26V)
LDO_OFF
PG_LDON
0.4V
VREF
+
0.1µF
RN2
(EQ. 11)
R 22
V OFF = V FBN + ----------   V FBN – V REF 
R
(EQ. 12)
Charge Pump
1 : Nn
RN1
VOFF (TO -20V)
DRVN
36V
ESD
CLAMP
R 12

V ON = V FBP   1 + ----------
R

11
21
FBN
+
GMN
Set-Up LDOs Output Voltage
RBN
3k
COFF
FIGURE 18. VOFF FUNCTION BLOCK DIAGRAM
The VON power supply is used to power the positive supply
of the row driver in the LCD panel. The DC/DC consists of an
external diode-capacitor charge pump powered from the
switch node (LXB) of the AVDD converter, followed by a low
dropout linear regulator (LDO_ON). The LDO_ON regulator
uses an external PNP transistor as the pass element. The
onboard LDO controller is a wide band (>10MHz)
transconductance amplifier capable of 5mA output current,
which is sufficient for up to 50mA or more output current
under the low dropout condition (forced beta of 10). Typical
VON voltage supported by the ISL97522 ranges from +15V
to +36V. A fault comparator is also included for monitoring
the output voltage. The undervoltage threshold is set at
16.7% below the 1.2V reference.
The VOFF power supply is used to power the negative
supply of the row driver in the LCD panel. The DC/DC
consists of an external diode-capacitor charge pump
powered from the switch node (LXB) of the AVDD converter,
followed by a low dropout linear regulator (LDO_OFF). The
LDO_OFF regulator uses an external NPN transistor as the
pass element. The onboard LDO controller is a wide band
(>10MHz) transconductance amplifier capable of 5mA
output current, which is sufficient for up to 50mA or more
output current under the low dropout condition (forced beta
of 10). Typical VOFF voltage supported by the ISL97522
ranges from -5V to -25V. A fault comparator is also included
for monitoring the output voltage. The undervoltage
threshold is set at 20% above the 1.0V reference level.SetUp LDOs Output Voltage.
14
To generate an output voltage higher than AVDD, single or
multi stages of charge pumps are needed. The number of
stage is determined by the input and output voltage. For
positive charge pump stages:
V OUT + V CE – V INPUT
N POSITIVE  -------------------------------------------------------------V INPUT – 2  V F
(EQ. 13)
where VCE is the dropout voltage of the pass component of
the linear regulator. It ranges from 0.3V to 1V depending on
the transistor. VF is the forward-voltage of the charge pump
rectifier diode.
The number of negative charge pump stages is given by:
V OUTPUT + V CE
N NEGATIVE  ------------------------------------------------V INPUT – 2  V F
(EQ. 14)
To achieve high efficiency and low material cost, the lowest
number of charge pump stages, which can meet the above
requirements, is always preferred.
Charge Pump Output Capacitors
A ceramic capacitor with low ESR is recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be
chosen by Equation 15.
I OUT
C OUT  -----------------------------------------------------2  V RIPPLE  f OSC
(EQ. 15)
Where fSOC is the switching frequency.
High Charge Pump Output Voltage (>36V)
Applications
In the applications where the charge pump output voltage is
over 36V, an external npn transistor need to be inserted into
between DRVP pin and base of pass transistor Q3 as shown
in Figure 19; or the linear regulator can control only one
stage charge pump and regulate the final charge pump
output as shown in Figure 20.
FN7445.0
December 13, 2006
ISL97522
The following equation gives the boundary between
discontinuous and continuous boost operation. For continuous
operation (LX switching every clock cycle) we require that:
CHARGE PUMP
VIN
OUTPUT
OR AVDD
I(AVDD_load) > D*(1-D)*VIN/(2*L*FOSC)
3k
DRVP
NPN
CASCODE
TRANSISTOR
where the duty cycle, D = (AVDD - VIN)/AVDD
Q3
For example, with VIN = 5V, FOSC = 1.0MHz and AVDD =
12V we find continuous operation of the boost converter can
be guaranteed for:
VON
ISL97522
L = 10µH and I(AVDD) > 61mA
L = 6.8µH and I(AVDD) > 89mA
FBP
L = 3.3µH and I(AVDD) > 184mA
Buck Converter
FIGURE 19. CASCODE NPN TRANSISTOR CONFIGURATION
FOR HIGH CHARGE PUMP OUTPUT VOLTAGE
(>36V)
V LOGIC
---------------------- = D
V IN
LX
0.1µF
AVDD
0.1µF
Q3
0.1µF
0.1µF
The Feedback Resistors
(>36V)
The buck converter output voltage is determined by the
following equation:
0.22µF
R 12 + R 13
V LOGIC = ---------------------------  V FBL
R 13
VON
0.47µF
0.1µF
ISL97522
FBP
(EQ. 16)
Where D is the duty cycle of the switching MOSFET.
Because D is always less than 1, the output voltage of buck
converter is lower than input voltage.
3k
DRVP
The buck converter is the step down converter, which
supplies the current to the logic circuit of the LCD system. In
the continuous current mode, the relationship between input
voltage and output voltage is as following:
FIGURE 20. THE LINEAR REGULATOR CONTROLS ONE
STAGE OF CHARGE PUMP
Discontinuous/Continuous Boost Operation and
its Effect on the Charge Pumps
(EQ. 17)
Where R12 and R13 are the feedback resistors of buck
converter to set the output voltage Current drawn by the
resistor network should be limited to maintain the overall
converter efficiency. The maximum value of the resistor
network is limited by the feedback input bias current and the
potential for noise being coupled into the feedback pin. A
resistor network in the order of 300 is recommended.
Buck Converter Input Capacitor
The ISL97522 VON and VOFF architecture uses LX
switching edges to drive diode charge pumps from which
LDO regulators generate the VON and VOFF supplies. It can
be appreciated that should a regular supply of LX switching
edges be interrupted, for example during discontinuous
operation at light AVDD boost load currents, then this may
affect the performance of VON and VOFF regulation depending on their exact loading conditions at the time.
The capacitor should support the maximum AC RMS current
which happens when D = 0.5 and maximum output current.
To optimize VON/VOFF regulation, the boundary of
discontinuous/continuous operation of the boost converter
can be adjusted, by suitable choice of inductor given VIN,
VOUT, switching frequency and the AVDD current loading, to
be in continuous operation.
An inductor value in the range 3.3-10µH is recommended for
the buck converter. Besides the inductance, the DC
resistance and the saturation current should also be
considered when choosing buck inductor. Low DC
resistance can help maintain high efficiency, and the
15
I acrms  C IN  =
(EQ. 18)
D   1 – D   IO
Where IO is the output current of the buck converter.
Buck Inductor
FN7445.0
December 13, 2006
ISL97522
saturation current rating should be at least maximum output
current plus half of ripple current.
on. Hence there is minimum load requirement to charge the
bootstrap capacitor properly.
Buck MOSFET
Start-Up Sequence
The principle to select Buck MOSFET is similar to that of
Boost. The voltage of stress of buck converter should be
maximum input voltage plus reasonable margin, and the
current rating should be over the maximum output current.
The rDS(ON) of this MOSFET should be in the range from
20m to 50m.
Figure 21 shows a detailed start-up sequence waveform. For
a successful power-up, there should be six peaks at VCDLY.
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
Rectifier Diode (Buck Converter)
A Schottky diode is recommended due to fast recovery and
low forward voltage. The reverse voltage rating should be
higher than the maximum input voltage. The average current
should be as the following equation,
I AVG =  1 – D *I O
(EQ. 19)
Where IO is the output current of buck converter.
Output Capacitor (Buck Converter)
Four 10µF or two 22µF ceramic capacitors are
recommended for this part. The overshoot and undershoot
will be reduced with more capacitance, but the recovery time
will be longer.
PI Loop Compensation (Buck Converter)
The buck converter of ISL97522 can be compensated by a
RC network connected from CINTL pin to ground. C27 =
4.7nF and R17= 2k RC network is used in the demo board.
The larger value resistor can lower the transient overshoot,
however, at the expense of stability of the loop.
The stability can be optimized in a similar manner to that
described in the section on "PI Loop Compensation (Boost
Converter)”.
Bootstrap Capacitor (C28)
This capacitor is used to provide the supply to the high driver
circuitry for the buck MOSFET. The bootstrap supply is
formed by an internal diode and capacitor combination. A
1µF is recommended for ISL97522. A low value capacitor
can lead to overcharging and in turn damage the part.
If EN is L, the device is powered down. If EN is H, and the
input voltage (VIN) exceeds 2.5V, an internal current source
starts to charge CDLY to an upper threshold using a fast
ramp followed by a slow ramp. If EN is low at this point, the
CDLY ramp will be delayed until EN goes high.
The first four ramps on CDLY (two up, two down) are used to
initialize the fault protection switch and to check whether
there is a fault condition on CDLY or VREF. If a fault is
detected, the outputs and the input protection will turn off
and the chip will power down.
If no fault is found, CCDLY continues ramping up and down
until the sequence is completed.
During the second ramp, the device checks the status of
VREF and over temperature.
Initially the boost is not enabled so VBOOST rises to VINVDIODE through the output diode. Hence, there is a step at
VBOOST during this part of the start-up sequence. If this step
is not desirable, an external PMOS FET can be used to delay
the output until the boost is enabled internally. The delayed
output appears at AVDD.
VBOOST soft-starts at the beginning of the third ramp. The
soft-start ramp depends on the value of the CDLY capacitor.
For CDLY of 220nF, the soft-start time is ~2ms.
VOFF turns on at the start of the fourth peak. At the fifth
peak, the open drain o/p DELB goes low to turn on the
external PMOS Q3 to generate a delayed VBOOST output.
VON is enabled at the beginning of the sixth ramp. AVDD,
VOFF, DELB and VON are checked at end of this ramp.
Vlogic’s start-up is controlled by ENL. When ENL is L, Vlogic
is off, and when ENL is H, VLOGIC is on.
If the load is too light, the on-time of the low side diode may
be insufficient to replenish the bootstrap capacitor voltage. In
this case, if VIN-VBUCK < 1.5V, the internal MOSFET pull-up
device may be unable to turn-on until VLOGIC falls. Hence,
there is a minimum load requirement in this case. The
minimum load can be adjusted by the feedback resistors
to FBL.
The bootstrap capacitor can only be charged when the
higher side MOSFET is off. If the load is too light which can
not make the on time of the low side diode be sufficient to
replenish the boot strap capacitor, the MOSFET can’t turn
16
FN7445.0
December 13, 2006
CHIP DISABLED
FAULT DETECTED
VON SOFT-START
DELB ON
VOFF ON
AVDD,
SOFT-START
VREF ON
ISL97522
VCDLY
EN
ENL
VLOGIC
VREF
VBOOST
tON
tOS
VOFF
tDEL1
DELAYED
VBOOST
tDEL2
VON
FAULT
PRESENT
START-UP SEQUENCE
TIMED BY CDLY
NORMAL
OPERATION
VON SLICE
FIGURE 21. ISL97522 START-UP SEQUENCE
17
FN7445.0
December 13, 2006
ISL97522
Fault Protection
Component Selection for Start-Up Sequencing and
Fault Protection
During the startup sequence, prior to BOOST soft-start,
VREF is checked to be within ±20% of its final value and the
device temperature is checked. If either of these are not
within the expected range, the part is disabled until the
power is recycled or EN is toggled.
The CREF capacitor is typically set at 220nF and is required
to stabilize the VREF output. The range of CREF is from
22nF to 1µF and should not be more than five times the
capacitor on CDEL to ensure correct start-up operation.
If CDELAY is shorted low, then the sequence will not start,
while if CDELAY is shorted H, the first down ramp will not
occur and the sequence will not complete.
The CDEL capacitor is typically 220nF and has a usable
range from 47nF minimum to several microfarads - only
limited by the leakage in the capacitor reaching µA levels.
Once the start-up sequence is completed, the chip
continuously monitors CDLY, DELB, FBP, FBL, FBN, VREF
and FBB for faults. During this time, the voltage on the CDLY
capacitor remains at 1.15V until either a fault is detected, or
the EN pin is pulled low.
CDEL should be at least 1/5 of the value of CREF (See
above). Note with 220nF on CDEL the fault time-out will be
typically 50ms and the use of a larger/smaller value will vary
this time proportionally (e.g. 1µF will give a fault time-out
period of typically 230ms).
A fault on CDELAY, VREF or temperature will shut down the
chip immediately. If a fault on any other output is detected,
CDELAY will ramp up linearly with a 5µA (typical) current to
the upper fault threshold (typically 2.4V), at which point the
chip is disabled until the power is recycled or EN is toggled.
If the fault condition is removed prior to the end of the ramp,
the voltage on the CDLY capacitor returns to 1.15V.
Fault Sequencing
Typical fault thresholds for FBP, FBL, FBN and FBB are
included in the tables. DELB fault threshold is typically 0.6V.
CINTB and CINTL have an internal current-limited clamp to
keep the voltage within their normal ranges. If they are
shorted low, the regulators will attempt to regulate to 0V.
If any of the regulated outputs (AVDD, VON, VOFF or
VLOGIC) are driven above their target levels the drive
circuitry will switch off until the output returns to its expected
value.
If AVDD and VLOGIC are excessively loaded, the current
limit will prevent damage to the chip. While in current limit,
the part acts like a current source and the regulated output
will drop. If the output drops below the fault threshold, a
ramp will be initiated on CDELAY and, provided that the fault
is sustained, the chip will be disabled on completion of the
ramp.
In some circumstances, (depending on ambient temperature
and thermal design of the board), continuous operation at
current limit may result in the over-temperature threshold
being exceeded, which will cause the part to disable
immediately.
All I/O also have ESD protection, which in many cases will
also provide overvoltage protection, relative to either ground
or VDD. However, these will not generally operate unless
abs max ratings are exceeded.
The ISL97522 has an advanced fault detection system
which protects the IC from both adjacent pin shorts during
operation and shorts on the output supplies.
A high quality layout/design of the PCB, in respect of
grounding quality and decoupling is necessary to avoid
falsely triggering the fault detection scheme - especially
during start-up. The user is directed to the layout guidelines
and component selection sections to avoid problems during
initial evaluation and prototype PCB generation.
Over-Temperature Protection
An internal temperature sensor continuously monitors the
die temperature. In the event that the die temperature
exceeds the thermal trip point of 140°C, the device will shut
down.
Layout Recommendation
The device's performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
There are some general guidelines for layout:
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
2. Place VREF, VDC and VDCP bypass capacitors close to
the pins.
3. Minimize the length of traces carrying fast signals and
high current.
4. All feedback networks should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point near the main
decoupling capacitors.
18
FN7445.0
December 13, 2006
ISL97522
6. The exposed die plate, on the underneath of the
package, should be soldered to an equivalent area of
metal on the PCB. This contact area should have multiple
via connections to the back of the PCB as well as
connections to intermediate PCB layers, if available, to
maximize thermal dissipation away from the IC.
7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track
and ground plane area connected to the exposed die
plate should be maximized and spread out as far as
possible from the IC. The bottom and top PCB areas
especially should be maximized to allow thermal
dissipation to the surrounding air.
8. A signal ground plane, separate from the power ground
plane and connected to the power ground pins only at the
exposed die plate, should be used for ground return
connections for feedback resistor networks (R1, R11,
R41) and the VREF capacitor, C25, the CDELAY capacitor
C7 and the integrator capacitor C30, C27.
9. Minimize feedback input track lengths to avoid switching
noise pick-up.
19
FN7445.0
December 13, 2006
ISL97522
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L38.5x7B (One of 10 Packages in MDP0046)
38 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220)
A
MILLIMETERS
D
N
(N-1)
(N-2)
B
1
2
3
PIN #1
I.D. MARK
E
(N/2)
2X
0.075 C
2X
0.075 C
0.10 M C A B
b
(N-2)
(N-1)
N
N LEADS
TOP VIEW
L
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
0.00
0.02
0.05
-
D
5.00 BSC
-
D2
3.50 REF
-
E
7.00 BSC
-
E2
5.50 REF
-
L
0.35
0.40
0.45
-
b
0.23
0.25
0.27
-
c
0.20 REF
-
e
0.50 BSC
-
N
38 REF
4
ND
7 REF
6
NE
12 REF
5
PIN #1 I.D.
Rev 0 5/06
3
NOTES:
1
2
3
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
(E2)
4. N is the total number of terminals on the device.
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
NE 5
(N/2)
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
7
(D2)
7. Inward end of terminal may be square or circular in shape with
radius (b/2) as shown.
BOTTOM VIEW
0.10 C
e
C
(c)
SEATING
PLANE
0.08 C
N LEADS
& EXPOSED PAD
C
2
A
(L)
SEE DETAIL "X"
A1
SIDE VIEW
N LEADS
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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20
FN7445.0
December 13, 2006
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