Application Note 1626 Author: Yi Tian ISL97645A Evaluation Board Application Manual Description Features The ISL97645A EVB is an evaluation board for the ISL97645A, a DC/DC voltage regulator for TFT-LCD displays with screen sizes up to 20". ISL97645A integrates a boost converter, a VON slice circuit, a supply monitor circuit and a high performance VCOM amplifier. This evaluation board is designed to: • A complete TFT-LCD PMIC evaluation platform for the ISL97645A • Input voltage: 2.7V to 5.5V • Non-synchronous boost for AVDD supply 1. Deliver up to 0.8A current for AVDD supply to the source / column driver ICs. • VON and VOFF charge pumps for gate driver IC supplies 2. Generate different VON (gate high) and VOFF (gate low) • Supply monitor circuit to generate the RESET signal • VON slice circuit for VGH_M 3. Modulated VGH_M output for gate high voltage with desired delay time and discharging slope using the VON slice circuit • Op Amp follower for VCOM 4. The high performance amplifier generates the LCD pixel common bias voltage (VCOM) • RoHS compliant 5. Generate a RESET signal correctly at power on and off The ISL97645A evaluation board provides a dip switch that allows users to select either 650kHz or 1.2MHz and the enable signal to enable or disable the IC. Pinout ISL97645A (24 LD 4x4 QFN) VGH RE CE PGND FB ENABLE TOP VIEW 24 23 22 21 20 19 3 16 FREQ2 VDPM 4 15 COMP VDD1 5 14 SS VDD2 6 13 RESET April 11, 2011 AN1626.0 AGND 10 1 11 12 VDIV VFLK CD2 17 VIN2 POS 2 NEG VGH_M OUT 18 LX 9 • The following instruments will be needed to perform testing: - Power supplies - DC Electronic load - Multimeters - Oscilloscope - Resistors - Cables and wires PART # 1 8 What is Needed Ordering Information GND 7 • Layout Guidelines ISL97645AIRZ-EVALZ DESCRIPTION Evaluation Board for ISL97645A CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. Copyright Intersil Americas Inc. 2011. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 1626 Quick Setup Guide Notes: Step 1: Connect power supply between headers of VIN and VIN_GND. The positive output of the power supply should be connected to VIN header. Set power supply voltage between 2.7V and 5.5V, and current limit at 4A. Step 2: Connect the positive and negative inputs of the Electronic load to AVDD header and AVDD_GND, respectively. The load current should not exceed the maximum output current in Table 1. Step 3: Put S1 to the direction of the arrow to tie FREQ pin to VIN to set 1.2MHz switching frequency; put S1 to the reverse direction of the arrow to pull FREQ to ground with R16 to set 650kHz. Step 4: Put S2 to the direction of the arrow to tie ENABLE pin to VIN to enable the part; put S2 to the reverse direction of the arrow to pull Enable to ground with R17 to disable the part. 1). Table 1 shows typical maximum output current values for 1.2MHz switching frequency and 10µH inductor. 2). Maximum current values in actual application may vary with component variance 3). Feedback compensation parameters, input and output capacitance of the boost may need to be modified to keep good stability with maximum peak inductor current of 2.6A. Gate Pulse Modulator Timing Diagram ISL97645A evaluation board can generate a modulated VGH_M with a fixed power on delay time, a discharging slope and a delay time to the falling edge of VFLK. The waveform of VGH_M is shown in Figure 1 and Figure 2. Step 5: Connect VDIV to a resistive divider between headers of VIN and VIN_GND. Step 6: Connect Electronic load between headers of VON and Vin_GND. The positive input of the E-load should be connected to VON header, the negative input of the E-load should be connected to Vin_GND. Connect E-load between headers of VOFF and Vin_GND. The positive input of the E-load should be connected to Vin_GND header, the negative input of the E-load should be connected to VOFF. Set current values of E-load. The values of VON and VOFF at different loadings are shown in Table 2. Step 7: Connect header of VON to VGH pin Step 8: Connect input from signal generator between headers of VFLK and SGND. Select y to square waveform with an amplitude of 3.3V and frequency of 50kHz Step 9: Connect power supply between headers of POS and SGND. Set power supply voltage at desired VCOM value. FIGURE 1. POWER ON DELAY TIME Step 10: Make sure all the connections on the EVB are correct, then turn on power supply and E-loads. The part starts to operate. Maximum Output Current The MOSFET current limit is 2.6A. This limits the maximum output current that ISL97645A can drive. Table 1 shows the maximum output current IOMAX at different input and output voltages. TABLE 1. TYPICAL MAXIMUM OUTPUT CURRENT VIN (V) VOUT (V) IOMAX (mA) 3.3 8 800 3.3 12 480 5 8 1370 5 12 850 FIGURE 2. VGH_M 2 AN1626.0 Application Note 1626 Supply Monitor Circuit Layout Recommendation The supply monitor circuit monitors VDIV and sets open-drain output RESET low. When RESET changes to low and VGH is above 2.5V, VGH_M is pulled up to follow VGH until VGH falls below 2.5V. Figure 3 shows the RESET and VGH_M voltages at power off (when VIN is dropping). The device performance including efficiency, output noise, transient response and control loop stability is dramatically affected by the PCB layout. PCB layout is critical, especially at high switching frequency. Following are some general guidelines for layout: 1. Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. Place VIN and VDD bypass capacitors close to the pins. 3. Reduce the loop area with large AC amplitudes and fast slew rate. 4. The feedback network should sense the output voltage directly from the point of load, and should be placed to the IC and as far away from LX node as possible. 5. The power ground (PGND) and signal ground (SGND) pins should be connected at only one point at the exposed die plate, underneath the package. 6. The exposed die plate should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC. FIGURE 3. VGH_M IS PULLED TO VGH AT POWER OFF VON and VOFF at Different Loadings The boost converter integrated in ISL97645A is capable to output up to 20V AVDD. This ISL97645A EVA board generates VON and VOFF based on the output AVDD designed. Table 2 shows different values of VON and VOFF at different AVDD and different loadings. By removing R18 and adding C24 and D3 into the circuit, the charge pump is able to deliver a VON higher than 2*AVDD. 7. To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bottom and top PCB areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. A signal ground plane, separated from the power ground plane and connected to the power ground pins only at the exposed die plate, should be used for ground return connections for control circuit. 9. Minimize feedback input track lengths to avoid switching noise pick-up. The EVB board layout on page 5 page 7 is available to illustrate the proper layout implementation. TABLE 2. TYPICAL VON AND VOFF FOR DIFFERENT LOADINGS VON (V) VOFF (V) ILOADING AVDD = 8V Single Stage AVDD = 8V Two Stages AVDD = 10V AVDD = 12V AVDD = 8V AVDD = 10V AVDD = 12V 1mA 15.2 23.4 20.6 23.8 4.3 4.3 4.4 5mA 15.1 23.2 20.2 23.3 4.3 4.3 4.3 10mA 14.7 23.0 20.0 23.2 4.2 4.2 4.3 3 AN1626.0 EVB Design Schematic 3 R18 Q1 MMBT3906 D4 P16 1 Voff C28 1uF/16V 2 C27 0.1uF/25V 1 2 1 2 C23 0.1uF/25V BAT54S 3 R4 1K AVDD C25 1uF/25V Von 3 P17 0 D3 OPEN D2 BAT54S C26 0.1uF/25V C22 0.1uF/25V C24 OPEN 4 S1 P15 1 2 MMSZ 5231B Z1 VGH 4 3 P1 AVDD_GND SW DIP-2 R17 10K R16 10K R3 10 P3 P4 VIN_GND SGND 10 P14 10uH C19 0.47u/40V 20 19 FB PGND SHDN 22 21 CE 24 23 RE VIN2 VDPM COMP VDD1 SS NEG 8 P9 R7 0 VS_GPM RESET P13 AVDD 18 17 C3 10uF/25V C17 1uF 16 C10 15 2.2nF 14 13 VDIV 6 VDD2 C20 0.47u/16V 7 1nF/16V LX FREQ OUT VFLK VIN R14 10K C16 OPEN C4 10uF/25V C5 10uF/25V C6 10uF/25V AVDD R1 10K R5 C7 OPEN 10K C9 10nF R2 1.3K 12 C18 0.47u/16V C12 5 D1 MBRM120T3 VFLK CD2 4 P11 VGH_M AGND 3 11 C14 1500pF POS 2 VGH_M GND 9 P12 10 1 C2 10uF/6.3V R6 C13 4.99K 470p VGH U1 ISL97645A C1 10uF/6.3V R9 100K C8 OPEN P2 RESET C11 1nF P8 R8 OPEN VS_AMP R13 0 R12 0 P5 C15 C21 0.1uF R10 0 R11 OPEN CD2 100K AN1626.0 P7 OUT POS VDIV Application Note 1626 R15 L1 Application Note 1626 EVB Layout FIGURE 4. EVB ASSEMBLY LAYER 5 AN1626.0 Application Note 1626 EVB Layout (Continued) FIGURE 5. TOP LAYER 6 AN1626.0 Application Note 1626 EVB Layout (Continued) FIGURE 6. BOTTOM LAYER 7 AN1626.0 Application Note 1626 BOM for ISL97645A Evaluation Board PART TYPE DESIGNATOR FOOTPRINT 10k R1 603 1.3k R2 603 10 R3 603 1k R4 603 10k R5 603 4.99k R6 603 0 R7 603 OPEN R8 603 100k R9 603 0 R10 603 100k R11 603 0 R12 603 0 R13 603 10k R14 603 10 R15 603 10k R16 603 10k R17 603 0 R18 805 10µF/6.3V C1 805 10µF/6.3V C2 805 10µF/25V C3 1210 10µF/25V C4 1210 10µF/25V C5 1210 10µF/25V C6 1210 OPEN C7 603 OPEN C8 603 10nF C9 603 2.2nF C10 603 1nF C11 603 1nF/16V C12 603 470p C13 603 1500pF C14 1206 OPEN C15 603 OPEN C16 603 1uF C17 603 0.47µF/16V C18 603 0.47µF/16V C19 805 0.47µF/16V C20 603 0.1µF C21 603 8 AN1626.0 Application Note 1626 BOM for ISL97645A Evaluation Board (Continued) PART TYPE DESIGNATOR FOOTPRINT 0.1µF/25V C22 603 0.1µF/25V C23 603 OPEN C24 603 1µF/25V C25 603 0.1µF/25V C26 603 0.1µF/25V C27 603 1µF/16V C28 603 MBRM120T3 D1 Case475 BAT54S D2 SOT-23 OPEN D3 SOT-23 BAT54S D4 SOT-23 10µH L1 RLF7030 AVDD_GND P1 POWERPOST LDO_GND P2 POWERPOST VIN_GND P3 POWERPOST SGND P4 POWERPOST VDIV P5 POWERPOST POS P6 POWERPOST OUT P7 POWERPOST VS_AMP P8 POWERPOST VS_GPM P9 POWERPOST CD2 P10 POWERPOST VFLK P11 POWERPOST VGH_M P12 POWERPOST AVDD P13 POWERPOST VIN P14 POWERPOST VGH P15 POWERPOST VON P16 POWERPOST VOFF P17 POWERPOST MMBT3906 Q1 SOT-23 SW DIP-2 S1 DIP4 ISL97645A U1 MMSZ 5233B Z1 SOD-123 Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 9 AN1626.0