DATASHEET

ISL97632
DESIGNS
FOR NEW
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ISL97634
Data Sheet
March 22, 2010
FN9239.3
LED Driver with 1-Wire Dimming
Features
The ISL97632 represents an efficient and highly integrated
PWM boost LED driver that is suitable for 1.8” to 3.5” LCDs
that employ 2 to 7 white LEDs for backlighting. With
integrated Schottky diode, OVP, and dynamic digital
dimming capability, the ISL97632 provides a simple, reliable,
and flexible solution to the backlight designers.
• 1-Wire 5-Bit Digital Dimming
The ISL97632 features a simple 1-Wire digital interface that
provides a 5-bit dimming control. The dimming signal adjusts
the FB voltage and therefore the LED brightness in a DC
manner in 32 linear steps. An EN pin can be used to provide
a zero brightness setting or shutdown power saving function.
• 86% Efficiency
The ISL97632 is available in the 8 Ld TDFN (2mmx3mm)
package. There are 14V, 18V, and 26V OVP options that are
suitable for 3, 4, and 7 LEDs (3.5V/20mA type) backlight
applications respectively. The ISL97632 is specified for
operation over the -40°C to +85°C ambient temperature at
input voltage from 2.4V to 5.5V.
Pinout
ISL97632
(8 LD 2x3 TDFN)
TOP VIEW
GND
1
8 LX
VIN
2
7 VOUT
EN
3
6 FBSW
SDIN
4
5 FB
• Drives Up to 7 LEDs in Series (3.5V/20mA type)
• OVP (14V, 18V and 26V for 3, 4, and 7 LEDs applications)
• Integrated Schottky Diode
• 2.4V to 5.5V input
• 1.4MHz Switching Frequency Allows Small LC
• Enable for Shutdown Function or Zero Brightness Setting
• 1µA Shutdown Current
• Internally Compensated
• 8 Ld TDFN (2mmx3mm)
• Pb-Free (RoHS Compliant)
Applications
• LED backlighting for
- Cell phones
- Smartphones
- MP3
- PMP
- Automotive Navigation Panel
- Portable GPS
Ordering Information
PART NUMBER
(Note)
ISL97632IRT14ZT*
Typical Application Circuit
10µH OR 22µH
VIN
VIN
LX
EN
VOUT
SDIN
FBSW
GND
FB
1
TEMP
RANGE
PART
(°C)
MARKING
PACKAGE
Tape and Reel
(Pb-Free)
PKG.
DWG.
NO.
ELB
-40 to +85 8 Ld 2x3 TDFN L8.2x3A
ISL97632IRT14ZTK* ELB
-40 to +85 8 Ld 2x3 TDFN L8.2x3A
ISL97632IRT18ZT*
-40 to +85 8 Ld 2x3 TDFN L8.2x3A
ELC
ISL97632IRT18ZTK* ELC
-40 to +85 8 Ld 2x3 TDFN L8.2x3A
ISL97632IRT26ZT*
ELD
-40 to +85 8 Ld 2x3 TDFN L8.2x3A
ISL97632IRT26ZTK* ELD
-40 to +85 8 Ld 2x3 TDFN L8.2x3A
* Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006-2008, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL97632
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
LX Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V
FBSW Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Thermal Resistance (Typical, Note 1, 2)
Operating Conditions
JA (°C/W)
JC (°C/W)
TDFN Package . . . . . . . . . . . . . . . . . .
70
10.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed over temperature of -40°C to +85°C unless otherwise stated. Typical values are for
information purposes only at TJ = TC = TA = +25°C.
NOTES:
1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
VIN = VEN = 3V. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested.
DESCRIPTION
VIN
Supply Voltage
IIN
Supply Current
CONDITION
MIN
TYP
2.4
EN = 3V, enabled, not switching
0.8
EN = 0V, disabled
MAX
UNIT
5.5
V
1.5
mA
1
µA
1,600
kHz
Fsw
Switching Frequency
1,300
1,450
DMAX
Maximum Duty Cycle
90
95
%
LX Current
400
470
mA
900
m
ILIM
RSW(LX)
ILEAK
VFB
LX Switch ON-Resistance
ILX = 100mA
LX Switch Leakage Current
VLX = 28V
Feedback Voltage
Serial interface setting = 15 (center)
90
Serial interface setting = S (S = 0,1 ..31)
Serial interface setting = 0
IFB
RSW(FBSW)
FB Pin Bias Current
95
1
µA
100
mV
9.8 + 5.68 x S
mV
9.8
mV
VFB = 95mV
1
FBSW Switch ON-Resistance
µA

10
VDIODE
Schottky Diode Forward
Voltage
IDIODE = 100mA, TA = +25°C
600
OVP
Overvoltage Protection
ISL97632IRT14Z
14
V
ISL97632IRT18Z
18
V
ISL97632IRT26Z
26
VIL
Logic Low Voltage
VIH
Logic High Voltage
850
mV
28
V
0.6
V
1.5
V
tLOGIC1
Timing Range for Logic 1
SDIN = low
15
45
µs
tLOGIC0
Timing Range for Logic 0
SDIN = low
90
120
µs
tLOGIC-LOAD
Timing Range for Load
SDIN = low
215
µs
tLOGIC-HIGH
Minimum Valid SDIN High
Time
SDIN = high
3
µs
2
FN9239.3
March 22, 2010
ISL97632
Block Diagram
VIN (2.4V TO 5.5V)
L
CIN
EN
VIN
LX
1.4MHZ OSCILLATOR AND RAMP
GENERATOR
ISL97632
VOUT
COUT
PWM
COMPARATOR
FET
PWM LOGIC
CONTROLLER
DRIVER
2 to 7 LEDs
CURRENT
SENSE
GND
FBSW
EN
GM AMP
COMPENSATION
GM
AMPLIFIER
FB
10mV to 186mV
SERIAL
INTERFACE
SDIN
BANDGAP
REFERENCE
GENERATOR
RSET
Pin Descriptions
PIN
NUMBER
PIN
NAME
1
GND
Ground Pin. Connect to local ground.
2
VIN
Input Supply Pin. Connect to the input supply voltage, the inductor and the input supply decoupling
capacitor.
3
EN
Enable Pin. Connect to enable signal to turn-on or off the device. Active High.
4
SDIN
5
FB
6
FBSW
Optional FB Disconnect Switch.
7
VOUT
Output Pin. Connect to the anode of the top LED and the output filter capacitor.
8
LX
3
DESCRIPTION
Single-Wire XSD Digital Interface (1-Wire Interface).
Feedback Pin. Connect to the cathode of bottom LED and the sense resistor.
Switching Pin. Connect to inductor.
FN9239.3
March 22, 2010
ISL97632
Single-Wire Serial Interface
30µs
100µs
'1'
'0'
0
200
'1'
400
220µs
'0'
600
'0'
800
'LOAD'
1000
1200
µs
FIGURE 1. 1-WIRE XSD INTERFACE
The ISL97632 uses a simple single-wire serial interface for
programming the output brightness of the LEDs. A 5-bit
interface is used to give a total of 32 levels of output
brightness. The interface uses a normally high connection
for use with open-drain driving schemes and Intersil’s
proprietary 1-Wire XSD bus. When held low for between
15µs and 45µs, the interface registers a logic 1. When held
low for between 90µs and 120µs the interface registers a
logic 0. When held low for greater that 215µs, the interface
loads the last 5 bits into the brightness control register and
updates the brightness level. The required minimum high
time is 3µs. This simple single-wire programming is
summarized as follows:
• Logic 0 = Negative pulse >90µs and <120µs
• Logic 1 = Negative pulse >15µs and <45µs
• Load = Negative pulse >215µs
Figure 1 shows an example of programming a binary code of
10100 and load it in to the device serial register.
The serial interface is automatically reset to 0 when the
device is disabled, or enters UVLO. Therefore, when the part
is enabled, the output brightness is automatically set to the
minimum level.
4
FN9239.3
March 22, 2010
ISL97632
Typical Performace Curves
90
1.0
4.2V IN 4 LEDs OUT (15µH)
85
0.8
0.6
3.6V IN 4 LEDs OUT (10µH)
75
Iq (mA)
EFFICIENCY (%)
80
3.6V IN 4 LEDs OUT (15µH)
70
4.2V IN 4 LEDs OUT (10µH)
65
0.4
0.2
4.2V IN 4 LEDs OUT (22µH)
60
55
0
3.6V IN 4 LEDs OUT (22µH)
50
0
5
10
15
20
25
30
35
40
- 0.2
45
0
1
2
IOUT (mA)
3
4
5
VIN (V)
FIGURE 2. EFFICIENCY vs LED CURRENT
FIGURE 3. QUIESCENT CURRENT vs VIN (ENAB = HI)
19.76
20.08
19.74
IO (mA)
19.72
20.00
19.70
19.68
19.66
19.96
19.64
19.62
2.5
19.92
0
5
10
15
VOUT (V)
20
25
30
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
FIGURE 4. LOAD REGULATION (VIN = 4V)
FIGURE 5. LINE REGULATION
40
RSET = 4.7
35
30
IO (mA)
IO (mA)
20.04
25
20
15
10
5
0
0
5
10
15
20
25
30
35
CODE = DECIMAL
FIGURE 6. ILED vs PROGRAMMING CODES
5
FN9239.3
March 22, 2010
ISL97632
Detailed Description
The ISL97632 uses a constant frequency, current mode
control scheme to provide excellent line and load regulation.
There are three OVP models for driving 3, 4, and 7 LEDs
(3.5V/20mA type) and their OVP thresholds are set at 14V,
18V, and 26V respectively. The ISL97632 operates from an
input voltage of 2.4V to 5.5V and ambient temperature
from -40°C to +85°C. The switching frequency is around
1.45MHz and allows the driver circuit to employ small LC
components. The forward current of the LED is set using the
RSET resistor. In the steady state mode, the LED current is
given by Equation 1:
V FB  S 
9.8mV + 5.68mV  S
I LED  S  = -------------------- = -------------------------------------------------------R SET
R SET
(EQ. 1)
where S is the 5-bit Serial Interface Setting or Digital code
from 0 to 31 programmed in the XSD single-wire interface.
The default setting is 0 and the VFB is at minimum.
Dimming Control
The ISL97632 powers up to provide minimium current. By
programming the digital code with the Intersil’s 1-Wire XSD
interface as shown in Figure 1, the current can be changed
linearly with the digital code from 0 to 31. Figure 6 shows
LED current versus the programming codes.
Overvoltage Protection
The ISL97632 comes with overvoltage protection. The
OVP trip points are at 14V, 18V, and 26V for
ISL97632IRT14Z, ISL97632IRT18Z, and
ISL97632IRT26Z respectively. The maximum numbers of
LEDs and OVP threshold are shown in Table 1. When the
device reaches the OVP, the LX stops switching, disabling
the boost circuit until VOUT falls about 7% below the OVP
threshold. At this point, LX will be allowed to switch again.
The OVP event will not cause the device to shutdown.
TABLE 1.
PART NO.
OVP
MAX NO. OF
LEDS
ISL97632IRT14Z
14V
3
70mA
ISL97632IRT18Z
18V
4
50mA
ISL97632IRT26Z
26V
7
30mA
MAX ILED
There are three OVP options. The 3 LEDs application
should use the 14V OVP device. The 7 LEDs application
should use the 26V OVP device. An output capacitor that is
only rated for the required voltage range can therefore be
used which will optimize the component costs in some
cases.
Shut-Down
An active high EN pin is normally on but this pin can be used
as a shutdown power saving function or zero brightness
setting. When taken low the EN pin places the ISL97632 into
power down mode down where the supply current is
reduced to less than 1µA. The EN pin cannot be used as
6
PWM input, as the part resets to 0 whenever EN is low. To
resume previous setting, the device needs to be
reprogrammed.
Output Disconnect
The ISL97632 features a FBSW feedback disconnect switch
that can be used in between the LED and RSET for an
optional short-circuit protection. For example, the user may
build an external short circuit detection to monitor the VOUT.
If the VOUT goes low due to one or more LEDs which are
shorted, the circuit can release the EN and FBSW switch to
disconnect the LEDs.
Components Selection
The input capacitance is typically 0.22µF to 4.7µF. The
output capacitor should be in the range of 0.22µF to 1µF.
X5R or X7R type of ceramic capacitors of the appropriate
voltage rating are recommended.
When choosing an inductor, make sure the average and
peak current ratings are adequate by using Equations 2, 3
and 4 (80% efficiency assumed):
I LED  V OUT
I LAVG = --------------------------------0.8  V IN
(EQ. 2)
1
I LPK = I LAVG + ---  I L
2
(EQ. 3)
V IN   V OUT – V IN 
I L = --------------------------------------------------L  V OUT  f OSC
(EQ. 4)
Where:
• IL is the peak-to-peak inductor current ripple in Amps
• L is the inductance in H.
• fOSC is the switching frequency, typically 1.45MHz
The ISL97632 supports a wide range of inductance values
(10µH~82µH). For lower inductor values or lighter loads, the
boost inductor current may become discontinuous. For high
boost inductor values, the boost inductor current will be in
continuous mode.
In addition to the inductor value and switching frequency, the
input voltage, the number of LEDs and the LED current also
affect whether the converter operates in continuous
conduction or discontinuous conduction mode. Both operating
modes are allowed and normal. The discontinuos conduction
mode yields lower efficiency due to higher peak current.
Compensation
The product of the output capacitor and the load create a
pole while the inductor creates a right half plane zero. Both
attributes degrade the phase margin but the ISL97632 has
an internal compensation network that ensures the device
operates reliabily under the specified conditions. The
internal compensation and the highly integrated functions of
the ISL97632 make it a design friendly device to be used in
high volume high reliability applications.
FN9239.3
March 22, 2010
ISL97632
Applications
Efficiency Improvement
Figure 2 on page 5 shows the efficiency measurements. The
choice of the inductor has a significant impact on the power
efficiency. As shown in Equation 4, the higher the
inductance, the lower the peak current therefore the lower
the conduction and switching losses. On the other hand, it
has also a higher series resistance. Nevertheless, the
efficiency improvement from lowering the peak current is
greater than the impact of the resistance increase with larger
value of inductor. Efficiency can also be improved for
systems that have high supply voltages. Since the ISL97632
can only supply from 2.4V to 5.5V, VIN must be separated
from the high supply voltage for the boost circuit as shown in
Figure 7 and the efficiency improvement is shown in
Figure 8.
C3 0.22µF
L1
Vs = 12V
C1
1
D2
2
22µH
1µF
D3
VIN = 2.7V TO 5.5V
C2 0.1µF
D1
D4 25mA
VIN
LX
VOUT
ISL97632
FBSW
EN
D5
D6
FB
SDIN
GND
R1
4
FIGURE 7. SEPARATE HIGH INPUT VOLTAGE FOR HIGHER
EFFICIENCY OPERATION
90
VS = 12V
EFFICIENCY (%)
85
VS = 9V
the ISL97632 is not sufficient. However, the ISL97632 can
be used as an LED controller with an external protection
MOSFET connected in cascode fashion to achieve higher
output voltage. A conceptual 9 LEDs driver circuit is shown
in Figure 9. A 40V logic level N-Channel MOSFET is
configured such that its drain ties between the inductor and
the anode of Schottky diode, its gate ties to the input, and its
source ties to the ISL97632 LX node connecting to the drain
of the internal switch. When the internal switch turns on, it
pulls the source of M1 down to ground, and LX conducts as
normal. When the internal switch turns off, the source of M1
will be pulled up by the follower action of M1, limiting the
maximum voltage on the ISL97632 LX pin to below VIN, but
allowing the output voltage to go much higher than the
breakdown limit on the LX pin. The switch current limit and
maximum duty cycle will not be changed by this setup, so
input voltage will need to be carefully considered to make
sure that the required output voltage and current levels are
achievable. Because the source of M1 is effectively floating
when the internal LX switch is off, the drain-to-source
capacitance of M1 may be sufficient to capacitively pull the
node high enough to breaks down the gate oxide of M1. To
prevent this, VOUT should be connected to VIN, allowing the
internal Schottky to limit the peak voltage. This will also hold
the VOUT pin at a known low voltage, preventing the built in
OVP function from causing problems. This OVP function is
effectively useless in this mode as the real output voltage is
outside its intended range. If the user wants to implement
their own OVP protection (to prevent damage to the output
capacitor, they should insert a zener from VOUT to the FB
pin. In this setup, it would be wise not to use the FBSW to FB
switch as otherwise the zener will have to be a high power
one capable of dissipating the entire LED load power. Then
the LED stack can then be connected directly to the sense
resistor and via a 10k resistor to FB. A zener can be placed
from VOUT to the FB pin allowing an over voltage event to
pull up on FB with a low breakdown current (and thus low
power zener) as a result of the 10k resistor.
VIN = 2.7V TO 5.5V
1
C1
1µF
80
C2
0.1µF
70
0
5
10
15
20
ILED (mA)
25
D0
2
2.2µH
M1
30
FIGURE 8. EFFICIENCY IMPROVEMENT WITH 9V AND 12V
INPUTS
VOUT
LX
ISL97632
FBSW
EN
FB
SDIN
GND
10BQ100
C3
4.7µF
FQT13N06L
SK011C226KAR
VIN
VIN = 4V
6 LEDs
L1 = 22µH
R1 = 4
75
L1
R1
D1
D2
6.3
D8
D9
9 LEDs Operation
For medium size LCDs that need more than 7 low power
LEDs for backlighting, such as a Portable Media Player or
Automotive Navigation Panel displays, the voltage range of
7
FIGURE 9. CONCEPTUAL 9 LEDS HIGH VOLTAGE DRIVER
FN9239.3
March 22, 2010
ISL97632
SEPIC Operation
where D is the on-time of the PWM duty cycle.
For applications where the output voltage is not always
above the input voltage, a buck or boost regulation is
needed. A SEPIC (Single Ended Primary Inductance
Converter) topology, (see Figure 10), can be considered for
such an application. A single cell Li-Ion battery operating a
cellphone backlight or flashlight is one example. The
battery voltage is between 2.5V and 4.2V depending on the
state of charge. On the other hand, the output may require
only one 3V to 4V medium power LED for illumination
because the light guard of the backlight assembly is
optimized or it is a cost efficiency trade off reason.
The convenience of SEPIC comes with some trade off in
addition to the additional L and C costs. The efficiency is
usually lowered because of the relatively large efficiency
loss through the Schottky diode if the output voltage is low.
The L2 series resistance also contributes additional loss.
Figure 11 shows the efficiency measurement of a single LED
application as the input varies between 2.7V and 4.2V.
VIN = 2.7V to 5.5V 1 L1 2
22µH
C1
1µF
VA
C3
VB
1µF
L2 C4
22µH
0.22µ
D1
VIN
C2
0.1µF
EN
LX
VOUT
VIN = 2.7V
72
VIN = 4.2V
68
1 LED
L1 = L2 = 22µH
64
C3 = 1µF
FBSW
R1 = 4.7
60
FB
SDIN
76
EFFICIENCY (%)
In fact, a SEPIC configured LED driver is flexible enough to
allow the output to be well above or below the input voltage,
unlike the previous example. Another example is when the
number of LEDs and input requirements are different from
platform to platform, a common circuit and PCB that fit all the
platforms, in some cases, may be beneficial enough that it
outweighs the disadvantage of adding additional component
cost. L1 and L2 can be a coupled inductor in one package.
Note, VB is considered the level-shifted LX node of a
standard boost regulator. The higher the input voltage, the
lower the VB voltage will be during PWM on period. The
result is that the efficiency will be lower at higher input
voltages because the SEPIC has to work harder to boost up
to the required level. This behavior is the opposite to the
standard boost regulator’s and the comparison is shown in
Figure 11.
0
GND
R1
1
5
10
ILED (mA)
15
20
FIGURE 11. EFFICIENCY MEASUREMENT OF 1 LED SEPIC
DRIVER
FIGURE 10. SEPIC LED DRIVER
The simplest way to understand SEPIC topology is to think
about it as a boost regulator in which the input volute is level
shifted downward at the same magnitude and the lowest
reference level starts at -VIN rather than 0V.
The SEPIC works as follows: Assume the circuit in Figure 10
operates normally when the ISL97632 internal switch opens,
and it is in the PWM ‘OFF’ state. After a short duration where
few LC time constants elapsed, the circuit is considered in
the steady-state within the PWM ‘OFF’ period that L1 and L2
are shorted. VB is therefore shorted to the ground and C3 is
charged to VIN with VA = VIN. When the ISL97632 internal
switch closes, and the circuit is in the PWM on state, VA is
now pulled to ground. Since the voltage in C3 cannot be
changed instantaneously, VB is shifted downward and
becomes -VIN. The next cycle, when the ISL97632 switch
opens, VB boosts up to the targeted output like the standard
boost regulator operation, except the lowest reference point
is at -VIN. The output is approximated as shown in
Equation 5:
D
V OUT = V IN -----------------1 – D
PCB Layout Considerations
The layout is very important for the converter to function
properly. RSET must be located as close as possible to the FB
and GND pins. Longer traces to the LEDs are acceptable.
Similarly, the supply decoupling capacitor and the output filter
capacitor should be as close as possible to the VIN and
VOUTpins.
The heat of the IC is mainly dissipated through the thermal
pad of the package. Maximize the copper area connected to
this pad if possible. In addition, a solid ground plane is always
helpful for the EMI performance.
(EQ. 5)
8
FN9239.3
March 22, 2010
ISL97632
Thin Dual Flat No-Lead Plastic Package (TDFN)
L8.2x3A
2X
0.15 C A
A
D
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
2X
MILLIMETERS
0.15 C B
SYMBOL
E
MIN
A
0.70
A1
-
6
A3
INDEX
AREA
b
TOP VIEW
D2
0.20
0.10
SIDE VIEW
C
SEATING
PLANE
D2
(DATUM B)
0.08 C
A3
7
0.75
0.80
-
-
0.05
-
0.25
0.32
1.50
1.65
1.75
1
7,8
3.00 BSC
-
8
1.65
e
1.80
1.90
7,8
0.50 BSC
-
k
0.20
-
-
-
L
0.30
0.40
0.50
8
N
8
Nd
4
D2/2
6
INDEX
AREA
5,8
C
E2
A
NOTES
2.00 BSC
E
//
MAX
0.20 REF
D
B
NOMINAL
2
3
Rev. 0 6/04
2
NX k
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
(DATUM A)
E2
4. All dimensions are in millimeters. Angles are in degrees.
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
NX L
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
N N-1
NX b
e
8
5
0.10
(Nd-1)Xe
REF.
M C A B
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
CL
(A1)
NX (b)
L
5
SECTION "C-C"
C C
TERMINAL TIP
e
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
FN9239.3
March 22, 2010
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