DATASHEET

DATASHEET
6-Channel LED Driver with Ultra Low Dimming
Capability
ISL97672B
Features
The ISL97672B is an integrated 6-channel power LED driver for
LCD backlight applications. The ISL97672B is capable of
driving LEDs with an input from 4.5V to 26.5V and a maximum
output up to 45V.
• 6 x 50mA channels
The ISL97672B employs an adaptive boost switching
architecture that allows direct PWM dimming with dimming
duty cycle as low as 0.007% at 200Hz or 0.8% at 20kHz. PWM
Dimming frequency can be as high as 30kHz.
The ISL97672B employs the dynamic headroom control that
monitors the highest LED forward voltage string for output
regulation to minimize headroom voltage and power loss in a
typical multi-string operation. Typical current matching
between channels is ±0.7%.
The ISL97672B incorporates extensive protection functions
that flag whenever a fault occurs. The protections include
string-open and short-circuit detections, OVP, OTP and an
optional output short-circuit protection with external fault
disconnect switch.
The ISL97672B is offered in a compact 20 Ld QFN 3x4
package and can operate in ambient temperatures of -40°C to
+85°C.
• 4.5V to 26.5V input
• 45V output maximum
• Adaptive boost switching architecture
• Direct PWM dimming with dimming linearity of
0.007%~100% at 200Hz or 0.8%~100% <20kHz
• Adjustable 200kHz to 1.4MHz switching frequency
• Dynamic headroom control
• Fault protections with latched flag indication
- String open/short-circuit
- Overvoltage Protection (OVP)
- Over-Temperature Protection (OTP)
- Optional output short-circuit fault protection switch
• Current matching ±0.7%
• 20 Ld 3x4 QFN package
Applications
• Notebook displays LED backlighting
• LCD monitor LED backlighting
• Multi-function printer scanning light source
VOUT = 45V*, 6 x 50mA
VIN = 4.5V~26.5V
Q1 OPTIONAL
ISL97672B
1 FAULT
LX 20
2 VIN
4 VDC
6 /FLAG
OVP 16
1.2
PGND 19
1.0
18 COMP
0.8
ILED (mA)
CH0 10
CH1 11
CH2 12
3 EN
CH3 13
5 PWM
CH4 14
17 RSET
ILED = 20mA
FPWM = 20kHz
* VIN ≥ 12V
9 AGND
0.4
0.2
CH5 15
8 FSW
0.6
0.0
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2
PWM DIMMING DUTY CYCLE (%)
FIGURE 1. TYPICAL APPLICATION DIAGRAM
May 2, 2016
FN7995.2
1
FIGURE 2. DIMMING LINEARITY AT 20kHz
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2013, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL97672B
Block Diagram
45V*, 6x50mA
VIN: 4.5V~26.5V
10µH/1.5A
FAULT
VIN
INTERNAL
BIAS
EN
REG
4.7µF/50V
LX
O/P SHORT
OSC AND
RAMP COMP
SUM = 0
LOGIC
IMAX
/FLAG
OVP
OVP
FAULT
FLAG
VDC
FET
DRIVERS
ILIMIT
PGND
FAULT
FLAG
GM
AMP
COMP
+
-
ISET
8-BIT
DAC
DYNAMIC
HEADROOM
CONTROL
HIGHEST VF
STRING
DETECT
+
-
REF
GEN
OPEN CKT, SHORT CKT
DETECTION
1
CH1
CH2
CH3
CH4
CH5
2
CH6
3
4
* VIN ≥ 12V
5
REF_OVP REF_VSC
6
+
-
PWM
DIMMING CONTROLLER
TEMP
SENSOR
ISL97672B
FIGURE 3. ISL97672B BLOCK DIAGRAM
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
ISL97672BIRZ
672B
PACKAGE
(RoHS Compliant)
20 Ld 3x4 QFN
PKG.
DWG. #
L20.3x4
NOTES:
1. Add “-T” suffix for 6k unit tape and reel option. Please refer to Tech Brief TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL97672B. For more information on MSL, please see Tech Brief TB363.
Submit Document Feedback
2
FN7995.2
May 2, 2016
ISL97672B
Pin Configuration
Pin Descriptions
COMP
RSET
20
PGND
LX
ISL97672B
(20 LD 3X4 QFN)
TOP VIEW
19
18
17
FAULT
1
16
OVP
VIN
2
15
CH5
EN
3
14
CH4
PAD
PWM
5
12
CH2
/FLAG
6
11
CH1
7
8
9
10
CH0
CH3
AGND
13
FSW
4
NC
VDC
(I = Input, O = Output, S = Supply)
PIN NAME
PIN #
TYPE
FAULT
1
O
A pull-down current output for external P-channel fault disconnect switch.
VIN
2
S
Input supply voltage for IC. Connect a 0.1µF decoupling capacitor close to this pin.
EN
3
I
IC enable pin. Pull high to enable the IC. If EN is low for longer than 30µs, the IC will be disabled.
VDC
4
S
Internal 5V regulator. Connect a 1µF decoupling capacitor on VDC.
PWM
5
I
PWM input pin for direct PWM dimming control.
/FLAG
6
O
/FLAG is latched low under any fault condition and resets after input power is recycled or part is re-enabled. This pin
is an open drain that needs pull-up.
NC
7
I
No connect.
FSW
8
I
Boost switching frequency set pin. Connect a resistor between this pin and ground to set up desired boost switching
frequency. See “Switching Frequency” on page 9 for resistance calculation.
AGND
9
S
Analog Ground for precision circuits.
CH0, CH1
CH2, CH3
CH4, CH5
10, 11,
12, 13,
14, 15
I
Current source and channel monitoring input for Channel 0, 1, 2 3, 4, 5. The unused channel inputs should be
connected to AGND.
OVP
16
I
Overvoltage protection input. See “OVP and VOUT” on page 10.
RSET
17
I
LED DC current set pin. Connect a resistor between this pin and ground to set up maximum LED DC current. See
“Maximum DC Current Setting” for resistance calculation.
COMP
18
O
Boost compensation pin. Connect a RC compensation network between this pin and GND to optimize boost stability
and transient response.
PGND
19
S
Power ground.
LX
20
O
Boost converter switching node
PAD
-
S
Electrically should be connected to PGND and AGND. For example, use the top plane as PGND and the bottom plane
as AGND with vias on the PAD to allow heat dissipation and minimum noise coupling from PGND to AGND operation.
Submit Document Feedback
DESCRIPTION
3
FN7995.2
May 2, 2016
ISL97672B
Absolute Maximum Ratings
(TA = +25°C)
VIN, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V
FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN - 8.5V to VIN + 0.3V
VDC, COMP, RSET, PWM, OVP, FSW . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5V
CH0 - CH5, LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V
PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
NOTE: Voltage ratings are with respect to AGND pin.
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 3kV
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . . 1kV
Latch-Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
20 Ld QFN Package (Notes 4, 5, 7). . . . . . .
40
4.5
Thermal Characterization (Typical)
PSIJT (°C/W)
1
20 Ld QFN Package (Note 6) . . . . . . . . . . . . . . . . . . . . .
Maximum Continuous Junction Temperature . . . . . . . . . . . . . . . . .+125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. PSIJT is the junction-to-top thermal resistance. If the package top temperature can be measured, with this rating then the die junction temperature
can be estimated more accurately than the JA and JC thermal resistance ratings.
7. Refer to JESD51-7 high effective thermal conductivity board layout for proper via and plane designs.
Electrical Specifications All specifications are tested at TA = +25°C, VIN = 12V, EN = 5V, RSET = 20.1kΩ, unless otherwise noted. Boldface
limits apply across the operating junction temperature range, -40°C to +85°C.
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
26.5
V
GENERAL
VIN (Note 10)
IVIN
IVIN_STBY
VOUT
VIN Supply Voltage
TC = <+60°C
TA = +25°C
VIN Current
EN = 5V
VIN Shutdown Current
TA = +25°C
5
µA
Output Voltage
4.5V < VIN ≤26V,
fSW = 600kHz
45
V
8.55V < VIN ≤26V,
fSW = 1.2MHz
45
V
4.5V < VIN ≤8.55V,
fSW = 1.2MHz
VIN/0.19
V
VUVLO
Undervoltage Lockout Threshold
VUVLO_HYS
Undervoltage Lockout Hysteresis
4.5
5
2.1
mA
2.6
200
V
mV
ENABLE AND PWM GENERATOR
VIL
Guaranteed Range for PWM Input Low Voltage
0.8
V
VIH
Guaranteed Range for PWM Input High Voltage
1.5
VDD
V
PWM Input Frequency Range
200
30,000
Hz
Minimum On Time
250
350
ns
FPWM
tON
Submit Document Feedback
4
FN7995.2
May 2, 2016
ISL97672B
Electrical Specifications All specifications are tested at TA = +25°C, VIN = 12V, EN = 5V, RSET = 20.1kΩ, unless otherwise noted. Boldface
limits apply across the operating junction temperature range, -40°C to +85°C.
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
4.55
4.8
5
V
5
µA
200
mV
REGULATOR
VDC
LDO Output Voltage
VIN > 6V
Standby Current
EN = 0V
VLDO
VDC LDO Droop Voltage
VIN > 5.5V, 20mA
ENLow
Guaranteed Range for EN Input Low Voltage
ENHi
Guaranteed Range for EN Input High Voltage
IVDC_STBY
tENLow
20
0.5
1.8
EN Low Time Before Shutdown
V
V
30
us
BOOST
SWILimit
Boost FET Current Limit
rDS(ON)
Internal Boost Switch ON-Resistance
TA = +25°C
Boost Soft-Start Time
100% LED Duty Cycle
7
ms
Peak Efficiency
VIN = 12V, 72 LEDs, 20mA
each, L = 10µH with DCR
101mΩTA = +25°C
92.9
%
VIN = 12V, 60 LEDs, 20mA
each, L = 10µH with DCR
101mΩTA = +25°C
90.8
%
0.1
%
SS
Eff_peak
IOUT/VIN
1.5
Line Regulation
Dmax
Boost Maximum Duty Cycle
Dmin
Boost Minimum Duty Cycle
fSW = 600kHz
90
fSW = 1.2MHz
81
2.0
2.7
A
235
300
mΩ
%
%
fSW = 600kHz
9.5
%
fSW = 1.2MHz
17
%
fS
Minimum Switching Frequency
RFSW = 200kΩ
175
200
235
kHz
fS
Maximum Switching Frequency
RFSW = 33kΩ
1.312
1.50
1.69
MHz
LX Leakage Current
LX = 45V, EN = 0
10
µA
Channel-to-Channel Current Matching
RSET = 20.5kΩ
(IOUT = 20mA)
±1.0
%
+1.5
%
ILX_leakage
CURRENT SOURCES
IMATCH
IACC
Current Accuracy
-1.5
Vheadroom20
Dominant Channel Current Source Headroom
at IIN Pin measured with ILED = 20mA
ILED = 20mA
TA = +25°C
Vheadroom33
Dominant Channel Current Source Headroom
at IIN Pin measured with ILED = 33mA
ILED = 33mA
TA = +25°C
Voltage at RSET Pin
RSET = 20.5kΩ
Maximum LED Current per Channel
VIN = 12V, VOUT = 45V,
fSW = 1.2MHz, TA = +25°C
Channel Short-Circuit Threshold
PWM Dimming = 100%
VRSET
ILEDmax
±0.7
500
(Note 9)
mV
560
(Note 9)
710
860
(Note 9)
mV
1.2
1.22
1.24
V
50
mA
8.2
V
FAULT DETECTION
VSC
7.5
Temp_shtdwn
Over-Temperature Shutdown Threshold
150
°C
Temp_Hyst
Over-Temperature Shutdown Hysteresis
23
°C
VOVPlo
Overvoltage Limit on OVP Pin
Submit Document Feedback
5
1.199
1.24
V
FN7995.2
May 2, 2016
ISL97672B
Electrical Specifications All specifications are tested at TA = +25°C, VIN = 12V, EN = 5V, RSET = 20.1kΩ, unless otherwise noted. Boldface
limits apply across the operating junction temperature range, -40°C to +85°C.
PARAMETER
FLAG_ON
DESCRIPTION
MIN
(Note 8)
TEST CONDITIONS
TYP
MAX
(Note 8)
UNIT
0.04
0.12
V
Flag Voltage when Fault Occurs
When Fault Occurs,
IPULLUP = 4mA
IFAULT
Fault Pull-Down Current
VIN = 12V
12
21
30
µA
VFAULT
Fault Clamp Voltage with Respect to VIN
VIN = 12, VIN - VFAULT
6
7
8.3
V
1.2
V
5
mA
FAULT PIN
LXstart_thres
ILXStartup
LX Start-Up Threshold
0.9
LX Start-Up Current
VDC = 5.0V
1
3.5
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. Compliance to limits is assured by characterization and design.
10. At maximum VIN of 26.5V, minimum VOUT is 28V. Minimum VOUT can be lower at lower VIN.
100
100
90
90
80
80
70
24VIN
12VIN
60
EFFICIENCY (%)
EFFICIENCY (%)
Typical Performance Curves
5VIN
50
40
30
70
40
30
10
10
5
10
15
20
0
25
5VIN
50
20
0
24VIN
12VIN
60
20
0
6P10S_30mA/CHANNEL
0
5
10
15
20
25
30
35
ILED(mA)
ILED(mA)
FIGURE 4. EFFICIENCY vs UP TO 20mA LED CURRENT (100% LED
DUTY CYCLE) vs VIN
FIGURE 5. EFFICIENCY vs UP TO 30mA LED CURRENT (100% LED
DUTY CYCLE) vs VIN
100
100
90
80
70
580k
60
1.2MHz
EFFICIENCY (%)
EFFICIENCY (%)
80
50
40
30
20
60
1.2MHz
580k
40
20
10
0
0
5
10
15
20
25
30
VIN
FIGURE 6. EFFICIENCY vs VIN vs SWITCHING FREQUENCY AT 20mA
(100% LED DUTY CYCLE)
Submit Document Feedback
6
0
0
5
10
15
20
25
30
VIN
FIGURE 7. EFFICIENCY vs VIN vs SWITCHING FREQUENCY AT 30mA
(100% LED DUTY CYCLE)
FN7995.2
May 2, 2016
ISL97672B
Typical Performance Curves
(Continued)
100
0.40
CURRENT MATCHING (%)
90
EFFICIENCY (%)
80
+25°C
70
60
-40°C
+85°C
0°C
50
40
30
20
10
0
0
5
10
15
20
25
0.30
0.20
0.10
0.00
12 VIN
-0.20
21 VIN
-0.30
-0.40
30
4.5 VIN
-0.10
0
1
2
3
4
5
6
7
CHANNEL
VIN
FIGURE 8. EFFICIENCY vs VIN vs TEMPERATURE AT 20mA (100%
LED DUTY CYCLE)
FIGURE 9. CHANNEL-TO-CHANNEL CURRENT MATCHING
1.2
0.60
-40°C
+25°C
1.0
CURRENT
VHEADROOM (V)
0.55
0.8
4.5 VIN
0.6
12 VIN
0.4
0.50
0°C
0.45
0.2
0
0
1
2
3
DC
4
5
6
0.40
FIGURE 10. CURRENT LINEARITY vs LOW LEVEL PWM DIMMING
DUTY CYCLE vs VIN
0
5
10
15
VIN (V)
20
25
30
FIGURE 11. VHEADROOM vs VIN AT 20mA
V_OUT
V_OUT
VO = 50mV/DIV
2.00µs/DIV
V_EN
V_EN
V_LX
V_LX
I_INDUCTOR
I_INDUCTOR
FIGURE 12. VOUT RIPPLE VOLTAGE, VIN = 12V, 6P12S AT
20mA/CHANNEL
Submit Document Feedback
7
FIGURE 13. START UP WAVEFORMS AT VIN = 6V FOR 6P12S AT
20mA/CHANNEL
FN7995.2
May 2, 2016
ISL97672B
Typical Performance Curves
(Continued)
V_OUT
V_OUT
6P12S, 20mA/CH
VIN = 10V/DIV
V_EN
V_EN
10.0ms/DIV
V_LX
V_LX
ILED = 20mA/DIV
I_VIN = 1A/DIV
I_INDUCTOR
I_INDUCTOR
FIGURE 14. STARTUP WAVEFORMS AT VIN = 12V FOR 6P12S AT
20mA/CHANNEL
6P12S, 20mA/CH
FIGURE 15. LINE REGULATION WITH VIN CHANGE FROM 6V TO 26V,
6P12S AT 20mA/CHANNEL
6P12S, 20mA/CH
VIN = 10V/DIV
VO = 1V/DIV
10.0ms/DIV
I_VIN = 1A/DIV
10.0ms/DIV
ILED = 20mA/DIV
ILED = 20mA/DIV
FIGURE 16. LINE REGULATION WITH VIN CHANGE FROM 26V TO 6V
FOR 6P12S AT 20mA/CHANNEL
FIGURE 17. BOOST OUTPUT VOLTAGE WITH BRIGHTNESS CHANGE
FROM 0% TO 100% , VIN = 12V, 6P12S AT
20mA/CHANNEL
LX = 20V/DIV
6P12S, 20mA/CH
100µs/DIV
VO = 1V/DIV
10.0ms/DIV
ILED =20mA/DIV
EN
ILED = 20mA/DIV
FIGURE 18. BOOST OUTPUT VOLTAGE WITH BRIGHTNESS CHANGE
FROM 100% TO 0% , VIN = 12V, 6P12S AT
20mA/CHANNEL
Submit Document Feedback
8
FIGURE 19. ISL97672B SHUTS DOWN AND STOPS SWITCHING
~30µs AFTER EN GOES LOW
FN7995.2
May 2, 2016
ISL97672B
Theory of Operation
PWM Boost Converter
The current mode PWM boost converter produces the minimal
voltage needed to enable the LED stack with the highest forward
voltage drop to run at the programmed current. The ISL97672B
employs current mode control boost architecture that has a fast
current sense loop and a slow voltage feedback loop. Such
architecture achieves a fast transient response that is essential
for notebook backlight applications in which drained batteries
can be instantly changed to an AC/DC adapter without
noticeable visual disturbance. The number of LEDs that can be
driven by ISL97672B depends on the type of LED chosen in the
application. The ISL97672B is capable of boosting up to 45V and
typically driving 13 LEDs in series for each of the 6 channels,
enabling a total of 78 pieces of the 3.2V/20mA type of LEDs.
effectively the lowest voltage from any of the CH0 through CH5
pins. When this lowest channel voltage is lower than the
short-circuit threshold, VSC, this voltage is used as the feedback
signal for the boost regulator. The boost adjusts the output to the
correct level such that the lowest channel pin is at the target
headroom voltage. Since all LED stacks are connected to the
same output voltage, the other channel pins will have a higher
voltage, however, the regulated current source circuit on each
channel ensures that each channel has the same current. The
output voltage regulates cycle-by-cycle, and it is always
referenced to the highest forward voltage string in the
architecture.
Dimming Controls
The ISL97672B allows two ways of controlling the LED current,
and therefore, the brightness. They are:
1. DC current adjustment
Enable
The device is enabled if the Enable pin voltage is high. If EN is
pulled low for longer than 30µs, the device will be shut down. The
Enable pin should not float; a 10k or higher pull-down resistor
should be connected between EN and GND.
Current Matching and Current Accuracy
Each channel of the LED current is regulated by the current
source circuit, as shown in Figure 20.
The LED DC current is set by translating the RSET current to the
output, with a scaling factor of 410.5/RSET. The source terminals
of the current source MOSFETs are designed to run at 500mV to
optimize power loss versus accuracy requirements. The source of
errors of the channel-to-channel current matching come from the
op amp’s offset, internal layout, reference and current source
resistors. These parameters are optimized for current matching
and absolute current accuracy. The absolute accuracy is also
affected by the external RSET. A 1% tolerance resistor should be
used.
2. PWM chopping of the LED current defined in Step 1.
MAXIMUM DC CURRENT SETTING
The LED DC current of each channel can be calculated as shown
in Equation 1:
410.5
I LEDmax = --------------R SET
(EQ. 1)
For example, if the maximum required LED current
(ILED(max)) is 20mA, rearranging Equation 1 yields Equation 2:
R SET = 410.5  0.02 = 20.52k
(EQ. 2)
PWM CURRENT CONTROL
The ISL97672B employs direct PWM dimming such that the output
PWM dimming follows directly with the input PWM signal without
modifying the input frequency. The average LED current of each
channel can be calculated as shown in Equation 3:
I LED  avg  = I LED  PWM
(EQ. 3)
Switching Frequency
The boost switching frequency can be adjusted by connecting a
resistor between the FSW pin and GND. The calculation of the
resistance is shown in Equation 4:
10
 5 10 
f SW = ----------------------R FSW
+
-
REF
(EQ. 4)
Where fSW is the desirable boost switching frequency, and RFSW
is the setting resistor
+
-
5V Low Dropout Regulator
RSET
+
PWM DIMMING
FIGURE 20. SIMPLIFIED CURRENT SOURCE CIRCUIT
There is an internal 5V Low Dropout (LDO) regulator to develop
the necessary low-voltage supply, which is used by the chip’s
internal control circuitry. VDC is the output of this LDO regulator,
which requires a bypass capacitor of 1µF or more for the
regulation. The VDC pin can be used as a coarse reference as
long as it is sourcing only a few milliamps.
Dynamic Headroom Control
The ISL97672B features a proprietary Dynamic Headroom
Control circuit that detects the highest forward voltage string or
Submit Document Feedback
9
FN7995.2
May 2, 2016
ISL97672B
IC Protection Features and Fault
Management
The ISL97672B has several protection and fault management
features that improve system reliability. The following sections
describe them in more detail.
INRUSH CONTROL AND SOFT-START
The ISL97672B has separate, built-in, independent inrush control
and soft-start functions. The inrush control function is built
around an external short-circuit protection P-channel FET in
series with VIN. At start-up, the fault protection FET is turned on
slowly due to a 21µA pull-down current output from the FAULT
pin. This discharges the fault FET's gate-to-source capacitance,
turning on the FET in a controlled fashion. As this happens, the
output capacitor is charged slowly through the low-current FET
before it becomes fully enhanced. This results in a low inrush
current. This current can be further reduced by adding a
capacitor (in the 1nF to 5nF range) across the gate source
terminals of the FET.
Once the chip detects that the fault protection FET is turned on
fully, it assumes that inrush is complete. At this point, the boost
regulator begins to switch, and the current in the inductor ramps
up. The current in the boost power switch is monitored, and
switching is terminated in any cycle in which the current exceeds
the current limit. The ISL97672B includes a soft-start feature in
which this current limit starts at a low value (275mA). This value
is stepped up to the final 2.2A current limit in seven additional
steps of 275mA each. These steps happen over at least 8ms and
are extended at low LED PWM frequencies if the LED duty cycle is
low. This extension allows the output capacitor to charge to the
required value at a low current limit and prevents high input
current for systems that have only a low to medium output
current requirement.
For systems with no master fault protection FET, the inrush current
flows towards COUT when VIN is applied. The inrush current is
determined by the ramp rate of VIN and the values of COUT and L.
FAULT PROTECTION AND MONITORING
The ISL97672B features extensive protection functions to cover
all perceivable failure conditions. The /FLAG pin is a latched
open-drain output that monitors string open, LED short, VOUT
short, and overvoltage and over-temperature conditions. This pin
resets only when input power is recycled or the part is re-enabled.
The failure mode of an LED can be either an open circuit or a
short. The behavior of an open-circuited LED can additionally
take the form of either infinite resistance or, for some LEDs, a
Zener diode, which is integrated into the device in parallel with
the now-opened LED.
For basic LEDs (which do not have built-in Zener diodes), an
open-circuit failure of an LED results only in the loss of one
channel of LEDs, without affecting other channels. Similarly, a
short-circuit condition on a channel that results in that channel
being turned off does not affect other channels unless a similar
fault is occurring.
Due to the lag in boost response to any load change at its output,
certain transient events (such as LED current steps or significant
step changes in LED duty cycle) can transiently look like LED
Submit Document Feedback
10
fault modes. The ISL97672B uses feedback from the LEDs to
determine when it is in a stable operating region and prevents
apparent faults during these transient events from allowing any
of the LED stacks to fault out. See Table 1 on page 12 for details.
A fault condition that results in an input current that exceeds the
device’s electrical limits will result in a shutdown of all output
channels.
SHORT-CIRCUIT PROTECTION (SCP)
The short-circuit detection circuit monitors the voltage on each
channel and disables faulty channels that are above
approximately 7.5V (this action is described in Table 1).
OPEN-CIRCUIT PROTECTION (OCP)
When one of the LEDs becomes an open circuit, it can behave as
either an infinite resistance or as a gradually increasing finite
resistance. The ISL97672B monitors the current in each channel
such that any string that reaches the intended output current is
considered “good.” Should the current subsequently fall below the
target, the channel is considered an “open circuit.” Furthermore,
should the boost output of the ISL97672B reach the OVP limit, or
should the lower over-temperature threshold be reached, all
channels that are not good are immediately considered to be open
circuit. Detection of an open circuit channel results in a time-out
before the affected channel is disabled. This time-out is sped up
when the device is above the lower over-temperature threshold, in
an attempt to prevent the upper over-temperature trip point from
being reached.
Some users employ special types of LEDs that have a Zener
diode structure in parallel with the LED. This configuration
provides ESD enhancement and enables open-circuit operation.
When this type of LED is open circuited, the effect is as if the LED
forward voltage has increased but the lighting level has not
increased. Any affected string will not be disabled, unless the
failure results in the boost OVP limit being reached, which allows
all other LEDs in the string to remain functional. In this case, care
should be taken that the boost OVP limit and SCP limit are set
properly, to ensure that multiple failures on one string do not
cause all other good channels to fault out. This condition could
arise if the increased forward voltage of the faulty channel
makes all other channels look as if they have LED shorts. See
Table 1 for details of responses to fault conditions.
OVP AND VOUT
The Overvoltage Protection (OVP) pin has a function of setting the
overvoltage trip level as well as limiting the VOUT regulation
range.
The ISL97672B OVP threshold is set by RUPPER and RLOWER such
that:
 R U PP E R + R L O WE R 
V OUT_OVP = 1.22Vx -------------------------------------------------------R L O WE R
(EQ. 5)
and VOUT can only regulate between 60% and 100% of the
VOUT_OVP such that:
Allowable VOUT = 60% to 100% of VOUT_OVP
if, for example, 10 LEDs are used with the worst-case VOUT of
35V.
FN7995.2
May 2, 2016
ISL97672B
If R1 and R2 are chosen such that the OVP level is set at 40V,
then VOUT is allowed to operate between 24V and 40V. If the VOUT
requirement is changed to an application of six LEDs of 21V, then
the OVP level must be reduced. Users should follow the
VOUT = (60% ~100%) OVP level requirement; otherwise, the
headroom control will be disturbed such that the channel voltage
can be much higher than expected. This can sometimes prevent
the driver from operating properly.
Additionally, the ISL97672B monitors the voltage at the LX and
OVP pins. At start-up, the LX pins inject a fixed current into the
output capacitor. The device does not start unless the voltage at
LX exceeds 1.2V. The OVP pin is also monitored such that if it
rises above and subsequently falls below 20% of the target OVP
level, the input protection FET is also switched off.
OVER-TEMPERATURE PROTECTION (OTP)
The ISL97672B includes two over-temperature thresholds. The
lower threshold is set to +130°C. When this threshold is reached,
any channel that is outputting current at a level significantly below
the regulation target is treated as an “open circuit” and is disabled
after a time-out period. This time-out period is 800µs when it is
above the lower threshold. The lower threshold isolates and disables
bad channels before they cause enough power dissipation (as a
result of other channels having large voltages across them) to hit the
upper temperature threshold.
The resistances should be large, to minimize power loss. For
example, a 1MΩ RUPPER and a 30kΩ RLOWER sets OVP to 41.9V.
Large OVP resistors also allow COUT to discharge slowly during the
PWM Off time. Parallel capacitors should also be placed across
the OVP resistors such that RUPPER/RLOWER = CLOWER/CUPPER.
Using a CUPPER value of 30pF is recommended. These capacitors
reduce the AC impedance of the OVP node, which is important
when using high-value resistors. For example, if RUPPER/RLOWER
= 33/1, then CUPPER/CLOWER = 1/33 with CUPPER = 100pF and
CLOWER = 3.3nF.
The upper threshold is set to +150°C. Each time this threshold is
reached, the boost stops switching, and the output current
sources switch off. Once the device has cooled to approximately
+100°C, the device restarts, with the DC LED current level
reduced to 75% of the initial setting. If dissipation persists,
subsequent hitting of the limit causes identical behavior, with the
current reduced in steps to 50% and finally 25%. Unless disabled
via the EN pin, the device stays in an active state throughout.
UNDERVOLTAGE LOCK-OUT
If the input voltage falls below the UVLO level, the device stops
switching and is reset. Operation restarts only when VIN returns
to the normal operating range.
INPUT OVERCURRENT PROTECTION
During a normal switching operation, the current through the
internal boost power FET is monitored. If the current exceeds the
current limit, the internal switch is turned off. Monitoring occurs
on a cycle-by-cycle basis in a self-protecting way.
For complete details of fault protection conditions, see Figure 21
and Table 1.
LX
VIN
/FLAG
FAULT
DRIVER
VOUT
LX
O/P
SHORT
OVP
IMAX
ILIMIT
LOGIC
FET
DRIVER
CH0
VSC
FAULT FLAG
CH5
THRM
SHDN
REF
T2
TEMP
SENSOR
OTP
T1
FAULT
DETECT
LOGIC
VSET
Q0
PWM/OC0/SC0
PWM
GENERATOR
VSET
Q5
PWM/OC5/SC5
FIGURE 21. SIMPLIFIED FAULT PROTECTIONS
Submit Document Feedback
11
FN7995.2
May 2, 2016
ISL97672B
TABLE 1. PROTECTIONS TABLE
CASE
FAILURE MODE
DETECTION MODE
FAILED CHANNEL ACTION
GOOD CHANNEL ACTION
1
CHX short-circuit
Upper
Over-Temperature
Protection limit (OTP)
not triggered, and
VCHX < 7.5V
CHX ON and burns power.
2
CHX short-circuit
Upper OTP triggered,
but VCHX < 7.5V
All channels go off until chip cools,
Same as CHX
and then come back on with current
reduced to 76%. Subsequent OTP
triggers further reduce IOUT.
Highest VF of
remaining
channels
3
CHX short-circuit
Upper OTP not
triggered, but
CHX > 7.5V
CHX disabled after six PWM cycle
time-outs.
Remaining channels normal
Highest VF of
remaining
channels
4
CHX open circuit with Upper OTP not
infinite resistance
triggered, and
CHX < 7.5V
VOUT ramps to OVP. CHX times out
after six PWM cycles and switches
off. VOUT drops to normal level.
Remaining channels normal
Highest VF of
remaining
channels
5
CHX LED open circuit Upper OTP not
triggered, and
but has paralleled
CHX < 7.5V
Zener
CHX remains ON and has highest VF; Remaining channels ON, remaining VF of CHX
thus, VOUT increases.
channel FETs burn power
6
CHX LED open circuit Upper OTP triggered,
but CHX < 7.5V
but has paralleled
Zener
All channels go off until chip cools,
Same as CHX
and then come back on with current
reduced to 76%. Subsequent OTP
triggers further reduce IOUT.
7
CHX LED open circuit Upper OTP not
triggered, but
but has paralleled
CHX > 7.5V
Zener
CHX remains ON and has highest VF; VOUT increases, then CHX switches VF of CHX
thus, VOUT increases.
OFF after six PWM cycles. This is an
unwanted shut off and can be
prevented by setting OVP at an
appropriate level.
8
Channel-to-channel
VF too high
Lower OTP triggered,
but CHX < 7.5V
Any channel below the target current faults out after six PWM cycles.
Remaining channels are driven with normal current.
Highest VF of
remaining
channels
9
Channel-to-channel
VF too high
Upper OTP triggered,
but CHX < 7.5V
All channels go off until chip cools and then come back on with current
reduced to 75%. Subsequent OTP triggers further reduce IOUT.
Boost switches off
10
Output LED stack
voltage too high
VOUT > VOVP
Any channel that is below the target current times out after six PWM cycles, Highest VF of
and VOUT returns to normal regulation voltage required for other channels. remaining
channels
11
VOUT/LX shorted to
GND at start-up, or
VOUT shorted in
operation
LX current and timing Chip is permanently shut down 31ms after power-up if VOUT/LX is shorted to
monitored.
GND.
OVP pins monitored
for excursions below
20% of OVP threshold.
Component Selection
According to the inductor Voltage-Second Balance principle, the
change of inductor current during the switching regulator On
time is equal to the change of inductor current during the
switching regulator Off time. As shown in Equations 6 and 7,
since the voltage across an inductor is:
VL
I L = ------- xt
L
Remaining channels normal
VOUT
REGULATED BY
Highest VF of all
channels
VF of CHX
Where D is the switching duty cycle defined by the turn-on time
over the switching period. VD is a Schottky diode forward voltage
that can be neglected for approximation.
Rearranging the terms without accounting for VD gives the boost
ratio and duty cycle, respectively, as shown in Equations 8 and 9:
VO  VI = 1   1 – D 
(EQ. 8)
D =  VO – VI   VO
(EQ. 9)
(EQ. 6)
and IL at On = IL at Off, therefore:
 V I – 0   L  D  tS =  VO – VD – VI   L   1 – D   tS
Submit Document Feedback
12
(EQ. 7)
FN7995.2
May 2, 2016
ISL97672B
Input Capacitor
user must select an output capacitor with low ESR and adequate
input ripple current capability.
Switching regulators require input capacitors to deliver peak
charging current and to reduce the impedance of the input
supply. The capacitors reduce interaction between the regulator
and input supply, thus improving system stability. The high
switching frequency of the loop causes almost all ripple current
to flow into the input capacitor, which must be rated accordingly.
Note: Capacitors have a voltage coefficient that makes their
effective capacitance drop as the voltage across them increases.
CO in Equation 11 assumes the effective value of the capacitor at
a particular voltage and not the manufacturer’s stated value,
measured at 0V.
A capacitor with low internal series resistance should be chosen
to minimize heating effects and to improve system efficiency.
The X5R and X7R ceramic capacitors offer small size and a lower
value for temperature and voltage coefficient compared to other
ceramic capacitors.
The value of VCo can be reduced by increasing CO or fS, or by
using small ESR capacitors. In general, ceramic capacitors are
the best choice for output capacitors in small- to medium-sized
LCD backlight applications, due to their cost, form factor, and low
ESR.
An input capacitor of 10µF is recommended. Ensure that the
voltage rating of the input capacitor is able to handle the full
supply range.
A larger output capacitor also eases driver response during the
PWM dimming Off period, due to the longer sample and hold
effect of the output drooping. The driver does not need to boost
harder in the next On period that minimizes transient current.
Inductor
Inductor selection should be based on its maximum current (ISAT)
characteristics, power dissipation (DCR), EMI susceptibility
(shielded vs unshielded), and size. Inductor type and value
influence many key parameters, including ripple current, current
limit, efficiency, transient performance, and stability.
Inductor maximum current capability must be adequate to
handle the peak current in the worst-case condition. If an
inductor core with too low a current rating is chosen, saturation
in the core will cause the effective inductor value to fall, leading
to an increase in peak-to-average current level, poor efficiency,
and overheating in the core. The series resistance, DCR, within
the inductor causes conduction loss and heat dissipation. A
shielded inductor is usually more suitable for EMI-susceptible
applications such as LED backlighting.
The peak current can be derived from the voltage across the
inductor during the Off period, as shown in Equation 10:
IL peak =  V O  I O    85%  V I  + 1  2  V I   V O – V I    L  V O  f S  
(EQ. 10)
The value of 85% is an average term for the efficiency
approximation. The first term is the average current that is
inversely proportional to the input voltage. The second term is
the inductor current change that is inversely proportional to L and
fS. As a result, for a given switching frequency and minimum
input voltage at which the system operates, the inductor ISAT
must be chosen carefully.
The output capacitor is also needed for compensation, and in
general, 2x4.7µF/50V ceramic capacitors are suitable for
notebook display backlight applications.
Schottky Diode
A high-speed rectifier diode is necessary to prevent excessive
voltage overshoot. Schottky diodes are recommended because
of their fast recovery time, low forward voltage and reverse
leakage current, which minimize losses. The reverse voltage
rating of the selected Schottky diode must be higher than the
maximum output voltage. Also the average/peak current rating
of the Schottky diode must meet the output current and peak
inductor current requirements.
Applications
High-Current Applications
Each channel of the ISL97672B can support up to 30mA
(50mA at VIN = 12V). For applications that need higher current,
multiple channels can be grouped to achieve the desired current
(Figure 22). For example, the cathode of the last LED can be
connected to CH0 through CH2; this configuration can be treated
as a single string with 90mA current driving capability.
VOUT
Output Capacitors
The output capacitor smooths the output voltage and supplies
load current directly during the conduction phase of the power
switch. Output ripple voltage consists of discharge and charge of
the output capacitor during FET On and OFF time and the voltage
drop due to flow through the ESR of the output capacitor. The
ripple voltage can be shown in Equation 11:
V CO =  I O  C O  D  f S  +   I O  ESR 
13
CH1
CH2
(EQ. 11)
The conservation of charge principle shown in Equation 9 also
indicates that, during the boost switch Off period, the output
capacitor is charged with the inductor ripple current, minus a
relatively small output current in boost topology. As a result, the
Submit Document Feedback
CH0
FIGURE 22. GROUPING MULTIPLE CHANNELS FOR HIGH CURRENT
APPLICATIONS
FN7995.2
May 2, 2016
ISL97672B
Low-Voltage Operations
The ISL97672B VIN pin can be separately biased from the LED
power input to allow low-voltage operation. For systems that have
only a single supply, VOUT can be tied to the driver VIN pin to allow
initial start-up (Figure 23). The circuit works as follows: when the
input voltage is available and the device is not enabled, VOUT
follows VIN with a Schottky diode voltage drop. The VOUT
boot-strapped to the VIN pin allows initial start-up, once the part
is enabled. Once the driver starts up with VOUT regulating to the
target, the VIN pin voltage also increases. As long as VOUT does
not exceed 26.5V and the extra power loss on VIN is acceptable,
this configuration can be used for input voltage as low as 3.0V.
The Fault Protection FET feature cannot be used in this
configuration.
For systems that have dual supplies, the VIN pin can be biased
from 5V to 12V, while the input voltage can be as low as 2.7V
(Figure 24). In this configuration, VBIAS must be greater than or
equal to VIN to use the fault FET.
VOUT = 26.5, 6 x 50mA*
VIN = 3.0V~21V
VIN = 2.7V~26.5V
VOUT = 45V*, 6 x 50mA*
Q1 OPTIONAL
ISL97672B
VBIAS = 5V~12V
1 FAULT
LX 20
2 VIN
OVP 16
4 VDC
6 /FLAG
PGND 19
CH0 10
CH1 11
CH2 12
5 PWM
CH3 13
3 EN
CH4 14
17 RSET
CH5 15
8 FSW
9 AGND
COMP 18
* VIN > 12V
FIGURE 24. DUAL SUPPLY 2.7V OPERATION
Compensation
The ISL97672B incorporates a transconductance amplifier in its
feedback path to allow the user to optimize boost stability and
transient response. The ISL97672B uses current mode control
architecture, which has a fast current sense loop and a slow
voltage feedback loop. The fast current feedback loop does not
require any compensation, but for stable operation, the slow
voltage loop must be compensated. The compensation is a
series of Rc, Cc1 network from COMP pin to ground, with an
optional Cc2 capacitor connected between the COMP pin and
ground. The Rc sets the high-frequency integrator gain for fast
transient response, and the Cc1 sets the integrator zero to
ensure loop stability. For most applications, the component
values in Figure 25 can be used: Rc is 10kΩ and Cc1 is 3.3nF.
Depending upon the PCB layout, for stability, a Cc2 of 390pF may
be needed to create a pole to cancel the output capacitor ESR’s
zero effect.
ISL97672B
1 FAULT
2 VIN
4 VDC
6 /FLAG
LX 20
OVP 16
PGND 19
CH0 10
CH1 11
5 PWM
CH2 12
3 EN
CH3 13
17 RSET
8 FSW
9 AGND
CH4 14
CH5 15
COMP 18
* VIN > 12V
FIGURE 23. SINGLE SUPPLY 3.0V OPERATION
Rc 10k
COMP
Cc1
3.3nF
Cc2
390pF
FIGURE 25. COMPENSATION CIRCUIT
Submit Document Feedback
14
FN7995.2
May 2, 2016
ISL97672B
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to web to make sure you have the latest revision.
DATE
REVISION
CHANGE
May 2, 2016
FN7995. 2
Applied Intersil Standards throughout the document.
Updated the Pin Descriptions on page 3 by adding more information to the CH0-CH5 description and adding
PAD information.
Removed Machine Model information from datasheet.
Updated the Theta JC on page 4 from 2.5 to 4.5.
November 22, 2013
FN7995. 1
ISL97672B Description in introduction on page 1 changed.
Changed Pin description changed on page 3.
Changed MIN/MAX specs for “VOVPlo” on page 5 from 1.19/1.25 V to 1.199/1.24 V
“tENLow” on page 5 added to “Electrical Specifications” Table.
Changed VIN, SS, Temp_shtdwn, Temp_Hyst, FLAG_ON Descriptions in “Electrical Specifications” table.
Figure 19 added to page 8.
In “Enable” on page 9, added information about 30µs shut down delay time. Revised description.
8 channel changed to 6 channel in “PWM Boost Converter” on page 9.
Description of “Switching Frequency” on page 9 changed.
Description of “5V Low Dropout Regulator” on page 9 changed.
1.21 changed to 1.22 in Equation 5 on page 10.
Changed 30µA to 21µA in “InRush Control and Soft-Start” on page 10.
Description of “InRush Control and Soft-Start” on page 10.
2.45V deleted from “Undervoltage Lock-out” on page 11.
Descriptions in Table “PROTECTIONS TABLE” on page 12 changed.
Changed Equation 6 on page 12.
Changed “Input Capacitor” on page 13.
Changed “Input Capacitor” on page 13.
Added "Note" in “Output Capacitors” on page 13; combined "Output Ripple" session with “Output Capacitors”
section.
Description of “Schottky Diode” on page 13 changed.
Compensation component values changed in “Compensation” on page 14 to match Figure 25.
Description of “Compensation” on page 14 changed.
Figures 13, 14 updated.
Test condition “Boldface limits apply over the operating junction temperature range, -40°C to +85°C” added
for Electrical Specifications table on page 4.
Note 9 added for Vheadroom20 in Electrical Specification table on page 5.
Vheadroom33 added in Electrical Specification table on page 5.
Flag_On TYP value changed in Electrical Specification table on page 6 from 0.4V to 0.04V and added MAX value
0.12V.
On page 9, Equations 1, 2 changed from 401.8 to 410.5
“High-Current Applications” on page 13: (50mA @ VIN = 12V) was added in first sentence.
Figure 25 added on page 14.
June 13, 2012
FN7995.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Submit Document Feedback
15
FN7995.2
May 2, 2016
ISL97672B
Package Outline Drawing
L20.3x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/10
3.00
0.10 M C A B
0.05 M C
A
B
4
20X 0.25
16X 0.50
+0.05
-0.07
17
A
16
6
PIN 1
INDEX AREA
6
PIN 1 INDEX AREA
(C 0.40)
20
1
4.00
2.65
11
+0.10
-0.15
6
0.15 (4X)
A
10
7
VIEW "A-A"
1.65
TOP VIEW
+0.10
-0.15
20x 0.40±0.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0.9± 0.10
C
SEATING PLANE
0.08 C
SIDE VIEW
(16 x 0.50)
(2.65)
(3.80)
(20 x 0.25)
C
(20 x 0.60)
0.2 REF
5
0.00 MIN.
0.05 MAX.
(1.65)
(2.80)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
Submit Document Feedback
16
FN7995.2
May 2, 2016
Similar pages