DATASHEET

ESIGNS
NEW D
R
O
F
D
ARTS
MENDE LACEMENT P
M
O
C
E
D REP
N OT R
MENDE
L97672B
RECOM SL97671A or IS
I
4-Channel LED Driver with Phase Shift Control
ISL97675
Features
The ISL97675 is an LED driver that drives 4 channels of low power
LEDs from 4.5V to 26V input and up to 45V output.
• 4 x 30mA Channels
The ISL97675 compensates for non-uniformity of the forward voltage
drops in the LED strings with its 4 voltage controlled-current source
channels. Its headroom control monitors the highest LED forward
voltage string for output regulation, to minimize the voltage headroom
and power loss in the typical multi-string operation.
• 4.5V to 26V Input
The ISL97675 offers two PWM Dimming modes: The part digitizes the
incoming 100Hz to 30kHz PWM signal and provides 8-bit PWM
dimming with phase shift function. Another mode is direct PWM
mode without phase shift, where the dimming frequency follows the
input PWM signal and the minimum on time can be as short as
350ns.
• Dynamic Headroom Control
The ISL97675 features channel phase shift control to minimize the
input, output ripple characteristics and load transients as well as
spreading the light output to help eliminate or reduce the video and
audio noise interference from the backlight driver operation.
• Selectable 600kHz or 1.2MHz Switching Frequency
• 45V Output Max
• Channel Phase Shift PWM Dimming with 8-bit Resolution
• 0.007% Direct PWM dimming at 200Hz
• Current Matching of ±1.5% from 1% ~ 100% Dimming
• Protections
- String Open/Short Circuit, VOUT Short Circuit Overvoltage, and
Over-temperature Protections
- Optional Master Fault Protection
• 20 Ld QFN 4mmx4mm Package
Applications
• Netbook Displays LED Backlighting
• Notebook Displays LED Backlighting
VOUT = 45V max*
ILED = 30mA PER STRING
VIN* = 4.5V~26V
ISL97675
17 FAULT
SW 16
19 VIN
OVP 14
PGND 15
1 VDDIO
3 FSW/Phase Shift
2 EN
20 PWM
18 COMP
FB1 12
13 RFPWM/DirectPWM
4 ISET
8 AGND
9 AGND
FB2 11
FB3 7
FB4 6
* VIN ≥ 6V
FIGURE 1. TYPICAL APPLICATION CIRCUIT
September 14, 2011
FN7630.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2010, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Block Diagram
45V*/30mA PER STRING
OPTIONAL PFET
VIN* = 4.5V~26V
48 (4x12) LEDS
10µH/3A
4.7µF/50V
SW
FAULT
ISL97675
VIN
EN
4.75V BIAS
REG
2
FAULT
FET
DRV
VDDIO
OSC &
RAMP
COMP
FSW/
PHASESHIFT
FSW
O/P SHORT
FET
DRIVER
LOGIC
Σ =0
IMAX
ILIMIT
PGND
PHASE
SELECT
OPEN CKT, SHORT CKT
DETECTS
FPO
COMP
GM
AMP
8-BIT
DAC
DYNAMIC
HEADROOM
VSET
+
REF OVP
STRING
DETECT
FB4
+
-
1
REF
GEN
TEMP
SENSOR
SHUTDOWN
REF VSC
2
+
-
GND
FB1
FB2
HIGHEST VF
CONTROL
ISL97675
DETECT
ISET
OVP
OVP
PHASE
SELECT
PHASE
* VIN ≥ 6V
SHIFT &
PWM
8-BIT
DIGITIZER
FPWM/DirectPWM
FN7630.1
September 14, 2011
DIRECTPWM
DETECT
PWM
CONTROLLER
+
-
4
ISL97675
Pin Configuration
PWM
VIN
COMP
FAULT
SW
ISL97675
(20 LD QFN)
TOP VIEW
20
19
18
17
16
VDDIO
1
15 PGND
EN
2
14 OVP
FSW/PhaseShift
3
ISET
4
12 FB1
NC
5
11 FB2
ISL97675
4mmx4mm
6
7
8
9
10
FB4
FB3
AGND
AGND
NC
13 RFPWM/DirectPWM
Pin Descriptions (I = Input, O = Output, S = Supply)
PIN NAME
PIN NO.
TYPE
VDDIO
1
S
Decouple with capacitor for internally generated supply rail.
EN
2
I
Enable
FSW/PhaseShift
3
I
FSW = 0 ~ 0.25 * VDDIO, Boost Switching Frequency = 1.2MHz with phase shift.
FSW = 0.25 * VDDIO ~ 0.5 * VDDIO, Boost Switching Frequency = 1.2MHz without phase shift.
FSW = 0.5 * VDDIO ~ 0.75 * VDDIO, Boost Switching Frequency = 600KHz without phase shift.
FSW = 0.75 * VDDIO ~ VDDIO, Boost Switching Frequency = 600KHz with phase shift.
ISET
4
I
Resistor connection for setting LED current, (see Equation 3 for calculating the ILEDpeak).
NC
5, 10
I
No Connect.
FB4
6
I
Input 4 to current source, FB, and monitoring.
FB3
7
I
Input 3 to current source, FB, and monitoring.
AGND
8, 9
S
Analog Ground for precision circuits.
FB2
11
I
Input 2 to current source, FB, and monitoring.
FB1
12
I
Input 1 to current source, FB, and monitoring.
RFPWM/DirectPWM
13
I
External PWM dimming with frequency modulation or Direct PWM dimming without frequency
modulation.
When this pin is not biased and a resistor is connected to ground, the dimming frequency will be
set by the Setting Resistor.
When this pin is floating, the part enters Direct PWM mode such that the dimming follows the
input PWM signal without frequency modulation.
OVP
14
I
Overvoltage protection input.
PGND
15
S
Power ground (LX Power return).
SW
16
O
Input to boost switch.
FAULT
17
O
Gate drive signal for external fault MOSFET. This pin should be left floating when fault MOSFET is
omitted in the application.
COMP
18
I
External compensation pin.
3
DESCRIPTION
FN7630.1
September 14, 2011
ISL97675
Pin Descriptions (I = Input, O = Output, S = Supply) (Continued)
PIN NAME
PIN NO.
TYPE
DESCRIPTION
VIN
19
S
LED driver supply voltage.
PWM
20
I
PWM brightness control pin.
EP
21
S
Connect Exposed Pad (EP) to junction of AGND and PGND with adequate Vias to form a star
ground.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL97675IRZ
PART
MARKING
976 75IRZ
TEMP RANGE
(°C)
-40 to +85
PACKAGE
(Pb-free)
20 Ld 4x4 QFN
PKG.
DWG. #
L20.4x4C
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL97675. For more information on MSL please see techbrief TB363.
4
FN7630.1
September 14, 2011
ISL97675
Table of Contents
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PWM Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Current Matching and Current Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Dynamic Headroom Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Dimming Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Maximum DC Current Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PWM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Phase Shift Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PWM Dimming Frequency Adjustment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Direct PWM Dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Inrush Control and Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Fault Protection and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Short Circuit Protection (SCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Open Circuit Protection (OCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Overvoltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Master Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Over-Temperature Protection (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Components Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Channel Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Schottky Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
High Current Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
FN7630.1
September 14, 2011
ISL97675
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V
FAULT, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to min(28, VIN + 0.3)V
FSW/PhaseShift, RFPWM/DirectPWM, OVP . . . . . . . . . . . . . -0.3V to 5.5V
VDDIO, PWM, COMP. . . . . . . . . . . . . . . . . . . . . -0.3V to min(5.5, VIN + 0.3)V
ISET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to min(VDDIO + 0.3, 5.5)V
FB1, FB2, FB3, FB4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V
SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 46V
PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Above voltage ratings are all with respect to AGND pin
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 300V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
20 Ld QFN Package (Notes 4, 5, 7) . . . . . .
39
2.5
Thermal Characterization (Typical)
PSIJT (°C/W)
20 Ld QFN Package (Note 6) . . . . . . . . . . . . . . . . . . . . .
3
Maximum Continuous Junction Temperature . . . . . . . . . . . . . . . . .+125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. PSIJT is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this rating then the die
junction temperature can be estimated more accurately than the θJC and θJC thermal resistance ratings.
7. Refer to JESD51-7 high effective thermal conductivity board layout for proper via and plane designs.
Electrical Specifications All specifications below are tested at TA = +25°C; VIN = 12V, EN = 3.3V, RISET = 19.6kΩ, unless otherwise noted.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
CONDITION
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
26
V
GENERAL
VIN (Note 9)
Backlight Supply Voltage
IVIN_STBY
VIN Shutdown Current
EN = 0V
10
μA
Output Voltage
4.5V < VIN ≤ 26V,
FSW = 600kHz
45
V
6.75V < VIN ≤ 26V,
FSW = 1.2MHz
45
V
4.5V < VIN ≤ 6.75V,
FSW = 1.2MHz
VIN/0.15
V
3.3
V
VOUT
VUVLO
Undervoltage Lockout Threshold
VUVLO_HYS
Undervoltage Lockout Hysteresis
4.5
2.6
3.1
320
mV
REGULATOR
VDDIO
IVDDIO_STBY
LDO Output Voltage
VIN > 5.5V
Standby Current
EN = 0V
4.6
4.8
IVIN
Driver Input Current
100% Dimming
9
VLDO
VDDIO LDO Dropout Voltage
VIN >5.5V, IVDDIO = 20mA
30
ENLow
Guaranteed Range for EN Input Low Voltage
ENHi
Guaranteed Range for EN Input High Voltage
tENLow
5
V
10
µA
mA
200
mV
0.5
V
1.8
EN Low Time before Shut-Down
V
29.5
ms
BOOST
SWILimit
rDS(ON)
Boost FET Current Limit
Internal Boost Switch ON-Resistance
6
1.5
TA = +25°C
2.2
2.7
A
230
300
mΩ
FN7630.1
September 14, 2011
ISL97675
Electrical Specifications All specifications below are tested at TA = +25°C; VIN = 12V, EN = 3.3V, RISET = 19.6kΩ, unless otherwise noted.
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
SS
PARAMETER
CONDITION
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
Soft-Start
100% LED Duty Cycle
14
ms
Eff_peak
Peak Efficiency
VIN = 12V, 48 LEDs, 20mA
each, L = 10µH with DCR
101mΩ,
TA = +25°C
92
%
ΔIOUT/ΔVIN
Line Regulation
0.1
%
DMAX
DMIN
FSW
ISW_leakage
Boost Maximum Duty Cycle
Boost Minimum Duty Cycle
Boost Switching Frequency
FSW < 0.5 * VDDIO
91
%
FSW > 0.5 * VDDIO
82
%
FSW < 0.5 * VDDIO
8.5
%
FSW > 0.5 * VDDIO
16.5
%
FSW <0.5 * VDDIO
475
600
640
kHz
FSW >0.5 * VDDIO
950
1200
1280
kHz
10
µA
SW Leakage Current
SW = 45V, EN = 0
DC Channel-to-Channel Current Matching
RISET = 19.6kΩ,
(IOUT = 20mA)
-1.5
+1.5
%
RISET = 39.2kΩ,
(IOUT = 10mA)
-1.5
+1.5
%
RISET = 19.6kΩ,
(IOUT = 20mA)
-1.5
+1.5
%
CURRENT SOURCES
IMATCH
IACC
VHEADROOM
VISET
ILEDmax
Current Accuracy
Dominant Channel Current Source Headroom
at FBx Pin
500
Voltage at ISET Pin
Maximum LED Current per Channel
1.2
4-Channel, VIN = 4.5V,
VOUT = 40V, FSW = 600kHz
1.22
mV
1.24
30
V
mA
PWM INTERFACE
VIL
Guaranteed Range for PWM Input Low Voltage
VIH
Guaranteed Range for PWM Input High Voltage
1.5
PWMI Input Frequency Range
100
FPWMI
PWMACC
PWMI Input Accuracy
PWMHYST
PWMI Input Allowable Jitter Hysteresis
0.8
V
V
30,000
8
-0.46
Hz
bits
+0.46
LSB
PWM GENERATOR
FPWM
VRFPWM
tDIRECTPWM
PWM Dimming Frequency Range
RFPWM = 1.5MΩ
45
50
55
Hz
RFPWM = 1.5kΩ
33
37
39
kHz
1.19
1.22
1.24
V
350
ns
4.3
V
Voltage at RFPWM pin
Direct PWM Minimum On Time
Direct PWM Mode
250
FAULT DETECTION
VSC
V TEMP_ACC
Channel Short Circuit Threshold
3.15
Over-Temperature Threshold Accuracy
V TEMP_SHDN
Over-Temperature Shutdown
VOVPlo
Overvoltage Limit on OVP Pin
7
1.2
3.6
5
°C
150
°C
1.22
1.24
V
FN7630.1
September 14, 2011
ISL97675
Electrical Specifications All specifications below are tested at TA = +25°C; VIN = 12V, EN = 3.3V, RISET = 19.6kΩ, unless otherwise noted.
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
OVPFAULT
PARAMETER
CONDITION
MIN
(Note 8)
OVP Short Detection Fault Level
TYP
MAX
(Note 8)
350
UNIT
mV
IFAULT
Fault Pull-down Current
VIN = 12V
8
15
25
µA
VFAULT
Fault Clamp Voltage with Respect to VIN
VIN = 12, VIN - VFAULT
6
7
8.3
V
1.2
1.4
1.5
V
1
3.5
5
mA
SWStart_thres
ISW_Startup
SW Start-Up Threshold
SW Start-Up Current
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. At minimum VIN of 4.5V, the maximum output is limited by the VOUT specifications. Also at maximum VIN of 26V, the minimum VOUT is 28V but
minimum VOUT can be lower at lower VIN. In general, the VIN and VOUT relationship is bounded by DMAX and DMIN.
8
FN7630.1
September 14, 2011
ISL97675
Typical Performance Curves
100
100
80
24VIN
12VIN
5VIN
EFFICIENCY (%)
EFFICIENCY (%)
80
60
40
5VIN
12VIN
10
20
ILED (mA)
60
40
20
20
0
0
5
10
15
20
0
25
0
ILED (mA)
FIGURE 2. EFFICIENCY vs 20mA LED CURRENT (100% LED DUTY
CYCLE) for 4P12S vs VIN
80
20mA/1.2MHz
20mA/582kHz
60
EFFICIENCY (%)
EFFICIENCY (%)
40
100
80
40
30mA/1.2MHz
30mA/582kHz
60
40
20
20
0
0
0
10
20
30
0
10
20
30
VIN (V)
VIN (V)
FIGURE 5. EFFICIENCY vs V IN vs SWITCHING FREQUENCY AT
30mA for 4P10S(100% LED DUTY CYCLE)
FIGURE 4. EFFICIENCY vs VIN vs SWITCHING FREQUENCY AT
20mA for 4P12S (100% LED DUTY CYCLE)
100
0.25
+25°C
CURRENT MATCHING (%)
-40°C
80
70
4.5VIN
0.20
0°C
90
EFFICIENCY (%)
30
FIGURE 3. EFFICIENCY vs 30mA LED CURRENT (100% LED DUTY
CYCLE) for 4P10S vs VIN
100
+85°C
0.15
0.10
0.05
0.00
-0.05
12VIN
-0.10
-0.15
21VIN
-0.20
60
24VIN
0
5
10
15
20
25
VIN (V)
FIGURE 6. EFFICIENCY vs VIN vs TEMPERATURE AT 20mA
9
30
-0.25
0
1
2
3
4
CHANNEL
FIGURE 7. CHANNEL-TO-CHANNEL CURRENT MATCHING
FN7630.1
September 14, 2011
ISL97675
Typical Performance Curves
(Continued)
10
1.0
0.8
9
0.6
IIN (mA)
ILED mA
4.5VIN
12VIN
0.4
0.2
0
8
7
6
0
1
2
3
4
5
6
DC (%)
5
0
5
10
15
20
25
30
VIN (V)
FIGURE 8. CURRENT LINEARITY vs LOW LEVEL PWM DIMMING DUTY
CYCLE vs VIN
FIGURE 9. QUIESCENT CURRENT vs VIN WITH PART ENABLED
0.60
-40°C
+25°C
VHEADROOM (V)
0.55
0.50
0°C
0.45
0.40
0
5
10
15
20
25
30
VIN (V)
FIGURE 10. VHEADROOM vs VIN vs TEMPERATURE AT 20mA
FIGURE 12. IN-RUSH AND LED CURRENT AT VIN = 6V FOR 4P12S
AT 20mA/CHANNEL
10
FIGURE 11. VOUT RIPPLE VOLTAGE, VIN = 12V, 4P12S AT
20mA/CHANNEL
FIGURE 13. IN-RUSH AND LED CURRENT AT VIN = 12V FOR 4P12S
AT 20mA/CHANNEL
FN7630.1
September 14, 2011
ISL97675
Typical Performance Curves
(Continued)
FIGURE 14. LINE REGULATION WITH VIN CHANGE FROM 6V TO 26V,
VIN = 12V, 4P12S AT 20mA/CHANNEL
FIGURE 15. LINE REGULATION WITH VIN CHANGE FROM 26V TO 6V
FOR 4P12S AT 20mA/CHANNEL
FIGURE 16. LOAD REGULATION WITH ILED CHANGE FROM 0% TO
100% PWM DIMMING, VIN = 12V, 4P12S AT
20mA/CHANNEL
FIGURE 17. LOAD REGULATION WITH ILED CHANGE FROM 100% TO
0% PWM DIMMING, VIN = 12V, 4P12S AT
20mA/CHANNEL
FIGURE 18. ISL97675 SHUTS DOWN AND STOPS SWITCHING ~ 30ms AFTER EN GOES LOW
11
FN7630.1
September 14, 2011
ISL97675
Theory of Operation
PWM Boost Converter
The current mode PWM boost converter produces the minimal
voltage needed to enable the LED stack with the highest forward
voltage drop to run at the programmed current. The ISL97675
employs current mode control boost architecture that has a fast
current sense loop and a slow voltage feedback loop. Such
architecture achieves a fast transient response that is essential
for the notebook backlight application. The input power may
instantly change when the user switches from a drained battery
to a AC/DC adapter without causing any flicker in the display
backlight. The ISL97675 is capable of boosting up to 45V and
typically can drive 13 (3.2V/20mA) LEDs in series on each of the
4 channels.
The LED peak current is set by translating the RISET current to the
output with a scaling factor of 392/RISET. The drain terminals of
the current source MOSFETs are designed to run at ~ 500mV to
minimize power loss. The sources of errors for the channel-tochannel current matching are due to internal mismatches,
offsets and the external RISET resistor. To minimize this external
offset, a 1% tolerance resistor is recommended.
OVP
The Overvoltage Protection (OVP) pin has a primary function of
setting the overvoltage trip level.
+
-
(EQ. 1)
The ISL97675 has a patent pending switching architecture that
uses the OVP block for feedback monitoring, hence allowing very
low PWM dimming duty cycle operation. As a result, the
overvoltage trip level also limits the VOUT regulation range
between 64% and 100% of the VOUT_OVP and the equation is:
Allowable V OUT = 64% to 100% of V OUT _OVP
(EQ. 2)
For example, if 10 LEDs are used with the worst case VOUT of 35V, and
RUPPER and RLOWER are chosen such that the OVP level is set at 40V,
then the allowed VOUT range is between 25.6V and 40V. If the
requirement is changed to 6 LEDs/channel for a maximum VOUT of
21V, then the OVP level must be reduced according to Equation 2 to
accommodate the new reduced output voltage. Otherwise, the
headroom control will be disturbed and the channel voltage may
be higher and prevent the driver from operating properly.
The ratio of the OVP capacitors should be the inverse of the OVP
resistors. For example, if RUPPER/RLOWER = 33/1, then
CUPPER/CLOWER = 1/33. For example, if CUPPER = 100pF then
CLOWER = 3.3nF.
Enable
An EN signal is required to enable the internal regulator for normal
operation. If there is no signal longer than 28ms, the device will
enter shutdown.
Power Sequence
There is no specific power sequence requirement for the
ISL97675. The EN signal can be tied to VIN but not the VDDIO as
it will prevent the device from powering up.
+
-
RISET
The ISL97675 OVP threshold is set by RUPPER and RLOWER such
that:
V OUT _OVP = 1.21V × ( R UPPER + R LOWER ) ⁄ R LOWER
REF
PWM DIMMING
FIGURE 19. SIMPLIFIED CURRENT SOURCE CIRCUIT
Dynamic Headroom Control
The ISL97675 features a proprietary Dynamic Headroom Control
circuit that detects the highest forward voltage string or
effectively the lowest voltage from any of the FB1-4 pins digitally.
This lowest FB voltage is used as the feedback signal for the
boost regulator. Since all LED stacks are connected in parallel to
the same output voltage, the other FB pins will have a higher
voltage, but the regulated current source circuit on each channel
will ensure that each channel has the same current. The output
voltage will regulate cycle by cycle and it is always referenced to
the highest forward voltage string in the architecture.
Dimming Controls
The ISL97675 allows two ways of controlling the LED current, and
therefore, the brightness. They are:
1. DC current adjustment.
2. PWM chopping of the LED current defined in step 1.
Maximum DC Current Setting
The initial brightness should be set by choosing an appropriate
value for RISET. This should be chosen to fix the maximum
possible LED current:
( 392 )
I LEDmax = --------------R ISET
(EQ. 3)
For example, if the maximum required LED current
(ILED(max)) is 20mA, rearranging Equation 3 yields Equation 4:
R ISET = ( 392 ) ⁄ 0.02 = 19.6kΩ
(EQ. 4)
Current Matching and Current Accuracy
Each channel of the LED current is regulated by the current
source circuit, as shown in Figure 19.
12
FN7630.1
September 14, 2011
ISL97675
PWM Control
The ISL97675 has a high speed 8-bit digitizer that decodes an
incoming PWM signal and converts it into four channels of 8-bit
PWM current with a phase shift function that will be described later.
During the PWM On period, the LED peak current is defined by the
value of RISET resistor, the average LED current of each channel is
controlled by ILEDmax and the PWM duty cycle in percent as:
I LED ( ave ) = I LEDmax × PWM
(EQ. 5)
ILED4-20mA
ILED3-20mA
ILED2-20mA
ILED1-20mA
ILED_Total_80mA
When the PWM input = 0, all channels are disconnected and the
ILED is guaranteed to be <10µA in this state.
The PWM dimming frequency is adjusted by a resistor at the
RFPWM pin, which will be described in “PWM Dimming
Frequency Adjustment” on page 14.
5
10
TIME (ms)
FIGURE 22. CONVENTIONAL LED DRIVER PWM DIMMING CHANNEL
AND TOTAL CURRENT AT 50% DUTY CYCLE
ILED1-20mA
ILED2-20mA
ILED3-20mA
ILED4-20mA
ILED4-20mA
ILED3-20mA
ILED_Total_80mA
ILED2-20mA
5
10
TIME (ms)
15
FIGURE 20. CONVENTIONAL 4-Ch LED DRIVER WITH 10% PWM
DIMMING CHANNEL CURRENT (UPPER) AND TOTAL
CURRENT (LOWER)
ILED1-20mA
ILED_Total_40mA
5
10
TIME (ms)
FIGURE 23. EQUAL PHASE SHIFT LED DRIVERpwm DIMMING
CHANNEL AT 50% DUTY CYCLE
ILED1-20mA
ILED2-20mA
Phase Shift Control
ILED3-20mA
The ISL97675 is capable of delaying the phase of each current
source. Conventional LED drivers pose the worst load transients
to the boost circuit by turning on all channels simultaneously as
shown in Figure 20. In contrast, the ISL97675 phase shifts each
channel by turning them on once during each PWM dimming
period as shown in Figure 21. At each dimming duty cycle except
at 100%, the sum of the phase shifted channel currents will be
less than a conventional LED driver as shown in Figure 21 and
23. Equal phase means there is fixed delay between channels
and such delay can be calculated as:
ILED4-20mA
ILED_Total_20mA
5
10
TIME (ms)
FIGURE 21. PHASE SHIFT 4-Ch LED DRIVER WITH 10% PWM
DIMMING CHANNEL CURRENT (UPPER) AND TOTAL
CURRENT (LOWER)
t FPWM 255
t D1 = ------------------ x ⎛ ----------⎞
( 255 ) ⎝ N ⎠
(EQ. 6)
t FPWM
255
t D2 = ------------------ x ⎛ ( 255 ) – ( N – 1 ) ⎛ ----------⎞ ⎞
⎝ N ⎠⎠
255 ⎝
(EQ. 7)
where (255/N) in Equation 6 and Equation 7 can only be integer
because the PWM dimming is controlled by an internal 8-bit
13
FN7630.1
September 14, 2011
ISL97675
digital counter. As a result, any decimal value of (255/N) will be
discarded. For example for N = 4, (255/N) = 63, thus:
63
t D1 = t FPWM × ---------255
TABLE 1.
(EQ. 8)
66
t D2 = t FPWM × ---------255
where tFPWM is the sum of tON and tOFF. N is the number of active
channels. The ISL97675 will detect the numbers of active
channels automatically and is illustrated in Figure 24 for 4channel.
40%
60%
FUNCTION
PHASE
SHIFT
Dimming
Resolution
Connects with
Resistor
PWM Dimming with
frequency adjust
Yes
8-bit
Floating
DirectPWM without
frequency adjust
No
N/A
When the FSW/PhaseShift pin is biased from VDDIO with a
resistor divider RUPPER and RLOWER, the switching frequency and
phase shift function will change according to the following
FSW/PhaseShift levels shown in Table 2 with the recommended
RUPPER and RLOWER values.
tFPWM (tPWMOUT)
tOFF
tON
40%
60%
ILED1
ILED2
RFWM/
DIRECTPWM
Switching Frequency
tPWMIN
PWMI
Table 1 shows the PWM Dimming with Phase Shift and Direct
PWM Dimming configurations.
tD1
tD1
ILED3
TABLE 2.
tD1
SWITCHING
FREQUENCY
PHASE
SHIFT
RUPPER
(kΩ)
RLOWER
(kΩ)
0 ~ 0.25 * VDDIO
1.2MHz
Yes
Open
0
0.25 * VDDIO ~ 0.5 * VDDIO
1.2MHz
No
150
100
0.5 * VDDIO ~ 0.75 * VDDIO
600kHz
No
100
150
0.75 * VDDIO ~ VDDIO
600kHz
Yes
0
Open
FSW/PHASE
SHIFT LEVEL
tD1
ILED4
tD2
ILED1
tD1 = Fixed Delay with Integer only while the decimal value
will be discarded (e.g. 63.75 = 63)
FIGURE 24. 4 EQUAL PHASE CHANNELS PHASE SHIFT
ILLUSTRATION
Inrush Control and Soft-Start
The ISL97675 has separate built-in independent inrush control and
soft-start functions. The inrush control function is built around the
short circuit protection FET, and is only available in applications which
include this device.
PWM Dimming Frequency Adjustment
The dimming frequency is set by an external resistor at the
RFPWM/DirectPWM pin to GND:
7
6.66 ×10
F PWM = -----------------------RFPWM
(EQ. 9)
where FPWM is the desirable PWM dimming frequency and
RFPWM is the setting resistor. Do not bias RFPWM/DirectPWM if
direct PWM dimming is used, see Table 1 for clarification.
The PWM dimming frequency can be set or applied up to 30kHz
with duty cycle from 0.4% to 100%. The lower limit of 0.4% is the
result of 8-bit digitizer resolution.
Direct PWM Dimming
The ISL97675 can also operate in direct PWM dimming mode
such that the output follows the input PWM signal without phase
shifting. To use Direct PWM mode, users should float
RFPWM/DirectPWM pin. The input PWM frequency should be
limited to 30kHz and the minimum duty cycle be calculated by
the following Equation 10:
Min Duty Cycle = 350ns × Input PWM Frequency
(EQ. 10)
For example, for a 200 Hz input PWM frequency, the minimum
duty cycle is:
Min DC = 350ns × 200Hz = 0.007%
14
(EQ. 11)
After an initial delay from the point where the master Fault
Protection FET is turned on, it is assumed that inrush has
completed. At this point, the boost regulator will begin to switch
and the current in the inductor will ramp-up. The current in the
boost power switch is monitored and the switching is terminated
in any cycle where the current exceeds the current limit. The
ISL97675 includes a soft-start feature where this current limit
starts at a low value (275mA). This is stepped up to the final 2.2A
current limit in 7 further steps of 275mA. These steps will
happen over at least 8ms, and will be extended at low LED PWM
frequencies if the LED duty cycle is low. This allows the output
capacitor to be charged to the required value at a low current
limit and prevents high input current for systems that have only a
low to medium output current requirement.
For systems with no master fault protection FET, the inrush
current will flow towards COUT when VIN is applied and it is
determined by the ramp rate of VIN and the values of COUT and
boost inductor, L.
Fault Protection and Monitoring
The ISL97675 features extensive protection functions to cover all
the perceivable failure conditions. The failure mode of an LED
can be either open circuit or as a short. The behavior of an open
circuited LED can additionally take the form of either infinite
FN7630.1
September 14, 2011
ISL97675
resistance or, for some LEDs, a zener diode, which is integrated
into the device in parallel with the now opened LED.
For basic LEDs (which do not have built-in zener diodes), an open
circuit failure of an LED will only result in the loss of one channel
of LEDs without affecting other channels. Similarly, a LED short
circuit condition which causes the FB voltage to rise to ~4V, will
result in that channel turning off. This does not affect any other
channels.
Due to the lag in boost response to any load change at its output,
certain transient events (such as LED current steps or significant
step changes in LED duty cycle) can transiently look like LED
fault modes. The ISL97675 uses feedback from the LEDs to
determine when it is in a stable operating region and prevents
apparent faults during these transient events from allowing any
of the LED stacks to fault out. See Table 3 for more details.
A fault condition that results in high input current due to a short
on VOUT with master fault protection switch will result in a
shutdown of all output channels. The control device logic will
remain functional.
Short Circuit Protection (SCP)
The short circuit detection circuit monitors the voltage on each
channel and disables faulty channels which are detected above
the programmed short circuit threshold. When an LED becomes
shorted, the action taken is described in Table 3. The short circuit
threshold is 4V.
Open Circuit Protection (OCP)
When one of the LEDs becomes open circuit, it can behave as
either an infinite resistance or a gradually increasing finite
resistance. The ISL97675 monitors the current in each channel
such that any string which reaches the intended output current is
considered “good”. Should the current subsequently fall below
the target, the channel will be considered an “open circuit”.
Furthermore, should the boost output of the ISL97675 reach the
OVP limit or should the lower over-temperature threshold be
reached, all channels which are not “good” will immediately be
considered as “open circuit”. Detection of an “open circuit”
channel will result in a time-out before disabling of the affected
channel. This time-out is run when the device is above the lower
over-temperature threshold in an attempt to prevent the upper
over-temperature trip point from being reached.
Some users employ special types of LEDs that have zener diode
structure in parallel with the LED for ESD enhancement, thus
enabling open circuit operation. When this type of LED goes open
circuit, the effect is as if the LED forward voltage has increased,
but no light is emitted. Any affected string will not be disabled,
unless the failure results in the boost OVP limit being reached,
allowing all other LEDs in the string to remain functional. Care
should be taken in this case that the boost OVP limit and SCP limit
are set properly, to make sure that multiple failures on one string
do not cause all other good channels to be faulted out. This is due
to the increased forward voltage of the faulty channel making all
other channels look as if they have LED shorts. See Table 3 for
details for responses to fault conditions.
15
Overvoltage Protection (OVP)
The integrated OVP circuit monitors the output voltage and keeps
the voltage at a safe level. The OVP threshold is set as:
OVP = 1.21V × ( R UPPER + R LOWER ) ⁄ R LOWER
(EQ. 12)
These resistors should be large to minimize the power loss. For
example, a 1MΩ RUPPER and 30kΩ RLOWER sets OVP to 41.2V.
Large OVP resistors also allow COUT discharges slowly during the
PWM Off time. Parallel capacitors should also be placed across
the OVP resistors such that RUPPER/RLOWER = CLOWER/CUPPER.
Using a CUPPER value of at least 30pF is recommended. These
capacitors reduce the AC impedance of the OVP node, which is
important when using high value resistors.
Undervoltage Lockout
If the input voltage falls below the UVLO level of 3.1V, the device
will stop switching and be reset. Operation will restart once the
input voltage is back in the normal operating range.
Master Fault Protection
During normal switching operation, the current through the
internal boost power FET is monitored. If the input current
exceeds the current limit due to output shorted to ground or
excessive loading, the internal switch will be turned off. This
monitoring happens on a cycle by cycle basis in a self protecting
way.
Additionally, the ISL97675 monitors the voltage at the LX and
OVP pins. At start-up, a fixed current is injected out of the LX pins
and into the output capacitor. The device will not start up unless
the voltage at LX exceeds 1.2V. The OVP pin is also monitored
such that if it rises above and subsequently falls below 20% of
the target OVP level, the input protection FET will be switched off.
Over-Temperature Protection (OTP)
The ISL97675 includes two over-temperature thresholds. The lower
threshold is set to +130°C. When this threshold is reached, any
channel which is outputting current at a level below the regulation
target will be treated as “open circuit” and disabled after a time-out
period. The intention of the lower threshold is to allow bad channels
to be isolated and disabled before they cause enough power
dissipation (as a result of other channels having large voltages
across them) to hit the upper temperature threshold.
The upper threshold is set to +150°C. Each time this is reached,
the boost will stop switching and the output current sources will
be switched off.
For the extensive fault protection conditions, please refer to
Figure 25 and Table 3 for details.
FN7630.1
September 14, 2011
ISL97675
VOUT
LX
VIN
DRIVER
IMAX
ILIMIT
FAULT
O/P
SHORT
LOGIC
OVP
FET
DRIVER
FB1
VSC
VIN
FB4
VSET/2
REG
THRM
SHDN
REF
OTP
T2
TEMP
SENSOR
T1
VSET
+
Q1 VSET
PWM1/OC1/SC1
+
Q4
-
-
PWM4/OC4/SC4
PHASE SHIFT &
CONTROL
LOGIC
FIGURE 25. SIMPLIFIED FAULT PROTECTIONS
TABLE 3. PROTECTIONS TABLE
CASE
FAILURE MODE
DETECTION MODE
FAILED CHANNEL ACTION
GOOD CHANNELS
ACTION
VOUT
REGULATED
BY
1
FB1 Short Circuit
Upper Over-Temperature Protection
FB1 ON and burns power.
limit (OTP) not triggered and FB1 < 4V
2
FB1 Short Circuit
Upper OTP triggered but VFB1 < 4V
3
FB1 Short Circuit
Upper OTP not triggered but FB1 > 4V FB1 disabled after 6 PWM cycle FB2 through FB4 Normal Highest VF of FB2
timeout.
through FB4
4
FB1 Open Circuit with
infinite resistance
Upper OTP not triggered and FB1 < 4V VOUT will ramp to OVP. FB1 will FB2 through FB4 Normal Highest VF of FB2
through FB4
time-out after 6 PWM cycles
and switch off. VOUT will drop to
normal level.
5
FB1 LED Open Circuit
but has paralleled
Zener
Upper OTP not triggered and FB1 < 4V FB1 remains ON and has
FB2 through FB4 ON, Q2
highest VF, thus VOUT increases. through Q4 burn power
VF of FB1
6
FB1 LED Open Circuit
but has paralleled
Zener
Upper OTP triggered but FB1 < 4V
VF of FB1
16
FB2 through FB4 Normal Highest VF of FB2
through FB4
All channels go off until chip
Same as FB1
cooled and then comes back on
with current reduced to 76%.
Subsequent OTP triggers will
reduce IOUT further.
All channels go off until chip
Same as FB1
cooled and then comes back on
with current reduced to 76%.
Subsequent OTP triggers will
reduce IOUT further
Highest VF of FB2
through FB4
FN7630.1
September 14, 2011
ISL97675
TABLE 3. PROTECTIONS TABLE (Continued)
DETECTION MODE
FAILED CHANNEL ACTION
GOOD CHANNELS
ACTION
VOUT
REGULATED
BY
CASE
FAILURE MODE
7
FB1 LED Open Circuit
but has paralleled
Zener
Upper OTP not triggered but FBx > 4V FB1 remains ON and has
VOUT increases, then FB-X VF of FB1
highest VF, thus VOUT increases. switches OFF after 6
PWM cycles. This is an
unwanted shut off and
can be prevented by
setting OVP at an
appropriate level.
8
Channel-to-Channel
ΔVF too high
Lower OTP triggered but FBx < 4V
Any channel at below the target current will fault out after 6 Highest VF of FB1
through FB4
PWM cycles.
Remaining channels driven with normal current.
9
Channel-to-Channel
ΔVF too high
Upper OTP triggered but FBx < 4V
All channels go off until chip cooled and then comes back
on with current reduced to 76%. Subsequent OTP triggers
will reduce IOUT further
Highest VF of FB1
through FB4
10
Output LED stack
voltage too high
VOUT > VOVP
Any channel that is below the target current will time-out
after 6 PWM cycles, and VOUT will return to the normal
regulation voltage required for other channels.
Highest VF of FB1
through FB4
11
VOUT/LX shorted to
LX current and timing are monitored. The chip is permanently shutdown 31ms after power-up if
VOUT/Lx is shorted to GND.
GND at start-up or VOUT OVP pins monitored for excursions
below 20% of OVP threshold.
shorted in operation
Components Selections
Input Capacitor
According to the inductor Voltage-Second Balance principle, the
change of inductor current during the switching regulator On-time is
equal to the change of inductor current during the switching
regulator Off-time. Since the voltage across an inductor is:
Switching regulators require input capacitors to deliver peak
charging current and to reduce the impedance of the input
supply. This reduces interaction between the regulator and input
supply, thereby improving system stability. The high switching
frequency of the loop causes almost all ripple current to flow in
the input capacitor, which must be rated accordingly.
V L = L × ΔI L ⁄ Δt
(EQ. 13)
and ΔIL @ TON = ΔIL @ TOFF, therefore:
( V I – 0 ) ⁄ L × D × tS = ( VO – V D – VI ) ⁄ L × ( 1 – D ) × tS
(EQ. 14)
where D is the switching duty cycle defined by the turn-on time over
the switching period. VD is Schottky diode forward voltage which can
be neglected for approximation.
Rearranging the terms without accounting for VD gives the boost
ratio and duty cycle respectively as:
VO ⁄ VI = 1 ⁄ ( 1 – D )
(EQ. 15)
D = ( VO – VI ) ⁄ VO
(EQ. 16)
17
A capacitor with low internal series resistance should be chosen
to minimize heating effects and improve system efficiency, such
as X5R or X7R ceramic capacitors, which offer small size and a
lower value of temperature and voltage coefficient compared to
other ceramic capacitors.
In boost mode, input current flows continuously into the inductor;
AC ripple component is only proportional to the rate of the
inductor charging, thus, smaller value input capacitors may be
used. It is recommended that an input capacitor of at least 10µF
be used. Ensure the voltage rating of the input capacitor is
suitable to handle the full supply range.
FN7630.1
September 14, 2011
ISL97675
The selection of the inductor should be based on its maximum
current (ISAT) characteristics, power dissipation (DCR), EMI
susceptibility (shielded vs unshielded), and size. Inductor type
and value influence many key parameters, including ripple
current, current limit, efficiency, transient performance and
stability.
The inductor’s maximum current capability must be large enough
to handle the peak current at the worst case condition. If an
inductor core is chosen with a lower current rating, saturation in
the core will cause the effective inductor value to fall, leading to
an increase in peak to average current level, poor efficiency and
overheating in the core. The series resistance, DCR, within the
inductor causes conduction loss and heat dissipation. A shielded
inductor is usually more suitable for EMI susceptible
applications, such as LED backlighting.
The peak current can be derived from the voltage across the
inductor during the off period, as expressed in Equation 17:
IL peak = ( V O × I O ) ⁄ ( 85% × V I ) + 1 ⁄ 2 [ V I × ( V O – V I ) ⁄ ( L × V O × f SW ) ]
(EQ. 17)
The choice of 85% is just an average term for the efficiency
approximation. The first term is the average current, which is
inversely proportional to the input voltage. The second term is
the inductor current change, which is inversely proportional to L
and fSW. As a result, for a given switching frequency, minimum
input voltage must be used to calculate the input/inductor
current as shown in Equation 17. Fora given inductor size, the
larger the inductance value, the higher the series resistance
because of the extra number of turns required, thus, higher
conductive losses. The ISL97675 current limit should be less
than the inductor saturation current.
Output Capacitors
The output capacitor acts to smooth the output voltage and
supplies load current directly during the conduction phase of the
power switch. Output ripple voltage consists of the discharge of
the output capacitor during the FET ton period and the voltage
drop due to load current flowing through the ESR of the output
capacitor. The ripple voltage is shown in Equation 18:
ΔV CO = ( I O ⁄ C O × D ⁄ f S ) + ( ( I O × ESR )
(EQ. 18)
Equation 18 shows the importance of using a low ESR output
capacitor for minimizing output ripple.
The choice of X7R over Y5V ceramic capacitors is highly
recommended because the former capacitor is less sensitive to
capacitance change over voltage as shown in Figure 26. Y5V’s
absolute capacitance can be reduced to 10%~20% of its rated
capacitance at the maximum voltage. In any case, Y5V type of
ceramic capacitor should be avoided.
For 20mA applications with VIN < 7V, 2 x 4.7µF (X7R type) is
required in some configurations.
3.0
POLY. (CERAMIC X7R 2.2µF 50V CAP)
2.5
CAPACITANCE (µF)
Inductor
2.0
1.5
1.0
POLY. (CERAMIC Y5V 2.2µF 50V CAP)
0.5
0
0
5
10
15
20
25
30
35
40
45
APPLIED VOLTAGE (V)
FIGURE 26. X7R AND V5Y TYPES CERAMIC CAPACITORS
Channel Capacitor
It is recommended to use at least 1.5nF capacitors from CH pins
to VOUT. Larger capacitors will reduce LED current ripple at boost
frequency, but will degrade transient performance at high PWM
frequencies. The best value is dependant on PCB layout. Up to
4.7nF is sufficient for most configurations.
Output Ripple
ΔVCo, can be reduced by increasing Co or fSW, or using small ESR
capacitors as shown in Equation 18. In general, Ceramic
capacitors are the best choice for output capacitors in small to
medium sized LCD backlight applications due to their cost, form
factor, and low ESR.
A larger output capacitor will also ease the driver response
during PWM dimming off period due to the longer sample and
hold effect of the output drooping. The driver does not need to
boost as much on the next on period which minimizes transient
current. The output capacitor is also needed for compensation,
and, in general one to two 4.7µF/50V ceramic capacitors are
needed for netbook or notebook display backlight applications.
Schottky Diode
A high speed rectifier diode is necessary to prevent excessive
voltage overshoot, especially in the boost configuration. Low
forward voltage and reverse leakage current will minimize
losses, making Schottky diodes the preferred choice. Although
the Schottky diode turns on only during the boost switch off
period, it carries the same peak current as the inductor,
therefore, a suitable current rated Schottky diode must be used.
Here are some recommendations for various applications:
For 20mA applications with VIN > 7V, 1 x 4.7µF (X7R type) is
sufficient.
18
FN7630.1
September 14, 2011
ISL97675
Applications
High Current Applications
Each channel of the ISL97675 can support up to 40mA. For
applications that need higher current, multiple channels can be
grouped to achieve the desirable current. For example, the
cathode of the last LED can be connected to FB1 to FB2, this
configuration can be treated as a single string with 80mA current
driving capability.
VOUT
FB1
FB2
FIGURE 27. GROUPING MULTIPLE CHANNELS FOR HIGH CURRENT
APPLICATIONS
19
FN7630.1
September 14, 2011
ISL97675
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
9/14/11
FN7630.1
CHANGE
On page 3 in “Pin Descriptions”:
Changed pin 3 description from:
“FSW = 0 ~ 0.25 * VDDIO, Boost Switching Frequency = 600kHz with phase shift.
FSW = 0.25 * VDDIO ~ 0.5 * VDDIO, Boost Switching Frequency = 600kHz without phase shift.
FSW = 0.5 * VDDIO ~ 0.75 * VDDIO, Boost Switching Frequency = 1.2MHz without phase shift.
FSW = 0.75 * VDDIO ~ VDDIO, Boost Switching Frequency = 1.2MHz with phase shift.”
to
“FSW = 0 ~ 0.25 * VDDIO, Boost Switching Frequency = 1.2MHz with phase shift.
FSW = 0.25 * VDDIO ~ 0.5 * VDDIO, Boost Switching Frequency = 1.2MHz without phase shift.
FSW = 0.5 * VDDIO ~ 0.75 * VDDIO, Boost Switching Frequency = 600KHz without phase shift.
FSW = 0.75 * VDDIO ~ VDDIO, Boost Switching Frequency = 600KHz with phase shift.”
On page 14 in Table 2:
Changed “Switching Frequency” in first 2 rows from 600khz to 1.2Mhz
Changed “Switching Frequency” in last 2 rows from 1.2MHz to 600kHz
Updated Tape & Reel note in Ordering Information to add "Add “-T*” suffix for tape and reel." The "*" covers all
possible tape and reel options
5/19/10
FN7630.0
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL97675
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
20
FN7630.1
September 14, 2011
ISL97675
Package Outline Drawing
L20.4x4C
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/06
4X
4.00
2.0
16X 0.50
A
B
16
6
PIN #1 INDEX AREA
20
6
PIN 1
INDEX AREA
1
4.00
15
2 .70 ± 0 . 15
11
(4X)
5
0.15
6
10
0.10 M C A B
4 20X 0.25 +0.05 / -0.07
20X 0.4 ± 0.10
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0 . 1
C
BASE PLANE
( 3. 8 TYP )
(
SEATING PLANE
0.08 C
2. 70 )
( 20X 0 . 5 )
SIDE VIEW
( 20X 0 . 25 )
C
0 . 2 REF
5
( 20X 0 . 6)
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
21
FN7630.1
September 14, 2011
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