Data Sheet

DF
N1
010
D-3
PDTD113/123/143/114EQA
series
50 V, 500 mA NPN resistor-equipped transistors
Rev. 1 — 4 February 2016
Product data sheet
1. Product profile
1.1 General description
NPN Resistor-Equipped Transistor (RET) family in a leadless ultra small DFN1010D-3
(SOT1215) Surface-Mounted Device (SMD) plastic package with visible and solderable
side pads.
Table 1.
Product overview
Type number
R1
R2
Package NXP
PNP complement
PDTD113EQA
1 k
1 k
PDTB113EQA
PDTD123EQA
2.2 k
2.2 k
DFN1010D-3
(SOT1215)
PDTB123EQA
PDTD143EQA
4.7 k
4.7 k
PDTB143EQA
PDTD114EQA
10 k
10 k
PDTB114EQA
1.2 Features and benefits
 500 mA output current capability
 Built-in bias resistors
  10% resistor ratio tolerance
 Simplifies circuit design
 Reduces component count
 Reduced pick and place costs
 Low package height of 0.37 mm
 Suitable for Automatic Optical
Inspection (AOI) of solder joint
 AEC-Q101 qualified
1.3 Applications
 Digital applications
 Cost saving alternative for
BC807/BC817 series in digital
applications
 Controlling IC inputs
 Switching loads
1.4 Quick reference data
Table 2.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCEO
collector-emitter voltage
open base
-
-
50
V
IO
output current
-
-
500
mA
PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
2. Pinning information
Table 3.
Pinning
Pin
Symbol
Description
1
I
input (base)
2
GND
GND (emitter)
Simplified outline
Graphic symbol
O
1
3
O
output (collector)
4
O
output (collector)
R1
I
4
3
R2
GND
2
aaa-019964
Transparent top view
3. Ordering information
Table 4.
Ordering information
Type number
PDTD113EQA
PDTD123EQA
PDTD143EQA
Package
Name
Description
Version
DFN1010D-3
plastic thermal enhanced ultra thin small outline
package; no leads; 3 terminals;
body: 1.1  1.0  0.37 mm
SOT1215
PDTD114EQA
PDTD113_123_143_114EQA_SER
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
2 of 23
PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
4. Marking
Table 5.
Marking codes
Type number
Marking code
PDTD113EQA
01 00 11
PDTD123EQA
01 01 10
PDTD143EQA
01 10 01
PDTD114EQA
01 11 01
4.1 Binary marking code description
READING
DIRECTION
MARKING CODE
(EXAMPLE)
YEAR DATE
CODE
VENDOR CODE
PIN 1
INDICATION MARK
MARK-FREE AREA
READING EXAMPLE:
11
01
10
aaa-008041
Fig 1.
SOT1215 binary marking code description
5. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
PDTD113_123_143_114EQA_SER
Product data sheet
Symbol
Parameter
Conditions
Min
Max
Unit
VCBO
collector-base voltage
open emitter
-
50
V
VCEO
collector-emitter voltage
open base
-
50
V
VEBO
emitter-base voltage
open collector
-
10
V
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
3 of 23
PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
Table 6.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VI
input voltage
PDTD113EQA
10
+10
V
PDTD123EQA
10
+12
V
PDTD143EQA
10
+30
V
PDTD114EQA
10
+50
V
output current
IO
total power dissipation
Ptot
Tamb  25 C
-
500
mA
[1]
-
325
mW
[2]
-
575
mW
[3]
-
525
mW
[4]
-
940
mW
Tj
junction temperature
-
150
C
Tamb
ambient temperature
55
+150
C
Tstg
storage temperature
65
+150
C
[1]
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
[2]
Device mounted on an FR4 PCB, single-sided copper, tin-plated; mounting pad for collector 1 cm2.
[3]
Device mounted on an FR4 PCB, 4-layer copper, tin-plated and standard footprint.
[4]
Device mounted on an FR4 PCB, 4-layer copper, tin-plated; mounting pad for collector 1 cm2.
aaa-020246
1
(1)
Ptot
(W)
0.8
0.6
(2)
(3)
0.4
(4)
0.2
0
-75
-25
25
75
125
175
Tamb (ºC)
(1) FR4 PCB, 4-layer copper, 1 cm2
(2) FR4 PCB, single-sided copper, 1 cm2
(3) FR4 PCB, 4-layer copper, standard footprint
(4) FR4 PCB, single sided copper, standard footprint
Fig 2.
PDTD113_123_143_114EQA_SER
Product data sheet
Power derating curves
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
4 of 23
PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
6. Thermal characteristics
Table 7.
Thermal characteristics
Symbol
Parameter
Conditions
thermal resistance from junction
to ambient
Rth(j-a)
in free air
Min
Typ
Max
Unit
[1]
-
-
385
K/W
[2]
-
-
218
K/W
[3]
-
-
239
K/W
[4]
-
-
133
K/W
-
-
40
K/W
thermal resistance from junction
to solder point
Rth(j-sp)
[1]
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint.
[2]
Device mounted on an FR4 PCB, single-sided copper, tin-plated; mounting pad for collector 1 cm2.
[3]
Device mounted on an FR4 PCB, 4-layer copper, tin-plated and standard footprint.
[4]
Device mounted on an FR4 PCB, 4-layer copper, tin-plated; mounting pad for collector 1 cm2.
aaa-020247
103
duty cycle = 1
Zth(j-a)
(K/W)
0.75
0.5
0.33
102
0.2
0.1
0.05
10
0.02
0.01
0
1
10-5
10-4
10-3
10-2
10-1
1
10
102
103
tp (s)
FR4 PCB, single-sided copper, tin-plated and standard footprint
Fig 3.
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
PDTD113_123_143_114EQA_SER
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 23
PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
aaa-020248
103
Zth(j-a)
(K/W)
duty cycle = 1
0.75
102
0.5
0.33
0.2
0.1
0.05
10
0.02
0.01
0
1
10-5
10-4
10-3
10-2
10-1
1
10
102
103
tp (s)
FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2
Fig 4.
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
aaa-020250
103
Zth(j-a)
(K/W)
duty cycle = 1
0.75
102
0.5
0.33
0.2
0.1
0.05
10
0.02
0.01
0
1
10-5
10-4
10-3
10-2
10-1
1
10
102
103
tp (s)
FR4 PCB, 4-layer copper, tin-plated and standard footprint
Fig 5.
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
PDTD113_123_143_114EQA_SER
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
6 of 23
PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
aaa-020249
103
Zth(j-a)
(K/W)
duty cycle = 1
102
0.75
0.5
0.33
0.2
0.1
10
0.05
0.02 0.01
0
1
10-5
10-4
10-3
10-2
10-1
1
10
102
103
tp (s)
FR4 PCB, 4-layer copper, tin-plated; mounting pad for collector 1 cm2
Fig 6.
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
PDTD113_123_143_114EQA_SER
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
7 of 23
PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
7. Characteristics
Table 8.
Characteristics
Tamb = 25 C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ICBO
collector-base cut-off
current
VCB = 50 V; IE = 0 A
-
-
100
nA
ICEO
collector-emitter cut-off VCE = 50 V; IB = 0 A
current
-
-
0.5
A
IEBO
emitter-base cut-off current
-
-
4
mA
PDTD123EQA
-
-
2
mA
PDTD143EQA
-
-
0.9
mA
0.4
mA
PDTD113EQA
VEB = 5 V; IC = 0 A
PDTD114EQA
DC current gain
hFE
33
-
-
PDTD123EQA
40
-
-
PDTD143EQA
60
-
-
70
-
-
-
-
100
PDTD113EQA
VCE = 5 V; IC = 50 mA
PDTD114EQA
VCEsat
collector-emitter
saturation voltage
VI(off)
off-state input voltage
VCE = 5 V; IC = 100 A
0.6
1.05
1.5
V
0.6
1.05
1.8
V
PDTD143EQA
0.6
1.05
1.5
V
PDTD114EQA
0.6
1.05
1.5
V
1
1.45
1.8
V
PDTD123EQA
1
1.5
2
V
PDTD143EQA
1
1.7
2.2
V
1
2.2
3
V
PDTD113EQA
0.7
1
1.3
k
PDTD123EQA
1.54
2.2
2.86
k
PDTD143EQA
3.3
4.7
6.1
k
k
on-state input voltage
PDTD113EQA
VCE = 0.3 V; IC = 20 mA
PDTD114EQA
R1
mV
PDTD123EQA
PDTD113EQA
VI(on)
IC = 50 mA; IB = 2.5 mA
[1]
bias resistor 1 (input)
PDTD114EQA
R2/R1
bias resistor ratio
Cc
collector capacitance
VCB = 10 V; IE = ie = 0 A; f = 1 MHz
fT
transition frequency
VCE = 5 V; IC = 50 mA; f = 100 MHz
[1]
See section test information for resistor calculation and test conditions.
[2]
Characteristics of built-in transistor.
PDTD113_123_143_114EQA_SER
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 February 2016
7
10
13
[1]
0.9
1
1.1
-
5
-
pF
[2]
-
210
-
MHz
© NXP Semiconductors N.V. 2016. All rights reserved.
8 of 23
PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
aaa-020251
103
(1)
IB (mA) = 2.33
IC
(A)
(2)
hFE
aaa-020252
0.5
(3)
2.16
1.99
0.4
1.82
102
1.65
0.3
1.48
1.31
0.2
1.14
10
0.97
0.1
0.8
1
10-1
1
10
102
0
103
0
1
2
3
4
IC (mA)
5
VCE (V)
Tamb = 25 C
VCE = 5 V
(1) Tamb = 100 C
(2) Tamb = 25 C
(3) Tamb = 40 C
Fig 7.
PDTD113EQA: DC current gain as a function of
collector current; typical values
aaa-020254
10
VI(on)
(V)
Fig 8.
PDTD113EQA: Collector current as a function
of collector-emitter voltage; typical values
aaa-020255
10
VI(off)
(V)
(1)
1
(2)
1
(1)
(3)
(2)
(3)
10-1
10-1
1
10
102
103
10-1
10-1
IC (mA)
VCE = 0.3 V
VCE = 5 V
(1) Tamb = 40 C
(2) Tamb = 25 C
(2) Tamb = 25 C
(3) Tamb = 100 C
(3) Tamb = 100 C
PDTD113EQA: On-state input voltage as a
function of collector current; typical values
PDTD113_123_143_114EQA_SER
Product data sheet
10
IC (mA)
(1) Tamb = 40 C
Fig 9.
1
Fig 10. PDTD113EQA: Off-state input voltage as a
function of collector current; typical values
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
9 of 23
PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
aaa-020253
10-1
aaa-020256
16
Cc
(pF)
VCEsat
(V)
12
8
(1)
(2)
(3)
4
10-2
10
102
103
0
0
10
20
IC (mA)
30
40
50
VCB (V)
f = 1 MHz; Tamb = 25 C
IC/IB = 20
(1) Tamb = 100 C
(2) Tamb = 25 C
(3) Tamb = 40 C
Fig 11. PDTD113EQA: Collector-emitter saturation
voltage as a function of collector current;
typical values
PDTD113_123_143_114EQA_SER
Product data sheet
Fig 12. PDTD113EQA: Collector capacitance as a
function of collector-base voltage; typical
values
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
10 of 23
PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
aaa-020257
103
aaa-020258
0.5
IB (mA) = 2.4
IC
(A)
hFE
2.2
2
0.4
1.8
(1)
(2)
(3)
102
1.6
0.3
1.4
1.2
0.2
1
10
0.8
0.1
1
10-1
1
10
102
103
0.6
0
1
2
3
4
IC (mA)
5
VCE (V)
Tamb = 25 C
VCE = 5 V
(1) Tamb = 100 C
(2) Tamb = 25 C
(3) Tamb = 40 C
Fig 13. PDTD123EQA: DC current gain as a function of
collector current; typical values
aaa-020261
10
Fig 14. PDTD123EQA: Collector current as a function
of collector-emitter voltage; typical values
aaa-020262
10
VI(off)
(V)
VI(on)
(V)
(1)
1
1
(1)
(2)
(3)
10-1
10-1
1
10
102
(2)
(3)
103
10-1
10-1
IC (mA)
VCE = 0.3 V
VCE = 5 V
(1) Tamb = 40 C
(2) Tamb = 25 C
(2) Tamb = 25 C
(3) Tamb = 100 C
(3) Tamb = 100 C
Fig 15. PDTD123EQA: On-state input voltage as a
function of collector current; typical values
Product data sheet
10
IC (mA)
(1) Tamb = 40 C
PDTD113_123_143_114EQA_SER
1
Fig 16. PDTD123EQA: Off-state input voltage as a
function of collector current; typical values
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
11 of 23
PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
aaa-020260
10-1
aaa-020263
16
Cc
(pF)
VCEsat
(V)
12
8
(1)
(2)
(3)
4
10-2
1
10
102
103
0
0
10
20
IC (mA)
30
40
50
VCB (V)
f = 1 MHz; Tamb = 25 C
IC/IB = 20
(1) Tamb = 100 C
(2) Tamb = 25 C
(3) Tamb = 40 C
Fig 17. PDTD123EQA: Collector-emitter saturation
voltage as a function of collector current;
typical values
PDTD113_123_143_114EQA_SER
Product data sheet
Fig 18. PDTD123EQA: Collector capacitance as a
function of collector-base voltage; typical
values
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
12 of 23
PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
aaa-020264
103
aaa-020265
0.5
IB (mA) = 2.1
IC
(A)
hFE
1.9
1.7
0.4
1.5
102
1.3
0.3
(1)
(2)
(3)
1.1
0.9
0.2
0.7
10
0.5
0.1
0.3
1
10-1
1
10
102
103
0
0
1
2
3
4
IC (mA)
5
VCE (V)
Tamb = 25 C
VCE = 5 V
(1) Tamb = 100 C
(2) Tamb = 25 C
(3) Tamb = 40 C
Fig 19. PDTD143EQA: DC current gain as a function of
collector current; typical values
aaa-020268
102
VI(on)
(V)
Fig 20. PDTD143EQA: Collector current as a function
of collector-emitter voltage; typical values
aaa-020266
10
VI(off)
(V)
10
(1)
(2)
1
(3)
1
(1)
(2)
(3)
10-1
10-1
1
10
102
103
10-1
10-1
IC (mA)
VCE = 0.3 V
VCE = 5 V
(1) Tamb = 40 C
(2) Tamb = 25 C
(2) Tamb = 25 C
(3) Tamb = 100 C
(3) Tamb = 100 C
Fig 21. PDTD143EQA: On-state input voltage as a
function of collector current; typical values
Product data sheet
10
IC (mA)
(1) Tamb = 40 C
PDTD113_123_143_114EQA_SER
1
Fig 22. PDTD143EQA: Off-state input voltage as a
function of collector current; typical values
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
13 of 23
PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
aaa-020267
10-1
aaa-020269
16
Cc
(pF)
VCEsat
(V)
12
8
(1)
(2)
(3)
4
10-2
1
10
102
103
0
0
10
20
IC (mA)
30
40
50
VCB (V)
f = 1 MHz; Tamb = 25 C
IC/IB = 20
(1) Tamb = 100 C
(2) Tamb = 25 C
(3) Tamb = 40 C
Fig 23. PDTD143EQA: Collector-emitter saturation
voltage as a function of collector current;
typical values
PDTD113_123_143_114EQA_SER
Product data sheet
Fig 24. PDTD143EQA: Collector capacitance as a
function of collector-base voltage; typical
values
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
14 of 23
PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
aaa-020270
103
aaa-020271
0.5
IB (mA) = 2.05
IC
(A)
hFE
1.85
1.65
0.4
1.45
102
(1)
(2)
(3)
1.25
0.3
1.05
0.85
0.2
0.65
10
0.45
0.1
0.25
1
10-1
1
10
102
103
0
0
1
2
3
4
IC (mA)
5
VCE (V)
Tamb = 25 C
VCE = 5 V
(1) Tamb = 100 C
(2) Tamb = 25 C
(3) Tamb = 40 C
Fig 25. PDTD114EQA: DC current gain as a function of
collector current; typical values
aaa-020272
102
VI(on)
(V)
Fig 26. PDTD114EQA: Collector current as a function
of collector-emitter voltage; typical values
aaa-020273
10
VI(off)
(V)
10
(1)
1
(2)
(3)
(1)
(2)
(3)
1
10-1
10-1
1
10
102
103
10-1
10-1
IC (mA)
VCE = 0.3 V
VCE = 5 V
(1) Tamb = 40 C
(2) Tamb = 25 C
(2) Tamb = 25 C
(3) Tamb = 100 C
(3) Tamb = 100 C
Fig 27. PDTD114EQA: On-state input voltage as a
function of collector current; typical values
Product data sheet
10
IC (mA)
(1) Tamb = 40 C
PDTD113_123_143_114EQA_SER
1
Fig 28. PDTD114EQA: Off-state input voltage as a
function of collector current; typical values
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
15 of 23
PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
aaa-020274
10-1
aaa-020275
10
Cc
(pF)
8
VCEsat
(V)
6
(1)
4
(2)
(3)
2
10-2
1
10
102
0
103
0
10
20
IC (mA)
30
40
50
VCB (V)
f = 1 MHz; Tamb = 25 C
IC/IB = 20
(1) Tamb = 100 C
(2) Tamb = 25 C
(3) Tamb = 40 C
Fig 29. PDTD114EQA: Collector-emitter saturation
voltage as a function of collector current;
typical values
Fig 30. PDTD114EQA: Collector capacitance as a
function of collector-base voltage; typical
values
aaa-020276
103
fT
(MHz)
102
10
10-1
1
10
102
103
IC (mA)
VCE = 5 V; f = 100 MHz; Tamb = 25 °C
Fig 31. Transition frequency as a function of collector current; typical values of built-in transistor
PDTD113_123_143_114EQA_SER
Product data sheet
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Rev. 1 — 4 February 2016
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PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
8. Test information
8.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is
suitable for use in automotive applications.
8.2 Resistor calculation
• Calculation of bias resistor 1 (R1):
V  I I2  – V  I I1 
R1 = ----------------------------------I I2 – I I1
• Calculation method A of bias resistor ratio (R2/R1):
R2 = V  I I3  – 1
-----------------------R1
R1  I 13
• Calculation method B of bias resistor ratio (R2/R1):
V  I I4  – V  I I3 
R2
-–1
------- = ----------------------------------R1
R1   I I4 – I 13 
n.c.
II1; II2
R1
II3; II4
R2
GND
aaa-020082
Fig 32. Resistor test circuit
PDTD113_123_143_114EQA_SER
Product data sheet
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Rev. 1 — 4 February 2016
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PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
8.3 Resistor test conditions
Table 9.
Resistor test conditions
Type number
R1
R2
Test conditions
k
k
II1
II2
II3
II4
PDTD113EQA
[1]
1
1
1.5 mA
1.9 mA
2.2 mA
-
PDTD123EQA
[1]
2.2
2.2
0.7 mA
0.8 mA
0.75 mA
-
PDTD143EQA
[2]
4.7
4.7
1.3 mA
1.5 mA
1.05 mA
1.25 mA
PDTD114EQA
[2]
10
10
0.7 mA
0.8 mA
0.45 mA
0.55 mA
[1]
Uses calculation method A of bias resistor ratio R2/R1
[2]
Uses calculation method B of bias resistor ratio R2/R1
9. Package outline
0.87
0.95
0.75
1
0.95
1.05
2
0.34
0.40
Dimensions in mm
0.17
0.25
0.16
0.24
0.1
3
0.04
max
0.22
0.30
0.245
0.325
0.195
0.275
1.05
1.15
13-03-05
Fig 33. Package outline DFN1010D-3 (SOT1215)
PDTD113_123_143_114EQA_SER
Product data sheet
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Rev. 1 — 4 February 2016
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PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
10. Soldering
Footprint information for reflow soldering of DFN1010D-3 package
SOT1215
1.2
0.45 (2x)
0.3
1.1
0.35 (2x)
0.4
0.25 (2x)
0.75
0.3
0.5
1.5
1.4
0.4
0.5
0.4
0.3
0.5
1.3
0.4
0.3
0.4
0.5
1.3
solder land
solder land plus solder paste
occupied area
solder resist
Dimensions in mm
Issue date
12-11-23
13-03-06
sot1215_fr
Fig 34. Reflow soldering footprint DFN1010D-3 (SOT1215)
PDTD113_123_143_114EQA_SER
Product data sheet
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Rev. 1 — 4 February 2016
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NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
11. Revision history
Table 10.
Revision history
Document ID
Release date
Data sheet status
Change notice Supersedes
PDTD113_123_143_114EQA_SER
v.1
20160104
Product data sheet
-
PDTD113_123_143_114EQA_SER
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 February 2016
-
© NXP Semiconductors N.V. 2016. All rights reserved.
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50 V, 500 mA NPN resistor-equipped transistors
12. Legal information
12.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
12.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PDTD113_123_143_114EQA_SER
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
21 of 23
PDTD113/123/143/114EQA
NXP Semiconductors
50 V, 500 mA NPN resistor-equipped transistors
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
12.4 Trademarks
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PDTD113_123_143_114EQA_SER
Product data sheet
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Rev. 1 — 4 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
22 of 23
NXP Semiconductors
PDTD113/123/143/114EQA
50 V, 500 mA NPN resistor-equipped transistors
14. Contents
1
1.1
1.2
1.3
1.4
2
3
4
4.1
5
6
7
8
8.1
8.2
8.3
9
10
11
12
12.1
12.2
12.3
12.4
13
14
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Binary marking code description. . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . 5
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Test information . . . . . . . . . . . . . . . . . . . . . . . . 15
Quality information . . . . . . . . . . . . . . . . . . . . . 15
Resistor calculation . . . . . . . . . . . . . . . . . . . . 15
Resistor test conditions . . . . . . . . . . . . . . . . . 15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 4 February 2016
Document identifier: PDTD113_123_143_114EQA_SER
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