DATASHEET

SMBus/I2C 8-Channel LED Driver
ISL97677
Features
The ISL97677 is an SMBus/I2C controlled multi-channel
• 8 Channels
LED driver for notebook and monitor LCD backlight
applications with PWM dimming and fault reporting
functions. The ISL97677 is capable of driving typically
96 pieces of 3.4V/50mA LEDs. The ISL97677 has
multiple channels of voltage controlled current sources
with typical currents matching to ±0.7%, which
compensate for the non-uniformity effect of forward
voltages variance in the LED strings. To minimize the
voltage headroom and power loss in the typical
multi-string operation, the ISL97677 features dynamic
headroom control that monitors the highest LED forward
voltage string and uses its feedback signal for output
regulation.
• 4.75V ~ 26V Input
The ISL97677 can operate in multiple modes of
operations. It can be controlled by SMBus/I2C
communications and an external PWM dimming signal
with currents matching of ±1% across all ranges.
The ISL97677 features extensive protection functions
that include string open and short circuit detections, OVP,
and OTP. The fault conditions will be recorded in the
Fault/Status register. There are selectable short-circuit
thresholds and the switching frequency can be
programmed between 500kHz and 1.5MHz.
• 45V Maximum Output
• Drive Typically 96 LEDs (3.4V/50mA each)
• Dimming Controls
- SMBus/I2C 8-Bit PWM Dimming
- SMBus and External PWM DPST Dimming Control
- External PWM Dimming with or without SMBus/I2C
- PWM Dimming range from 0.4% to 100%
• Current Matching ±0.7%
• Protections
- String Open Circuit and Short Circuit Detections,
OVP, and OTP
• Adjustable Dimming Frequency
• Adjustable Switching Frequency
• 32 Ld (5mmx5mm) QFN Package
Applications
• Notebook Displays WLED or RGB LED Backlighting
• LCD Monitor LED Backlighting
ISL97677 is available in the 32 Leads QFN 5mmx5mm
and operate from -40°C to +85°C with input voltage
ranges from 4.75V to 26V.
November 13, 2009
FN6996.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL97677
FOR NEW DESIGNS
NOT RECOMMENDED
PLACEMENT
NO RECOMMENDED RE
Support Center at
contact our Technical
w.intersil.com/tsc
1-888-INTERSIL or ww
ISL97677
Typical Application Circuit
VIN* = 4.75V~26V
L1
10uH/3A
Co
Ci
LX1 20
1uF
1uF
16
VIN
18
VDC
10
VLOGIC
3
3.3nF
14.2k
50k
333k
LX2 21
100pF
OVP
23
3.3nF
2
15k
3x4.7uF
ISL97677
10uF
8x12 = 96 LEDs
Output 45V*, 50mA per string max
D1
806k
22k
SMBCLK/SCL
SMBDAT/SDA CH1
25
CH2
26
CH3
27
CH4
28
CH5
29
CH6
30
CH7
31
CH8
32
4
PWM
17
EN
14
COMP
13
RSET
11
FSW
12
FPWM
6
AGND
7
AGND
8
AGND
9
AGND
5
AGND
15
AGND
PGND
1
PGND
19
* Vin > = 12V for 45V/50mA
Applications
PGND 22
FIGURE 1. ISL97677 TYPICAL APPLICATION DIAGRAM
2
FN6996.1
November 13, 2009
ISL97677
Block Diagram
45V*, 50mA per string
96 (8x12) LEDs
VIN* = 4.75V~26V
VIN
VDC
VLOGIC
O/P Short
Logic Bias
REG2
2x4.7uF/50V
LX
Analog Bias
REG1
OVP
OVP
Fault/Status
Register
fsw
OSC &
RAMP
Comp
fSW
10uH/3A
/EN
Boost SW

Imax
Logic
FET
Drivers
ILIMIT
PGND
pe
Open Ckt, Short Ckt
Detects
Fault/Status Control
COMP
GM
AMP
VSET
SMBCLK/SCL
SMBDAT/SDA
+
-
Temp
Sensor
1
Fault/Status
Register
REF_OVP
REF_VSC
AGND
CH8
REF
GEN
+
-
RSET
CH1
CH2
Highest VF
String Detect
2
+
-
SMBus
Interface
* Vin >=12V for 45V/50mA apps
PWMI
fPWM
Mode
Select &
Dimming
Controller
PWM
Controller
+
-
8
ISL97677
FIGURE 2. ISL97677 BLOCK DIAGRAM
Ordering Information
PART NUMBER
PART MARKING
ISL97677IRZ (Notes 1, 2)
ISL9767 7IRZ
PACKAGE
(Pb-free)
32 Ld 5x5 QFN
PKG.
DWG. #
L32.5x5B
NOTES:
1. Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL97677. For more information on MSL please
see techbrief TB363.
3
FN6996.1
November 13, 2009
ISL97677
Pin Configuration
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
ISL97677
(32 LD 5X5 QFN)
TOP VIEW
32
31
30
29
28
27
26
25
PGND
1
24 NC
SMBCLK/SCL
2
23 OVP
SMBDAT/SDA
3
22 PGND
PWM
4
21 LX
EXPOSED THERMAL PAD
Pin Descriptions
PIN
7
18 VDC
AGND
8
17 EN
10
11
12
13
14
15
16
VIN
9
AGND
AGND
COMP
19 PGND
RSET
6
FPWM
AGND
FSW
20 LX
VLOGIC
5
AGND
AGND
(I = Input, O = Output, S = Supply)
NAME
TYPE
DESCRIPTION
1, 19, 22
PGND
S
Power Ground
2
SMBCLK/SCL
I
SMBus/I2C Serial Clock Input
3
SMBDAT/SDA
I/O
4
PWM
I
PWM Brightness Control
5, 6, 7, 8, 9,
15
AGND
S
Analog Ground
10
VLOGIC
O
Internal 2.5V Logic Bias Regulator. Need Decoupling Capacitor for Regulation
11
FSW
I
When RfSW is 100k, fSW is 500kHz.
When RfSW is 33k, fSW is 1.5MHz
12
FPWM
I
When RFPWM is 333k, FPWM is 200Hz.
When RFPWM is 3.3k, FPWM is 20kHz.
13
RSET
I
Resistor Connection for Setting LED Current
14
COMP
O
Boost compensation
16
VIN
S
Main Power
SMBus/I2C Serial Data Input and Output
17
EN
I
Enable
18
VDC
S
Internal 5V Analog Bias Regulator. Needs Decoupling Capacitor for Regulation
20, 21
LX
O
Boost MOSFET Drain Terminal Switching Node
23
OVP
I
Overvoltage Protection Input as well as Output Voltage FB Monitoring
24
NC
I/O
25 ~ 32
CH1 ~ CH8
I
4
No Connect
LED Driver PWM Dimming Monitoring
FN6996.1
November 13, 2009
ISL97677
Absolute Maximum Ratings
Thermal Information
voltage ratings are all with respect to AGND pin
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 27V
EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 27V
VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.75V
VDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.75V
COMP, RSET, FPWM, FSW . . . . . . . . . . . . . . . . -0.3V to min
. . . . . . . . . . . . . . . . . . . . . . . . . . . . (VDC + 0.3V, 5.75V)
SMBCLK, SMBDAT, PWM . . . . . . . . . . . . . . . -0.3V to 5.75V
CH1 - CH8, LX, OVP . . . . . . . . . . . . . . . . . . . . -0.3V to 45V
PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Thermal Resistance (Typical)
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . -40°C to +85°C
JA (°C/W)
32 Ld QFN (Notes 4, 5) . . . . . . . . . 31
Thermal Characterization (Typical, Note 6)
JC (°C/W)
3
PSIJT (°C/W)
32 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . .
0.2
Maximum Continuous Junction Temperature . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . -65°C to +150°C
Power Dissipation
TA < +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2W
TA < +70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8W
TA < +85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3W
TA < +100°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8W
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. PSIJT is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this
rating then the die junction temperature can be estimated more accurately than the JC and JC thermal resistance ratings.
Electrical Specifications
All specifications below are characterized at TA = -40°C to +85°C; VIN = 12V, /SHUT = 5V,
ISET = 36k, unless otherwise noted. Boldface limits apply over the operating
temperature range, -40°C to +85°C.
5.
PARAMETER
DESCRIPTION
CONDITION
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
GENERAL
VIN
Backlight Supply Voltage
IVIN_SHDN
VIN Shutdown Current
VOUT
Output Voltage
VUVLO
Undervoltage Lockout Threshold
VUVLO_HYS
Undervoltage Lockout Hysteresis
4.75
/SHUT = 0
2.9
26
(Note 8)
V
5
µA
45
V
3.3
V
300
mV
LINEAR REGULATOR
VDC
5V Analog Bias Regulator
VIN > 6V
VDC_DROP
VDC LDO Dropout Voltage
IVDC
4.8
5
5.1
V
IVDC = 30mA
71
100
mV
Active Current
/SHUT = 5V, R = 33k
10
VLOGIC
2.5V Logic Bias Regulator
VIN > 6V
VLOGIC_DROP
VLOGIC LDO Dropout Voltage
IVLOGIC = 30mA
2.3
mA
2.4
2.5
V
31
100
mV
BOOST SWITCHING REGULATOR
SS
Soft-Start
SWILimit
Boost FET Current Limit
rDS(ON)
Internal Boost Switch ON-Resistance
5
16
TA = +25°C to +85°C
3.0
ms
4.7
130
A
m
FN6996.1
November 13, 2009
ISL97677
Electrical Specifications
PARAMETER
Eff_peak
All specifications below are characterized at TA = -40°C to +85°C; VIN = 12V, /SHUT = 5V,
ISET = 36k, unless otherwise noted. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
DESCRIPTION
Peak Efficiency
CONDITION
MIN
(Note 7)
MAX
(Note 7)
UNIT
VIN = 24V, 96LEDs,
20mA each, L = 10µH
with DCR 100m
fSW = 600kHz,
TA = +25°C
92.4
%
VIN = 12V, 96 LEDs,
20mA each, L = 10µH
with DCR 100m
fSW=600kHz,
TA = +25°C
91.5
%
VIN = 6V, 96 LEDs,
20mA each, L = 10µH
with DCR  100m
fSW = 600kHz,
TA = +25°C
81.6
%
VIN = 24V, 80 LEDs,
40mA each, L = 10µH
with DCR  100m
fSW = 600kHz,
TA = +25°C
93.4
%
VIN = 12V, 80 LEDs,
40mA each, L = 10µH
with DCR  100m
fSW = 600kHz,
TA = +25°C
90.7
%
DMAX
Boost Maximum Duty Cycle
fSW = 500kHz
DMIN
Boost Minimum Duty Cycle
fSW = 500kHz
fSW
Boost Switching Frequency
Rfsw = 100k
0.45
Rfsw = 33k
1.35
ILX_leakage
TYP
90
%
10
%
0.5
0.55
MHz
1.5
1.65
MHz
10
µA
+1.1
%
Lx Leakage Current
VLX = 45V, /SHUT = 0V
IMATCH
Channel-to-Channel Current Matching
ILED = 20mA
-1.1
IACC
Absolute Current Accuracy
IRSET = 36k
TA = +25°C
-1.5
+1.5
%
IRSET = 36k
TA = -40°C to +80°C
-2
+2
%
SMBus Register0x0F,
SC[1:0] = 01
2.4
3.6
V
SMBus Register0x0F,
SC[1:0] = 10
3.3
4.6
V
SMBus Register0x0F,
SC[1:0] = 11
4.2
5.6
V
REFERENCE
±0.7
FAULT DETECTION
VSC
Channel Short Circuit Threshold
Vtemp
Over-Temperature Threshold
Vtemp_acc
Over-Temperature Threshold Accuracy
VOVP
Overvoltage Limit on OVP Pin
6
1.18
150
°C
5
°C
1.22
1.24
V
FN6996.1
November 13, 2009
ISL97677
Electrical Specifications
PARAMETER
All specifications below are characterized at TA = -40°C to +85°C; VIN = 12V, /SHUT = 5V,
ISET = 36k, unless otherwise noted. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
DESCRIPTION
CONDITION
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
0.8
V
5.5
V
0.4
V
0.17
V
250
kHz
SMBus INTERFACE (SMBus Mode, 1D_EN = 0)
VIL
Logic Input Low Voltage - SMBCLK/SCL,
SMBDAT/SDA
VIH
Logic Input High Voltage - SMBCLK/SCL,
SMBDAT/SDA
VOL
SMBus Data Line Logic Low Voltage with
1.1kseries resistor from data bus to
SMBDAT pin
1.5
IPULLUP = 350µA
SMBus Data Line Logic Low Voltage without IPULLUP = 4mA
series resistor from data bus to SMBDAT pin
SMBus TIMING SPECIFICATIONS
fSMB
SMBus Clock Frequency
tBUF
Bus Free Time Between Stop and Start
Condition
4.7
µs
tHD:STA
Hold Time After (Repeated) START
Condition. After this Period, the First Clock is
Generated
4.0
µs
tSU:STA
Repeated Start Condition Setup Time
4.7
µs
tSU:STO
Stop Condition Setup Time
4.0
µs
tHD:DAT
Data Hold Time (Note 9)
300
ns
tSU:DAT
Data Setup Time (Note 9)
250
ns
tLOW
Clock Low Period
4.7
µs
tHIGH
Clock High Period
4.0
µs
tF
Clock/Data Fall Time (Note 9)
300
ns
CURRENT SOURCES
VHEADROOM
Dominant Channel Current Source
Headroom at CH Pin
VISET
Voltage at ISET Pin
ILEDmax
Maximum LED Current per Channel
ILED = 50mA
TA = +25°C
1.0
1.18
1.21
V
1.24
50
LED config = 8P10S
with VF = 3.4V and
VIN = 11V
V
mA
PWM GENERATOR
FPWM
Generated PWM Frequency
RFPWM = 330k
180
200
220
Hz
RFPWM = 3.3k
18
20
22
kHz
100
%
1.21
1.24
V
20k
Hz
1.21
1.25
V
Dimming Range
PWM Dimming Duty Cycle Limits (Note 9)
fPWM  30kHz
0.4
VFSW
FSW Voltage
RFSW = 33k
1.18
RFPWM = 3.3k
1.18
FPWMI
PWMI Input Frequency Range (Note 9)
VFPWM
VFPWM Voltage
200
NOTES:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
8. At maximum VIN of 26V, minimum VOUT is 28V. Minimum VOUT can be lower at lower VIN
9. Limits established by characterization and are not production tested.
7
FN6996.1
November 13, 2009
ISL97677
Typical Performance Curves
100
100
50mA
8P11S
fSW = 600kHz
95
0°C
90
+85°C
85
EFFICIENCY (%)
EFFICIENCY (%)
95
-40°C
+25°C
80
80
70
70
10
15
20
25
30
+85°C
85
75
5
-40°C
0°C
90
75
0
20mA
8P11S
fSW = 600kHz
+25°C
0
5
10
VIN (V)
25
95
8P10S
30
50mA
8P11S
94
93
12V/50mA
24V/50mA
92
24V
91
90
89
88
87
12V
86
85
0
10
20
30
ILED (mA)
40
0.8
1.0
20mA - 8P12S
50mA - 8P11S
12V/20mA
0.2
0.0
-0.2
-0.4
-0.6
12V/50mA
-0.8
-1.0
1
2
3
4
5
CHANNEL
6
7
FIGURE 7. CHANNEL-TO-CHANNEL CURRENT
MATCHING EXAMPLE
8
1.6k
50mA
8P11
0.8
0.6
0.4
600
800
1k
1.2k
1.4k
SWITCHING FREQUENCY (Hz)
FIGURE 6. EFFICIENCY vs SWITCHING FREQUENCY
CURRENT MATCHING (%)
1.0
84
400
50
FIGURE 5. EFFICIENCY vs ILED
CURRENT MATCHING (%)
20
FIGURE 4. EFFICIENCY vs VIN vs TEMPERATURE AT
20mA
EFFICIENCY (%)
EFFICIENCY (%)
FIGURE 3. EFFICIENCY vs VIN vs TEMPERATURE AT
50mA
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
15
VIN (V)
8
0.6
0°C
0.4
0.2
0.0
+25°C
-0.2
+85°C
-0.4
-0.6
-0.8
-1.0
-40°C
0
5
10
15
VIN (V)
20
25
30
FIGURE 8. CURRENT MATCHING vs VIN vs
TEMPERATURE
FN6996.1
November 13, 2009
ISL97677
Typical Performance Curves (Continued)
2.0
2.0
20mA - 8P12S
50mA - 8P11S
1.6
12V/50mA
1.4
ILED (mA)
1.8
CHANNEL VOLTAGE (V)
1.8
24V/50mA
1.2
1.0
0.8
5V/20mA
0.6
0.4
24V/20mA
0.2
FIGURE 9. CURRENT LINEARITY vs LOW LEVEL PWM
DIMMING DUTY CYCLE
1.0
0.8
0.6
0.90
0.8
0.85
0.7
+85°C
0.70
0°C
0.65
20
25
30
FIGURE 11. VHEADROOM vs VIN vs TEMPERATURE AT
50mA
10
4
5
CHANNEL
+25°C
0.3
0.1
15
VIN (V)
3
6
7
8
+85°C
0.4
0.2
10
2
0.5
0.55
5
1
0.6
0.60
0.50
0
HEADROOM CONTROL CHANNEL
20mA
8P11S
0.9
0.75
12V/20mA
0.4
FIGURE 10. TYPICAL CHANNEL VOLTAGE EXAMPLE
+25°C
0.80
0.0
0
5
10
0°C
15
VIN (V)
20
25
30
FIGURE 12. VHEADROOM vs VIN vs TEMPERATURE AT
20mA
/SHUT = HIGH
PWM DUTY CYCLE = 0%
9
LX (20V/DIV)
8
IIN (mA)
1.2
1.0
50mA
8P11S
20mA - 8P12S
50mA - 8P11S
1.4
0.0
VHEADROOM (V)
VHEADROOM (V)
0.95
1.6
0.2
0.0
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
PWM DIMMING DUTY CYCLE (%)
1.00
12V/50mA
7
+85°C
6
VO (100mV/DIV)
5
4
-40°C
3
ILED (20mA/DIV)
2
1
0
0
5
10
15
20
25
30
VIN (V)
FIGURE 13. QUIESCENT CURRENT vs VIN vs
TEMPERATURE WITH /SHUT ENABLE
9
FIGURE 14. VOUT RIPPLE VOLTAGE
FN6996.1
November 13, 2009
ISL97677
Typical Performance Curves (Continued)
VO (20V/DIV)
VO (20V/DIV)
EN (5V/DIV)
EN (5V/DIV)
IIN (1A/DIV)
IIN (1A/DIV)
ILED (50mA/DIV)
FIGURE 15. IN-RUSH CURRENT and LED CURRENT AT
VIN = 12V
VIN (10V/DIV)
ILED (50mA/DIV)
FIGURE 16. IN-RUSH CURRENT AND LED CURRENT
AT VIN = 26V
VIN (10V/DIV)
IIN (500mA/DIV)
IIN (500mA/DIV)
ILED (50mA/DIV)
FIGURE 17. LINE REGULATION WITH VIN CHANGES
FROM 12V TO 26V DISABLE PROFILE
ILED (50mA/DIV)
FIGURE 18. LINE REGULATION WITH VIN CHANGES
FROM 26V TO 12V
VO (1V/DIV)
VO (1V/DIV)
ILED (20mA/DIV)
ILED (20mA/DIV)
FIGURE 19. LOAD REGULATION WITH ILED CHANGES
FROM 0.4% TO 100% PWM DIMMING
10
FIGURE 20. LOAD REGULATION WITH ILED CHANGES
FROM 100% TO 0.4% PWM DIMMING
FN6996.1
November 13, 2009
ISL97677
Typical Performance Curves (Continued)
VO (1V/DIV)
VO (500mV/DIV)
ILED (20mA/DIV)
ILED (20mA/DIV)
FIGURE 21. LOAD REGULATION WITH ILED CHANGES
FROM 0% TO 100% PWM DIMMING
FIGURE 22. LOAD REGULATION WITH ILED CHANGES
FROM 100% to 0% PWM DIMMING
VO (20V/DIV)
EN (5V/DIV)
IIN (1A/DIV)
ILED (50mA/DIV)
FIGURE 23. DISABLE PROFILE
Theory of Operation
PWM Boost Converter
The current mode PWM boost converter produces the
minimal voltage needed to enable the LED string with the
highest forward voltage drop to run at the programmed
current. The ISL97677 employs current mode control
boost architecture that has a fast current sense loop and
a slow voltage feedback loop. Such architecture achieves
a fast transient response that is essential for the
notebook backlight application where the power can be
several Li-ion cell batteries or instantly change to an
AC/DC adapter without rendering a noticeable visual
nuisance. The number of LEDs that can be driven by
ISL97677 depends on the type of LED chosen in the
application. The ISL97677 is capable of boosting up to
45V and drive 8 channels of LEDs at maximum of 45mA
per channel.
11
Current Matching and Current Accuracy
Each channel of the LED current is regulated by the
current source circuit, as shown in Figure 24.
The LED peak current is set by translating the RSET
current to the output with a scaling factor of 707.9/RSET.
The source terminals of the current source MOSFETs are
designed to run at 500mV to optimize power loss vs
accuracy requirements. The sources of errors of the
channel-to-channel current matching come from the
op amps offset, internal layout, reference, and current
source resistors. These parameters are optimized for
current matching and absolute current accuracy.
However, the absolute accuracy is additionally
determined by the external RSET. A 0.1% tolerance
resistor is recommended.
FN6996.1
November 13, 2009
ISL97677
The ratio of the OVP capacitors should be the inverse of
the OVP resistors. For example, if RUPPER/RLOWER =
33/1, then CUPPER/CLOWER=1/33 with CUPPER = 100pF
and CLOWER = 3.3nF.
.
Dimming Controls
The ISL97677 allows two ways of controlling the LED
current, and therefore, the brightness. They are:
+
-
REF
1. DC current adjustment
+
-
2. PWM chopping of the LED current defined in Step 1.
There are various ways to achieve DC or PWM current
control, which will be described in the following.
RSET
+
-
In any dimming controls, the EN pin must be high. EN
is a high voltage pin that can be applied with a digital
signal or tied directly to VIN for enable function.
PWM DIMMING
FIGURE 24. SIMPLIFIED CURRENT SOURCE CIRCUIT
Dynamic Headroom Control
The ISL97677 features a proprietary Dynamic Headroom
Control circuit that detects the highest forward voltage
string or effectively the lowest voltage from any of the
CH pins. When this lowest IIN voltage is lower than the
short circuit threshold, VSC, such voltage will be used as
the feedback signal for the boost regulator. The boost
makes the output to the correct level such that the
lowest CH pin is at the target headroom voltage. Since all
LED strings are connected to the same output voltage,
the other CH pins will have a higher voltage, but the
regulated current source circuit on each channel will
ensure that each channel has the same programmed
current. The output voltage will regulate cycle by cycle
and is always referenced to the highest forward voltage
string in the architecture.
OVP and VOUT Requirement
The Overvoltage Protection (OVP) pin has a function of
setting the overvoltage trip level as well as limiting the
VOUT regulation range.
The ISL97677 OVP threshold is set by RUPPER and
RLOWER as shown in Equation 1:
V OUT_OVP = 1.21V   R UPPER + R LOWER   R LOWER
The initial brightness should be set by choosing an
appropriate value for RSET. This should be chosen to fix
the maximum possible LED current:
707.9
I LEDmax = --------------R SET
(EQ. 2)
Alternatively, the RSET can be replaced by digital
potentiometer for adjustable current. On the other
hand, the current accuracy is designed when RSET is
set at 20m to 40mA.
PWM CONTROL
The ISL97677 also provides PWM dimming by PWM
chopping of the current in the LEDs for all 8 channels
to provide an average LED current. During the On
periods, the LED current will be defined by the value of
RSET, as described in Equation 1.
PWM Dimming Frequency Adjustment
The dimming frequencies of all modes are set by an
external resistor at the FPWM pin as shown in
Equation 3:
7
6.66 10
f PWM = -----------------------RPWM
(EQ. 3)
(EQ. 1)
VOUT can only regulate between 64% and 100% of the
VOUT_OVP such that:
Allowable VOUT = 64% to 100% of VOUT_OVP
For example, if 10 LEDs are used with the worst case
VOUT of 35V. If R1 and R2 are chosen such that the OVP
level is set at 40V, then the VOUT is allowed to operate
between 25.6V and 40V. If the requirement is changed to
a 6 LEDs 21V VOUT application, then the OVP level must
be reduced and users should follow VOUT = (64%
~100%)OVP requirement. Otherwise, the headroom
control will be disturbed such that the channel voltage
can be much higher than expected and sometimes it can
prevents the driver from operating properly.
12
MAXIMUM DC CURRENT SETTING
where fPWM is the desirable PWM dimming frequency
and RFPWM is the setting resistor.
External PWM Dimming
The ISL97677 can operate as basic PWM dimming LED driver
with or without the need of SMBus/I2C interface. To do so,
users need to set EN = high and SMBCLK/SCL = grounded or
floating, SMBDAT/SDA = grounded or floating. The EN is a
high voltage pin that can be applied with a digital I/O signal or
tie to VIN. The PWM output will follow the PWM input and the
dimming frequency will be set by RPWM.
FN6996.1
November 13, 2009
ISL97677
Switching Frequency
The boost switching frequency can be adjusted by a
resistor as shown in Equation 4:
10
 5 10 
f SW = ----------------------R OSC
(EQ. 4)
where fSW is the desirable boost switching frequency
and ROSC is the setting resistor.
5V and 2.3V Low Dropout Regulators
A 5V LDO regulator is present at the VDC pin to develop
the necessary low voltage supply, which is used by the
chips internal control circuitry. Because VDC is an LDO
pin, it requires a bypass capacitor of 1µF or more for the
regulation. The VDC pin can be used for a coarse
regulator or reference but do not pull more than few mA
from it.
Similarly, a 2.3V LDO regulator is present at the
VLOGIC pin to develop the necessary low voltage supply
for the chip’s internal logic control circuitry. A 1µF
bypass capacitor or more is needed for regulation. The
VLOGIC pin can be used as a coarse regulator or
reference but do not pull more than few mA from it.
Soft-Start
The ISL97677 uses a digital soft-start where the boost
current limit is stepped up in 8 steps. The initial current
limit level is set to one ninth of the full current limit, with
subsequent steps increasing this by a ninth every 2ms.
In the event that no LEDs have been conducting during
the interval since the last step (for example, if the LEDs
are running at low duty cycle at low PWM frequency)
then the step will be delayed until the LEDs are
conducting. If the LEDs are disabled and re-enabled
again then soft start will be restarted when the LEDs are
enabled.
Fault Protection and Monitoring
The ISL97677 features extensive protection functions to
cover all the perceivable failure conditions. The failure
mode of a LED can be either open circuit or as a short.
The behavior of an open circuited LED can additionally
take the form of either infinite resistance or, for some
LEDs, a zener diode, which is integrated into the device
in parallel with the now opened LED.
For basic LEDs (which do not have built-in zener diodes),
an open circuit failure of an LED will only result in the loss
of one channel of LEDs without affecting other channels.
Similarly, a short circuit condition on a channel that
results in that channel being turned off does not affect
other channels unless a similar fault is occurring. All LED
faults are reported via the SMBus interface to Register
0x02 (Fault/Status register).
Due to the lag in boost response to any load change at its
output, certain transient events (such as significant step
changes in LED duty cycle) can transiently look like LED
fault modes. The ISL97677 uses feedback from the LEDs
to determine when it is in a stable operating region and
13
prevents apparent faults during these transient events
from allowing any of the LED strings to fault out. See
Table 1 for more details.
Short Circuit Protection (SCP)
The short circuit detection circuit monitors the voltage on
each channel and disables faulty channels which are
detected above the programmed short circuit threshold.
There are three selectable levels of short circuit threshold
(3V, 4V, and 5V) that can be programmed through the
Configuration Register 0x0F. When an LED becomes
shorted, the action taken is described in Table 1. The
default short circuit threshold is 4V. The detection of this
failure mode can be disabled by SMBus interface via
Register 0x0F.
Open Circuit Protection (OCP)
When one of the LEDs becomes open circuit, it can
behave as either an infinite resistance or a gradually
increasing finite resistance. The ISL97677 monitors the
current in each channel such that any string which
reaches the intended output current is considered
“good”. Should the current subsequently fall below the
target, the channel will be considered an “open circuit”.
Furthermore, should the boost output of the ISL97677
reach the OVP limit or should the lower over-temperature
threshold be reached, all channels which are not “good”
will immediately be considered as “open circuit”.
Detection of an “open circuit” channel will result in a
time-out before disabling of the affected channel.
Some users employ some special types of LEDs that
have zener diode structure in parallel with the LED for
ESD enhancement, thus enabling open circuit operation.
When this type of LED goes open circuit, the effect is as
if the LED forward voltage has increased, but no light
will be emitted. Any affected string will not be disabled,
unless the failure results in the boost OVP limit being
reached, allowing all other LEDs in the string to remain
functional. Care should be taken in this case that the
boost OVP limit and SCP limit are set properly, so as to
make sure that multiple failures on one string do not
cause all other good channels to be faulted out. This is
due to the increased forward voltage of the faulty
channel making all other channel look as if they have
LED shorts. See Table 1 for details for responses to fault
conditions.
Overvoltage Protection (OVP)
The integrated OVP circuit monitors the output voltage
and keeps the voltage at a safe level. The OVP threshold
is set as shown in Equation 5:
OVP = 1.21V   RUPPER + R LOWER   R LOWER
(EQ. 5)
These resistors should be large to minimize the power
loss. For example, a 1Mk RUPPER and 30k RLOWER
sets OVP to 41.2V. Large OVP resistors also allow COUT
discharges slowly during the PWM Off time. Parallel
capacitors should be placed across the OVP resistors
such that RUPPER/RLOWER = CLOWER/CUPPER. Using a
CUPPER value of at least 30pF is recommended. These
FN6996.1
November 13, 2009
ISL97677
capacitors reduce the AC impedance of the OVP node,
which is important when using high value resistors.
upper threshold will also set the thermal fault bit of the
Fault/Status register 0x02. Unless disabled via the /SHUT
pin, the device stays in an active state throughout,
allowing the external processor to interrogate the fault
condition.
Undervoltage Lockout
If the input voltage falls below the UVLO level of 2.8V, the
device will stop switching and be reset. Operation will
restart only if the device control interface re-enables it
once the input voltage is back in the normal operating
range. Also all digital settings will be reset to their default
states.
For the extensive fault protection conditions, please refer
to Figure 25 and Table 1 for details.
Shutdown
When the EN pin is low the entire chip is shut down to
give close to zero shutdown current. The digital
interfaces will not be active during this time.
Over-Temperature Protection (OTP)
The ISL97677 includes two over-temperature thresholds.
The lower threshold is set to +130°C. When this
threshold is reached, any channel which is outputting
current at a level significantly below the regulation target
will be treated as “open circuit” and disabled after a
time-out period. The intention of the lower threshold is to
allow bad channels to be isolated and disabled before
they cause enough power dissipation (as a result of other
channels having large voltages across them) to hit the
upper temperature threshold.
The upper threshold is set to +150°C. Each time this is
reached, the boost will stop switching and the output
current sources will be switched off and stay off until the
control interface disables and re-enables it. Hitting of the
LX
VIN
FAULT
DRIVER
IMAX ILIMIT
LOGIC
VOUT
LX
O/P
SHORT
OVP
FET
DRIVER
CH1
VSC
CH8
VSET/2
REG
THRM
SHDN
REF
OTP
T2
TEMP
SENSOR
T1
VSET
+
Q1 VSET
PWM1/OC1/SC1
FAULT/
STATUS
REGISTER
SMBUS
CONTROL
LOGIC
+
Q8
-
-
PWM8/OC8/SC8
DC CURRENT
FIGURE 25. SIMPLIFIED FAULT PROTECTIONS
14
FN6996.1
November 13, 2009
ISL97677
TABLE 1. PROTECTIONS TABLE
DETECTION MODE
FAILED CHANNEL ACTION
CASE
FAILURE MODE
1
CH1 Short Circuit
Upper
CH1 ON and burns power
Over-Temperature
Protection limit (OTP)
not triggered and
VIIN0 < VSC
CH2 through CH8 Normal
Highest VF of
CH2 through
CH8
2
CH1 Short Circuit
Upper OTP triggered
but VIN1 < VSC
CH1 goes off
Same as CH1
Highest VF of
CH2 through
CH8
3
CH1 Short Circuit
Upper OTP not
triggered but VIIN1 >
VSC
CH1 disabled after 6 PWM
cycles time-out.
Highest VF of
If 3 channels are already
shut down, all channels will CH2 through
CH8
be shut down. Otherwise
CH2-8 will remain as normal
4
CH1 Open Circuit
with infinite
resistance
Upper OTP not
triggered and VIIN1
< VSC
VOUT will ramp to OVP. CH1 will CH2 through CH8 Normal
time-out after 6 PWM cycles
and switch off. VOUT will drop
to normal level.
5
CH1 LED Open
Circuit but has
paralleled Zener
Upper OTP not
CH1 remains ON and has
triggered and VIIN1 < highest VF, thus VOUT
VSC
increases
CH2 through CH8 ON, Q2
through Q8 burn power
VF of CH1
6
CH1 LED Open
Circuit but has
paralleled Zener
Upper OTP triggered
but VIIN1 < VSC
Same as CH1
VF of CH1
7
CH1 LED Open
Circuit but has
paralleled Zener
CH1 OFF
Upper OTP not
triggered but VIIN1 >
VSC
CH2 through CH8 Normal
Highest VF of
CH2 through
CH8
CH1 remains ON and has
Upper OTP not
triggered but VIINx > highest VF, thus VOUT
VSC
increases.
VOUT increases then CH-X
switches OFF. This is an
unwanted shut off and can
be prevented by setting OVP
and/or VSC at an
appropriate level.
VF of CH1
CH1 goes off
GOOD CHANNELS ACTION
VOUT
REGULATED
BY
Highest VF of
CH2 through
CH8
8
Channel-toChannel VF too
high
Lower OTP triggered
but VIINx < VSC
Any channel at below the target current will fault out after
6 PWM cycles.
Remaining channels driven with normal current.
Highest VF of
CH1 through
CH8
9
Channel-toChannel VF too
high
Upper OTP triggered
but VIINx < VSC
All channels switched off
Highest VF of
CH1 through
CH8
10
Output LED string
voltage too high
VOUT > VOVP
Driven with normal current. Any channel that is below the
target current will time-out after 6 PWM cycles.
Highest VF of
CH1 through
CH8
11
VOUT/LX shorted
to GND
LX will not switch
15
FN6996.1
November 13, 2009
ISL97677
SMBCLK
tF
tR
tLOW
VIH
VIL
tHD:DAT
tHD:STA
tHIGH
tSU:DAT
tSU:STA
tSU:STO
SMBDAT
VIH
VIL
P
tBUF
S
P
S
NOTES:
SMBus Description
S = Start condition
P = Stop condition
A = Acknowledge
A = Not acknowledge
R/W = Read enable at high; Write enable at low
FIGURE 26. SMBUS INTERFACE
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS
W
A
COMMAND CODE
A
DATA BYTE
A
P
Master to Slave
Slave to Master
FIGURE 27. WRITE BYTE PROTOCOL
1
7
1
1
8
1
1
8
1
1
8
1
1
S
SLAVE
ADDRESS
W
A
COMMAND
CODE
A
S
SLAVE ADDRESS
R
A
DATA BYTE
A
P
Master to Slave
Slave to Master
FIGURE 28. READ BYTE PROTOCOL
16
FN6996.1
November 13, 2009
ISL97677
The backlight controller may sense the state of the pins
at POR or during normal operation—the pins will not
change state while the device is in operation.
MSB
Read Byte
0
As shown in the Figure 28, the four byte long Read Byte
protocol starts out with the slave address followed by
the “command code” which translates to the “register
index.” Subsequently, the bus direction turns around
with the rebroadcast of the slave address with bit 0
indicating a read (“R”) cycle. The fourth byte contains
the data being returned by the backlight controller. That
byte value in the data byte reflects the value of the
register being queried at the “command code” index.
Note the bus directions, which are highlighted by the
shaded label that is used on cycles during which the
slaved backlight controller “owns” or “drives” the Data
line. All other cycles are driven by the “host master.”
Slave Device Address
The slave address contains 7 MSB plus one LSB as R/W
bit, but these 8 bits are usually called Slave Address
bytes. As shown in Figure 29, the high nibble of the slave
address byte is 0x5 or 0101b to denote the “backlight
controller class.” Bit 3 in the lower nibble of the slave
address byte is 1. Bit 0 is always the R/W bit, as specified
by the SMBus protocol. Note: In this document, the
device address will always be expressed as a full 8-bit
address instead of the shorter 7-bit address typically
used in other backlight controller specifications to avoid
LSB
1
0
1
DEVICE
IDENTIFIER
1
0
0
DEVICE
ADDRESS
R/W
BI
T
The Write Byte protocol is only three bytes long. The first
byte starts with the slave address followed by the
“command code,” which translates to the “register index”
being written. The third byte contains the data byte that
must be written into the register selected by the
“command code”. A shaded label is used on cycles during
which the slaved backlight controller “owns” or “drives”
the Data line. All other cycles are driven by the “host
master.”
confusion. Therefore, if the device is in the write mode
where bit 0 is 0, the slave address byte is 0x58 or
01011000b. If the device is in the read mode where bit 0
is 1, the slave address byte is 0x59 or 01011001b.
RE
AD
/W
RI
TE
Write Byte
FIGURE 29. SLAVE ADDRESS BYTE DEFINITION
SMBus Register Definitions
The backlight controller registers are Byte wide and
accessible via the SMBus Read/Write Byte protocols.
Their bit assignments are provided in the following
sections with reserved bits containing a default value
of “0”.
TABLE 2A. REGISTER LISTING
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DEFAULT
VALUE
SMBUS
PROTOCOL
BRT7
BRT6
BRT5
BRT4
BRT3
BRT2
BRT1
BRT0
0xFF
Read and Write
PWM_SEL
BL_CTL
0x00
Read and Write
FAULT
0x00
Read Only
REV0
0xC8
Read Only
0x00
PWM Brightness
Control Register
0x01
Device Control
Register
Reserved
Reserved
Reserved
Reserved
Reserved
PWM_MD
0x02
Fault/Status
Register
Reserved
Reserved
2_CH_SD
1_CH_S
D
BL_STAT
OV_CURR THRM_SHDN
0x03
Identification
Register
LED
PANEL
MFG3
MFG2
MFG1
MFG0
17
REV2
REV1
FN6996.1
November 13, 2009
ISL97677
TABLE 2B. DATA BIT DESCRIPTIONS
ADDRESS
REGISTER
DATA BIT DESCRIPTIONS
0x00
PWM Brightness Control
Register
BRT[7..0] = 256 steps of DPWM duty cycle brightness control
0x01
Device Control Register
PWM_MD = PWM mode select bit (1 = absolute brightness, 0 = % change),
default = 0
PWM_SEL = Brightness control select bit (1 = control by PWMI, 0 = control by
SMBus), default = 0
BL_CTL = BL On/Off (1 = On, 0 = Off), default = 0
PWM_MD PWM_SEL
MODE
X
1
PWMI Mode
1
0
SMBus Mode
0
0
SMBus and PWMI mode with
DPST
0x02
Fault/Status Register
2_CH_SD = Two LED output channels are shutdown (1 = shutdown, 0 = OK)
1_CH_SD = One LED output channel is shutdown (1 = shutdown, 0 = OK)
BL_STAT = BL status (1 = BL On, 0 = BL Off)
OV_CURR = Input overcurrent (1 = Overcurrent condition, 0 = Current OK)
THRM_SHDN = Thermal Shutdown (1 = Thermal fault, 0 = Thermal OK)
FAULT = Fault occurred (Logic “OR” of all of the fault conditions)
0x03
Identification Register
MFG[3..0] = Manufacturer ID (16 vendors available. Intersil is vendor ID 9)
REV[2..0] = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins)
PWM Brightness Control Register (0x00)
The Brightness control resolution has 256 steps of PWM
duty cycle adjustment. The bit assignment is shown in
Tables 2A and 2B. All of the bits in this Brightness Control
Register can be read or write. Step 0 corresponds to the
minimum step where the current is less than 10µA. Steps
1 to 255 represent the linear steps between 0.39% and
100% duty cycle with approximately 0.39% duty cycle
adjustment per step.
• An SMBus Write Byte cycle to Register 0x00 sets the
PWM brightness level only if the backlight controller
is in SMBus mode (see Table 3 “Operating Modes
selected by Device Control Register Bits 1 and 2”).
• An SMBus Read Byte cycle to Register 0x00 returns
the programmed PWM brightness level, regardless of
the value of PWM_SEL.
• An SMBus setting of 0xFF for Register 0x00 sets the
backlight controller to the maximum brightness.
• An SMBus setting of 0x00 for Register 0x00 sets the
backlight controller to the minimum brightness
output in which the LED current is guaranteed to be
less than 10µA.
• Default value for Register 0x00 is 0xFF.
Device Control Register (0x01)
This register has 2 bits that control the operating mode
of the backlight controller and a single bit that controls
the BL ON/OFF state. The remaining bits are reserved.
The bit assignment is shown in Tables 2A and 2B. All
other bits in the Device Control Register will read as low
18
unless otherwise written. Bits 7 and 6 are not
implemented and will always read low.
TABLE 3. OPERATING MODES SELECTED BY DEVICE
CONTROL REGISTER BITS 1 AND 2
PWM_MD PWM_SEL
MODE
X
1
PWMI Mode
1
0
SMBus Mode
0
0
SMBus and PWMI Mode with DPST
The PWM_SEL bit determines whether the SMBus or
PWMI input should drive the output brightness in terms
of PWM dimming. When PWM_SEL bit is 1, the PWMI
drives the output brightness regardless of what the
PWM_MD is.
When the PWM_SEL bit is 0, the PWM_MD bit selects the
manner in which the PWM dimming is to be interpreted;
when this bit is 1, the PWM dimming is based on the
SMBus brightness setting. When this bit is 0, the PWM
dimming reflects a percentage change in the current
brightness programmed in the SMBus Register 0x00, i.e.
DPST (Display Power Saving Technology) mode, as
shown in Equation 6:
(EQ. 6)
DPST Brightness = Cbt  PWMI
Where:
Cbt = Current brightness setting from SMBus Register
0x00 without influence from the PWMI
PWMI = is the percent duty cycle of the PWMI
FN6996.1
November 13, 2009
ISL97677
For example, the Cbt = 50% duty cycle programmed in
the SMBus Register 0x00 and the PWM frequency is
tuned to be 200Hz with an appropriate capacitor at the
FPWM pin. On the other hand, PWMI is fed with a 1kHz
30% high PWM signal. When PWM_SEL = 0 and
PWM_MD = 0, the device is in DPST operation where
DPST brightness = 15% PWM dimming at 200Hz.
• All reserved bits return a “0” when read.
• All reserved bits have no functional effect when
written.
• All defined control bits return their current, latched
value when read.
• A value of 1 written to BL_CTL turns on the BL in 4ms
or less after the write cycle completes. The BL is
deemed to be on when Bit 3 BL_STAT of Register 0x02
is 1 and Register 0x09 is not 0. See Tables 2A and 2B.
• A value of 0 written to BL_CTL immediately turns off the
BL. The BL is deemed to be off when Bit 3 BL_STAT of
Register 0x02 is 0 and Register 0x09 is 0. See Tables 2A
and 2B.
• **Note that the behavior of Register 0x00
(Brightness Control Register) is affected by certain
combinations of the control bits, as shown in Table 3
“Operating Modes Selected by Device Control
Register Bits 1 and 2.”
• When an SMBus mode is selected, Register 0x00
reflects the last value written to it. But, when any
non-SMBus mode is selected, Register 0x00 reflects
the current brightness value based on the current
mode of operation, with the exception of SMBus
mode with DPST, where PWM_MD = 0 and
PWM_SEL = 0.
read-only, with the exception of bit 0, which can be
cleared by writing to it.
• A Read Byte cycle to Register 0x02 indicates the
current BL on/off status in BL_STAT (1 if the BL is on,
0 if the BL is off).
• A Read Byte cycles to Register 0x2 also returns
FAULT as the logical OR of THRM_SHDN, OV_CURR,
2_CH_SD, and 1_CH_SD should these events occur.
• 1_CH_SD returns a 1 if one or more channels have
faulted out.
• 2_CH_SD returns a 1 if two or more channels have
faulted out.
• A fault will not be reported in the event that the BL is
commanded on and then immediately off by the
system.
• When FAULT is set to 1, it will remain at 1 even if the
signal which sets it goes away. FAULT will be cleared
when the BL_CTL bit of the Device Control Register is
toggled or when written low. At that time, if the fault
condition is still present or reoccurs, FAULT will be
set to 1 again. BL_STAT will not cause FAULT to be
set.
• The controller will not indicate a fault if the VBL+
goes away, whether or not the LEDs were on at the
time of the power loss. This can occur if there is
some hang condition that causes the user to force
the system off by holding the power button down
for 4s.
• The default value for Register 0x02 is 0x00.
Identification Register (0x03)
• The default value for Register 0x01 is 0x00.
The ID register contains 3-bit fields to denote the LED
driver (always set to 1), manufacturer and the silicon
revision of the controller IC. The bit field widths allow up
to 16 vendors with up to 8 silicon revisions each. In order
to keep the number of silicon revisions low, the revision
field will not be updated unless the part will make it out
to the user’s factory. Thus, if during the engineering
development process, 3 silicon spins were needed, the
next available revision ID would be used for all 3 spins
until that same ID made it to the factory. Except Bit 7,
which has to be 1, all of the bits in this register are
read-only.
Fault/Status Register (0x02)
• Vendor ID 9 represents Intersil Corporation.
This register has 6 status bits that allow monitoring of
the backlight controller’s operating state. Bit 0 is a logical
“OR” of all fault codes to simplify error detection. Not all
of the bits in this register are fault related (Bit 3 is a
simple BL status indicator). The remaining bits are
reserved and return a “0” when read and ignore the bit
value when written. All of the bits in this register are
• The default value for Register 0x03 is 0xC8.
• When SMBus mode with DPST is selected, Register
0x00 reflects the last value written to it from SMBus.
• When a write to Register 0x01 (Device Control
Register) causes the backlight controller to transition
to an SMBus mode, the brightness of the BL does not
change. On the other hand, when a write to Register
0x01causes the backlight controller to transition to a
non-SMBus mode, the brightness of the BL changes
as appropriate for the new mode.
19
The initial value of REV shall be 0. Subsequent values of
REV will increment by 1.
Components Selections
According to the inductor Voltage-Second Balance
principle, the change of inductor current during the
switching regulator On-time is equal to the change of
inductor current during the switching regulator Off-time.
FN6996.1
November 13, 2009
ISL97677
Since the voltage across an inductor is as shown in
Equation 7:
(EQ. 7)
V L = L  I L  t
Inductor
and IL @ On = IL @ Off, therefore:
 V I – 0   L  D  tS =  VO – VD – VI   L   1 – D   tS
(EQ. 8)
where D is the switching duty cycle defined by the
turn-on time over the switching periods. VD is Schottky
diode forward voltage that can be neglected for
approximation.
Rearranging the terms without accounting for VD gives
the boost ratio and duty cycle respectively as Equations 9
and 10:
VO  VI = 1   1 – D 
(EQ. 9)
D =  VO – VI   VO
(EQ. 10)
Input Capacitor
Switching regulators require input capacitors to deliver
peak charging current and to reduce the impedance of
the input supply. This reduces interaction between the
regulator and input supply, thereby improving system
stability. The high switching frequency of the loop causes
almost all ripple current to flow in the input capacitor,
which must be rated accordingly.
A capacitor with low internal series resistance should be
chosen to minimize heating effects and improve system
efficiency, such as X5R or X7R ceramic capacitors, which
offer small size and a lower value of temperature and
voltage coefficient compared to other ceramic capacitors.
REGISTER 0x00
BRT7
It is recommended that an input capacitor of at least
10µF be used. Ensure the voltage rating of the input
capacitor is suitable to handle the full supply range.
BRT6
The selection of the inductor should be based on its
maximum and saturation current (ISAT) characteristics,
power dissipation (DCR), EMI susceptibility (shielded vs
unshielded), and size. Inductor type and value influence
many key parameters, including ripple current, current
limit, efficiency, transient performance and stability.
The inductor’s maximum current capability must be
adequate enough to handle the peak current at the worst
case condition. Additionally if an inductor core is chosen
with too low a current rating, saturation in the core will
cause the effective inductor value to fall, leading to an
increase in peak to average current level, poor efficiency
and overheating in the core. The series resistance, DCR,
within the inductor causes conduction loss and heat
dissipation. A shielded inductor is usually more suitable
for EMI susceptible applications, such as LED
backlighting.
The peak current can be derived from the voltage across
the inductor during the Off-period, as expressed in
Equation 11:
IL peak =  V O  I O    85%  V I  + 1  2  V I   V O – V I    L  V O  f SW 
(EQ. 11)
The choice of 85% is just an average term for the
efficiency approximation. The first term is the average
current, which is inversely proportional to the input
voltage. The second term is the inductor current change,
which is inversely proportional to L and fSW. As a result,
for a given switching.
PWM BRIGHTNESS CONTROL
REGISTER
BRT5
BRT4
BRT3
BRT2
BRT1
BRT0
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
BIT ASSIGNMENT
BRT[7..0]
BIT FIELD DEFINITIONS
= 256 steps of PWM brightness levels
FIGURE 30. DESCRIPTIONS OF BRIGHTNESS CONTROL REGISTER
20
FN6996.1
November 13, 2009
ISL97677
REGISTER 0x01
DEVICE CONTROL REGISTER
RESERVED
RESERVED RESERVED RESERVED
RESERVED
PWM_MD PWM_SEL
Bit 7 (R/W)
Bit 6 (R/W)
Bit 3 (R/W)
Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
Bit 5 (R/W)
BIT ASSIGNMENT
Bit 4 (R/W)
BL_CTL
BIT FIELD DEFINITIONS
PWM_MD
= PWM mode select bit (1 = absolute
brightness, 0 = % change) default = 0
PWM_SEL
= Brightness control select bit (1 = control
by PWMI, 0 = control by SMBus) default = 0
BL_CTL
= BL On/Off (1 = On, 0 = Off) default = 0
FIGURE 31. DESCRIPTIONS OF DEVICE CONTROL REGISTER
REGISTER 0x02
FAULT/STATUS REGISTER
RESERVED
RESERVED
2_CH_SD
1_CH_SD
BL_STAT
Bit 7 (R)
Bit 6 (R)
Bit 5 (R)
Bit 4 (R)
Bit 3 (R)
OV_CURR THRM_SHDN
Bit 2 (R)
FAULT
Bit 1 (R)
Bit 0 (R)
BIT
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
Bit 5
2_CH_SD
= Two LED output channels are shutdown (1 = shutdown, 0 = OK)
Bit 4
1_CH_SD
= One LED output channel is shutdown (1 = shutdown, 0 = OK)
Bit 3
BL_STAT
= BL Status (1 = BL On, 0 = BL Off)
Bit 2
OV_CURR
= Input Overcurrent (1 = Overcurrent condition, 0 = Current OK)
Bit 1
THRM_SHDN
Bit 0
FAULT
= Thermal Shutdown (1 = Thermal Fault, 0 = Thermal OK)
= Fault occurred (Logic “OR” of all of the fault conditions)
FIGURE 32. DESCRIPTIONS OF FAULT/STATUS REGISTER
REGISTER 0x03
ID REGISTER
LED
PANEL
MFG3
MFG2
MFG1
MFG0
REV2
REV1
REV0
Bit 7 = 1
Bit 6 (R)
Bit 5 (R)
Bit 4 (R)
Bit 3 (R)
Bit 2 (R)
Bit 1 (R)
Bit 0 (R)
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
MFG[3..0]
= Manufacturer ID. See “Identification
Register (0x03)” on page 19.
Data 0 to 8 in decimal correspond to other
vendors data 9 in decimal represents Intersil
ID data 10 to 14 in decimal are reserved
data 15 in decimal Manufacturer ID is not
implemented
REV[2..0]
= Silicon rev (Rev 0 through Rev 7 allowed
for silicon spins)
FIGURE 33. DESCRIPTIONS OF ID REGISTER
21
FN6996.1
November 13, 2009
ISL97677
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
11/13/09
FN6996.1
Changed in OVP and VOUT Requirement
Changed from:
VOUT can only regulate between 61% and 100% of the VOUT_OVP such that:
To:
VOUT can only regulate between 64% and 100% of the VOUT_OVP such that
From:
Allowable VOUT = 61% to 100% of VOUT_OVP
To:
Allowable VOUT = 64% to 100% of VOUT_OVP
From:
...then the VOUT is allowed to operate between 24.4V and 40V.
To:
...then the VOUT is allowed to operate between 25.6V and 40V.
From:
...should follow VOUT = (61% ~100%)OVP requirement
To:
...should follow VOUT = (64% ~100%)OVP requirement.
Changed VSC spec from “2.5Vmin, 3.4Vmax, 3.3min, 4.4max, 4.2min, 5.4max to “2.4Vmin,
3.6Vmax, 3.3min, 4.6max, 4.2min, 5.6max”.
10/21/09
FN6996.0
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL97677
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
22
FN6996.1
November 13, 2009
ISL97677
Package Outline Drawing
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 11/07
4X 3.5
5.00
28X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
32
25
1
5.00
24
3 .30 ± 0 . 15
17
(4X)
8
0.15
9
16
TOP VIEW
0.10 M C A B
+ 0.07
32X 0.40 ± 0.10
4 32X 0.23 - 0.05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0.1
C
BASE PLANE
SEATING PLANE
0.08 C
( 4. 80 TYP )
(
( 28X 0 . 5 )
SIDE VIEW
3. 30 )
(32X 0 . 23 )
C
0 . 2 REF
5
( 32X 0 . 60)
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
23
FN6996.1
November 13, 2009