DATASHEET

8-Channel 45V, 50mA LED Driver
ISL97678
Features
The ISL97678 is an 8-channel PWM dimming LED driver for
LCD backlight applications. The ISL97678 is capable of driving
up to 96 pieces of 3.4V/50mA LEDs but larger numbers of
LEDs is possible if the LED forward voltage combined is less
than 45V. The ISL97678 has 8 channels of voltage controlled
current sources with typical currents matching to ±1%, which
compensate for the non-uniformity effect of forward voltages
variance in the LED strings. To minimize the voltage headroom
and power loss in the typical multi-string operation, the
ISL97678 features dynamic headroom control that monitors
the highest LED forward voltage string and uses its feedback
signal for output regulation.
• 8 Channels
• 4.75V ~ 26V Input
• 45V Maximum Output
• Drive Typically 96 LEDs (3.4V/50mA each)
• External PWM Input up to 20kHz Dimming
• Dimming range 0.4%~100% up to 30kHz
• Current Matching ±0.7% Typical
• Protections
- String Open Circuit and Short Circuit Detections, OVP, and
OTP
• Adjustable Dimming Frequency
The ISL97678 features PWM dimming up to 30kHz with
0.4%~100% duty cycle and maintains ±1% current matching
across all ranges. The PWM dimming frequency can be
adjusted between 100Hz and 30kHz. The boost switching
frequency can also be adjusted between 600kHz and 1.5MHz.
• Adjustable Switching Frequency
• 32 Ld (5mmx5mm) QFN Package
Applications
The ISL97678 features extensive protection functions that
include string open and short circuit detections, OVP, and OTP.
• Notebook Displays WLED or RGB LED Backlighting
• LCD Monitor LED Backlighting
ISL97678 is available in the 32 Leads QFN 5mmx5mm and
operate from -40°C to +85°C with input voltage ranges from
4.75V to 26V.
VIN
4.75V~26V
45V*, 50mA per String
96 (8x12) LEDs
CIN
10µH/3A
3x4.7µF/50V
OVP
PWM
ISL97678
RSET
RFPWM
RSET
CH1
CH2
FPWM
LED
BACKLIGHT
CH8
FSW
RFSW
RLOWER
EN
PROCESSOR
RUPPER
LX
CLOWER
VIN
CUPPER
10µF
COUT
AGND
PGND
FIGURE 1. TYPICAL APPLICATION CIRCUIT: TFT-LCD NOTEBOOK DISPLAY
May 6, 2014
FN6998.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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ISL97678
Typical Application Circuit
10µH/3A
10µF
21
3x4.7µF/50V
COUT
CUPPER
100pF
17 EN
OVP
ISL97678
RUPPER
806k 
VIN
20
LX
CIN Optional fuse
LX
L1
16
45V*, 50mA per String
96 (8x12) LEDs
D1
VIN* = 4.75V~26V
23
18
VDC
CH1
25
10
VLOGIC
CH2
26
11
FSW
CH3
27
12
FPWM
CH4
28
13
RSET
CH5
29
14 COMP
CH6
30
CLOWER
3.3nF
RLOWER
22k 
1µF
1µF
50k
333k
THERMAL
PAD
14.2k
3.3nF
15k 
CH8
32
3
AGND
PGND
1
5
AGND
PGND 19
PGND
AGND
AGND
2
AGND
31
AGND
CH7
AGND
PWM
AGND
4
6
7
8
9
15
22
Note: VIN* ≥ 12V for 45V/50mA Applications
FIGURE 2. ISL97678 TYPICAL APPLICATION DIAGRAM
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FN6998.2
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ISL97678
Block Diagram
45V*, 50mA per String
96 (8x12) LEDs
VIN = 4.75V~26V
CIN
Optional fuse
10µH/3A
VIN
LX
EN
2x4.7µF/50V
REG
OVP
OVP
LOGIC BIAS
FAULT
FSW
FSW
OSC &
RAMP
COMP
LOGIC
RFSW
Imax
RLOWER
VLOGIC
ANALOG BIAS
RUPPER
REG1
CLOWER
O/P SHORT
VDC
COUT
CUPPER
10µF
FET
DRIVER
ILIMIT
PGND
FAULT CONTROL
COMP
GM
AMP
RSET
REF
GEN
+
-
1
2
CH8
REF_VSC
REF_OVP
RSET
AGND
CH1
CH2
HIGHEST VF
STRING DETECT
VSET
+
-
Open Ckt, Short Ckt
Detection
PWM
PWM DIMMING
CONTROLLER
FPWM
RFPWM
TEMP
SENSOR
FAULT
CONTROL
+
-
8
ISL97678
FIGURE 3. ISL97678 BLOCK DIAGRAM
Ordering Information
PART NUMBER
(Notes 1, 2)
PART MARKING
ISL97678IRZ
ISL9767 8IRZ
PACKAGE
(RoHS Compliant)
32 Ld 5x5 QFN
PKG.
DWG. #
L32.5x5B
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL97678. For more information on MSL please see techbrief TB363.
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FN6998.2
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ISL97678
Pin Configuration
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
ISL97678
(32 LD 5X5 QFN)
TOP VIEW
32
31
30
29
28
27
26
25
PGND
1
24 NC
AGND
2
23 OVP
AGND
3
22 PGND
PWM
4
21 LX
EXPOSED THERMAL PAD
7
18 VDC
AGND
8
17 EN
10
11
12
13
14
15
16
VIN
9
AGND
AGND
COMP
19 PGND
RSET
6
FPWM
AGND
FSW
20 LX
VLOGIC
5
AGND
AGND
Pin Descriptions (I = Input, O = Output, S = Supply)
PIN
NAME
TYPE
DESCRIPTION
1, 19, 22
PGND
S
Power Ground.
2, 3, 5, 6, 7,
8, 9, 15
AGND
S
Analog Ground.
4
PWM
I
PWM Brightness Control.
10
VLOGIC
O
Internal 2.5V Logic Bias Regulator. Need Decoupling Capacitor for Regulation.
11
FSW
I
When RFSW is 100k, fSW is 500kHz.
When RFSW is 33k, fSW is 1.5MHz.
12
FPWM
I
When RFPWM is 333k, FPWM is 200Hz.
When RFPWM is 3.3k, FPWM is 20kHz.
13
RSET
I
Resistor Connection for Setting LED Current.
14
COMP
O
Boost compensation.
16
VIN
S
Main Power.
17
EN
I
Enable
18
VDC
S
Internal 5V Analog Bias Regulator. Needs Decoupling Capacitor for Regulation.
20, 21
LX
O
Boost MOSFET Drain Terminal Switching Node.
23
OVP
I
Overvoltage Protection Input as well as Output Voltage FB Monitoring.
24
NC
I/O
25 ~ 32
CH1 ~ CH8
I
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No Connect
LED Driver PWM Dimming Monitoring.
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May 6, 2014
ISL97678
Absolute Maximum Ratings
Thermal Information
Voltage ratings are all with respect to AGND pin
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 27V
EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 27V
VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.75V
VDC, PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.75V
COMP, RSET, FPWM, FSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to min
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(VDC + 0.3V, 5.75V)
CH1 - CH8, LX, OVP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V
PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Thermal Resistance (Typical)
JA (°C/W)
32 Ld QFN (Notes 4, 5). . . . . . . . . . . . . . . . . 31
Thermal Characterization (Typical, Note 6)
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
JC (°C/W)
3
PSIJT (°C/W)
32 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.2
Maximum Continuous Junction Temperature . . . . . . . . . . . . . . . . .+125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation
TA < +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2W
TA < +70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8W
TA < +85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3W
TA < +100°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8W
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. PSIJT is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this rating then the die
junction temperature can be estimated more accurately than the JA and JC thermal resistance ratings.
Electrical Specifications
5.
All specifications below are characterized at TA = -40°C to +85°C; VIN = 12V, EN = 5V, RSET = 36kΩ, unless
otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
GENERAL
VIN
Backlight Supply Voltage
IVIN_SHDN
VIN Shutdown Current
VOUT
Output Voltage
VUVLO
Undervoltage Lockout Threshold
VUVLO_HYS
Undervoltage Lockout Hysteresis
4.75
EN = 0
2.9
26
(Note 8)
V
5
µA
45
V
3.3
V
300
mV
LINEAR REGULATOR
VDC
5V Analog Bias Regulator
VIN > 6V
VDC_DROP
VDC LDO Dropout Voltage
IVDC
4.8
5
5.1
V
IVDC = 30mA
71
100
mV
Active Current
EN = 5V, R = 33kΩ
10
VLOGIC
2.5V Logic Bias Regulator
VIN > 6V
VLOGIC_DROP
VLOGIC LDO Dropout Voltage
IVLOGIC = 30mA
2.3
mA
2.4
2.5
V
31
100
mV
BOOST SWITCHING REGULATOR
SS
Soft-Start
SWILimit
Boost FET Current Limit
rDS(ON)
Internal Boost Switch ON-Resistance
VFSW
fSW Voltage
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16
5
TA = +25°C to +85°C
3.0
ms
4.7
130
RFSW = 33kΩ
1.18
1.21
A
mΩ
1.24
V
FN6998.2
May 6, 2014
ISL97678
Electrical Specifications
All specifications below are characterized at TA = -40°C to +85°C; VIN = 12V, EN = 5V, RSET = 36kΩ, unless
otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
Eff_peak
DESCRIPTION
Peak Efficiency
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
VIN = 24V, 96LEDs, 20mA
each, L = 10µH with DCR
100mΩFSW = 600kHz,
TA = +25°C
92.4
%
VIN = 12V, 96 LEDs, 20mA
each, L = 10µH with DCR
100mΩFSW = 600kHz,
TA = +25°C
91.5
%
VIN = 6V, 96 LEDs, 20mA
each, L = 10µH with DCR
100mΩFSW = 600kHz,
TA = +25°C
81.6
%
VIN = 24V, 80 LEDs, 40mA
each, L = 10µH with DCR
100mΩFSW=600kHz,
TA = +25°C
93.4
%
VIN = 12V, 80 LEDs, 40mA
each, L = 10µH with DCR
100mΩFSW = 600kHz,
TA = +25°C
90.7
%
DMAX
Boost Maximum Duty Cycle
fSW = 500kHz
90
DMIN
Boost Minimum Duty Cycle
fSW = 500kHz
fSW
Boost Switching Frequency
RFSW = 100kΩ
0.45
RFSW = 33kΩ
1.35
ILX_leakage
Lx Leakage Current
VLX = 45V, EN= 0V
IMATCH
Channel-to-Channel Current Matching
ILED = 20mA
-1.1
IACC
Absolute Current Accuracy
RSET = 36kΩTA = +25°C
%
10
%
0.5
0.55
MHz
1.5
1.65
MHz
10
µA
+1.1
%
-1.5
+1.5
%
-2
+2
%
3.3
4.6
V
REFERENCE
RSET = 36kΩ
TA = -40°C to +80°C
±0.7
FAULT DETECTION
VSC
Channel Short Circuit Threshold
Vtemp
Over-Temperature Threshold
Vtemp_acc
Over-Temperature Threshold Accuracy
VOVP
Overvoltage Limit on OVP Pin
1.18
150
°C
5
°C
1.22
1.24
V
0.8
V
5.5
V
DIGITAL INTERFACE
VIL
Logic Input Low Voltage
VIH
Logic Input High Voltage
1.5
CURRENT SOURCES
VHEADROOM
Dominant Channel Current Source Headroom at CH ILED = 50mA
Pin
TA = +25°C
VRSET
Voltage at RSET Pin
ILEDmax
Maximum LED Current per Channel
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1.0
1.18
LED config = 8P10S with
VF = 3.4V and VIN = 11V
1.21
50
V
1.24
V
mA
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May 6, 2014
ISL97678
Electrical Specifications
All specifications below are characterized at TA = -40°C to +85°C; VIN = 12V, EN = 5V, RSET = 36kΩ, unless
otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
DESCRIPTION
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
RFPWM = 330kΩ
180
200
220
Hz
RFPWM = 3.3kΩ
18
20
22
kHz
fPWM  30kHz
0.4
100
%
200
20k
Hz
1.25
V
TEST CONDITIONS
PWM GENERATOR
FPWM
Generated PWM Frequency
Dimming Range
PWM Dimming Duty Cycle Limits (Note 9)
FPWMI
PWMI Input Frequency Range (Note 9)
VFPWM
VFPWM Voltage
RFPWM = 3.3kΩ
1.18
1.21
NOTES:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
8. At maximum VIN of 26V, minimum VOUT is 28V. Minimum VOUT can be lower at lower VIN
9. Limits established by characterization and are not production tested.
Typical Performance Curves
100
100
50mA
8P11S
fSW = 600kHz
95
0°C
90
-40°C
+85°C
85
EFFICIENCY (%)
EFFICIENCY (%)
95
20mA
8P11S
fSW = 600kHz
+25°C
80
-40°C
0°C
90
+85°C
85
80
75
75
+25°C
70
0
5
10
15
VIN (V)
20
25
5
10
15
20
25
30
FIGURE 5. EFFICIENCY vs VIN vs TEMPERATURE AT 20mA
95
8P10S
50mA
8P11S
94
93
92
12V/50mA
EFFICIENCY (%)
EFFICIENCY (%)
0
VIN (V)
FIGURE 4. EFFICIENCY vs VIN vs TEMPERATURE AT 50mA
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
70
30
24V/50mA
24V
91
90
89
88
87
12V
86
85
0
10
20
30
ILED (mA)
FIGURE 6. EFFICIENCY vs ILED
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7
40
50
84
400
600
800
1k
1.2k
1.4k
SWITCHING FREQUENCY (Hz)
1.6k
FIGURE 7. EFFICIENCY vs SWITCHING FREQUENCY
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May 6, 2014
ISL97678
Typical Performance Curves (Continued)
1.0
0.6
12V/20mA
0.4
0.2
0.0
-0.2
-0.4
-0.6
12V/50mA
0.0
4
5
CHANNEL
3
6
7
8
+85°C
-0.4
-0.6
-40°C
0
5
10
15
VIN (V)
20
25
30
FIGURE 9. CURRENT MATCHING vs VIN vs TEMPERATURE
2.0
20mA - 8P12S
50mA - 8P11S
1.6
1.8
CHANNEL VOLTAGE (V)
1.8
12V/50mA
1.4
24V/50mA
1.2
1.0
0.8
5V/20mA
0.6
0.4
24V/20mA
0.2
0.4
0.8 1.2 1.6 2.0 2.4 2.8 3.2
PWM DIMMING DUTY CYCLE (%)
3.6
1.6
1.4
1.2
1.0
0.8
0.6
12V/20mA
0.4
0.0
4.0
FIGURE 10. CURRENT LINEARITY vs LOW LEVEL PWM DIMMING
DUTY CYCLE
1.00
50mA
8P11S
0.95
HEADROOM CONTROL CHANNEL
1.0
0.8
0.85
0.7
VHEADROOM (V)
0.90
+85°C
0.70
0°C
0.65
20
25
30
FIGURE 12. VHEADROOM vs VIN vs TEMPERATURE AT 50mA
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+25°C
0.3
0.1
15
VIN (V)
6
7
8
+85°C
0.4
0.2
10
4
5
CHANNEL
0.5
0.55
5
3
0.6
0.60
0
2
20mA
8P11S
0.9
0.75
1
FIGURE 11. TYPICAL CHANNEL VOLTAGE EXAMPLE
+25°C
0.80
20mA - 8P12S
50mA - 8P11S
12V/50mA
0.2
0.0
0.0
0.50
+25°C
-0.2
-1.0
2.0
ILED (mA)
0.2
-0.8
2
0°C
0.4
-1.0
FIGURE 8. CHANNEL-TO-CHANNEL CURRENT MATCHING EXAMPLE
VHEADROOM (V)
0.6
-0.8
1
50mA
8P11
0.8
CURRENT MATCHING (%)
CURRENT MATCHING (%)
1.0
20mA - 8P12S
50mA - 8P11S
0.8
0.0
0
5
10
0°C
15
VIN (V)
20
25
30
FIGURE 13. VHEADROOM vs VIN vs TEMPERATURE AT 20mA
FN6998.2
May 6, 2014
ISL97678
Typical Performance Curves (Continued)
10
EN = HIGH
PWM DUTY CYCLE = 0%
9
8
LX (20V/DIV)
IIN (mA)
7
+85°C
6
5
VO (100mV/DIV)
4
-40°C
3
ILED (20mA/DIV)
2
1
0
0
5
10
15
20
25
30
VIN (V)
FIGURE 14. QUIESCENT CURRENT vs VIN vs TEMPERATURE WITH
ENABLE
FIGURE 15. VOUT RIPPLE VOLTAGE
VO (20V/DIV)
VO (20V/DIV)
EN (5V/DIV)
EN (5V/DIV)
IIN (1A/DIV)
IIN (1A/DIV)
ILED (50mA/DIV)
FIGURE 16. IN-RUSH CURRENT and LED CURRENT AT VIN = 12V
VIN (10V/DIV)
ILED (50mA/DIV)
FIGURE 17. IN-RUSH CURRENT AND LED CURRENT AT VIN = 26V
VIN (10V/DIV)
IIN (500mA/DIV)
IIN (500mA/DIV)
ILED (50mA/DIV)
FIGURE 18. LINE REGULATION WITH VIN CHANGES FROM 12V TO
26V DISABLE PROFILE
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ILED (50mA/DIV)
FIGURE 19. LINE REGULATION WITH VIN CHANGES FROM 26V TO
12V
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ISL97678
Typical Performance Curves (Continued)
VO (1V/DIV)
VO (1V/DIV)
ILED (20mA/DIV)
ILED (20mA/DIV)
FIGURE 20. LOAD REGULATION WITH ILED CHANGES FROM 0.4% TO
100% PWM DIMMING
FIGURE 21. LOAD REGULATION WITH ILED CHANGES FROM 100% TO
0.4% PWM DIMMING
VO (500mV/DIV)
VO (1V/DIV)
ILED (20mA/DIV)
ILED (20mA/DIV)
FIGURE 22. LOAD REGULATION WITH ILED CHANGES FROM 0% TO
100% PWM DIMMING
VO (20V/DIV)
FIGURE 23. LOAD REGULATION WITH ILED CHANGES FROM 100% to
0% PWM DIMMING
FPWM = 30KHz
100nSec/DIV
PWM Input (1V/DIV)
EN (5V/DIV)
IIN (1A/DIV)
ILED (20mA/DIV)
ILED (50mA/DIV)
FIGURE 24. DISABLE PROFILE
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FIGURE 25. MINIMUM 0.4% PWM DIMMING DUTY CYCLE
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ISL97678
Theory of Operation
PWM Boost Converter
The current mode PWM boost converter produces the minimal
voltage needed to enable the LED string with the highest forward
voltage drop to run at the programmed current. The ISL97678
employs current mode control boost architecture that has a fast
current sense loop and a slow voltage feedback loop. This
architecture achieves a fast transient response that is essential
for the notebook backlight application where the power can be
several Li-ion cell batteries or instantly change to an AC/DC
adapter without rendering a noticeable visual nuisance. The
number of LEDs that can be driven by ISL97678 depends on the
type of LED chosen in the application. The ISL97678 is capable
of boosting up to 45V and drive 8 channels of LEDs at a
maximum of 45mA per channel.
all LED strings are connected to the same output voltage, the
other CH pins will have a higher voltage, but the regulated current
source circuit on each channel will ensure that each channel has
the same programmed current. The output voltage will regulate
cycle-by-cycle and is always referenced to the highest forward
voltage string in the architecture.
OVP and VOUT Requirement
The Overvoltage Protection (OVP) pin has a function of setting the
overvoltage trip level as well as limiting the VOUT regulation
range.
The ISL97678 OVP threshold is set by RUPPER and RLOWER as
shown in Equation 1:
V OUT_OVP = 1.21V   R UPPER + R LOWER   R LOWER
(EQ. 1)
Current Matching and Current Accuracy
VOUT can only regulate between 64% and 100% of the VOUT_OVP
such that:
Each channel of the LED current is regulated by the current
source circuit, as shown in Figure 26.
Allowable VOUT = 64% to 100% of VOUT_OVP
The LED peak current is set by translating the RSET current to the
output with a scaling factor of 707.9/RSET. The source terminals
of the current source MOSFETs are designed to run at 500mV to
optimize power loss versus accuracy requirements. The sources
of errors of the channel-to-channel current matching come from
the op amps offset, internal layout, reference, and current source
resistors. These parameters are optimized for current matching
and absolute current accuracy. However, the absolute accuracy is
additionally determined by the external RSET. A 0.1% tolerance
resistor is recommended.
.
For example, if 10 LEDs are used with the worst case VOUT of
35V. If RUPPER and RLOWER are chosen such that the OVP level is
set at 40V, then the VOUT is allowed to operate between 25.6V
and 40V. If the requirement is changed to a 6 LEDs 21V VOUT
application, then the OVP level must be reduced and users
should follow VOUT = (64% ~100%) OVP requirement. Otherwise,
the headroom control will be disturbed such that the channel
voltage can be much higher than expected and sometimes it can
prevent the driver from operating properly.
The ratio of the OVP capacitors should be the inverse of the OVP
resistors. For example, if RUPPER/RLOWER = 33/1, then
CUPPER/CLOWER = 1/33 with CUPPER = 100pF and
CLOWER = 3.3nF.
Dimming Controls
The ISL97678 allows two ways of controlling the LED current, and
therefore, the brightness. They are:
1. DC current adjustment
+
-
REF
2. PWM chopping of the LED current defined in Step 1.
+
-
There are various ways to achieve DC or PWM current control,
which will be described in the following.
RSET
+
PWM DIMMING
In any dimming controls, the EN pin must be high. EN is a high
voltage pin that can be applied with a digital signal or tied
directly to VIN for enable function.
MAXIMUM DC CURRENT SETTING
FIGURE 26. SIMPLIFIED CURRENT SOURCE CIRCUIT
Dynamic Headroom Control
The ISL97678 features a proprietary Dynamic Headroom Control
circuit that detects the highest forward voltage string or
effectively the lowest voltage from any of the CH pins. When this
lowest IIN voltage is lower than the short circuit threshold, VSC,
such voltage will be used as the feedback signal for the boost
regulator. The boost makes the output to the correct level such
that the lowest CH pin is at the target headroom voltage. Since
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The initial brightness should be set by choosing an appropriate
value for RSET. This should be chosen to fix the maximum
possible LED current:
707.9
I LEDmax = --------------R SET
(EQ. 2)
Alternatively, the RSET can be replaced by a digital potentiometer
for adjustable current.
FN6998.2
May 6, 2014
ISL97678
PWM CONTROL
The ISL97678 provides PWM dimming by PWM chopping of the
current in the LEDs for all 8 channels. To achieve PWM dimming,
the users need to apply a PWM signal at the PWM pin. The PWM
output will follow the PWM input and the dimming frequency will
be set by RPWM. During the On periods, the LED current will be
defined by the value of RSET, as described in Equation 1.
PWM Dimming Frequency Adjustment
The dimming frequencies are set by an external resistor at the
FPWM pin as shown by Equation 3:
7
6.66 10
f PWM = -----------------------R FPWM
(EQ. 3)
where fPWM is the desirable PWM dimming frequency and
RFPWM is the setting resistor. fPWM range is from 100Hz to
30kHz.
Switching Frequency
The boost switching frequency can be adjusted by a resistor as
shown in Equation 4:
10
 5 10 
f SW = ----------------------R FSW
(EQ. 4)
where fSW is the desirable boost switching frequency and RFSW is
the setting resistor.
5V and 2.3V Low Dropout Regulators
A 5V LDO regulator is present at the VDC pin to develop the
necessary low voltage supply, which is used by the chips internal
control circuitry. Because VDC is an LDO pin, it requires a bypass
capacitor of 1µF or more for the regulation. The VDC pin can be
used for a coarse regulator or reference but does not pull more
than a few mA from it.
Similarly, a 2.3V LDO regulator is present at the VLOGIC pin to
develop the necessary low voltage supply for the chip’s internal
logic control circuitry. A 1µF bypass capacitor or more is needed
for regulation. The VLOGIC pin can be used as a coarse regulator or
reference but does not pull more than a few mA from it.
Soft-Start
The ISL97678 uses a digital soft-start where the boost current
limit is stepped up in 8 steps. The initial current limit level is set
to one ninth of the full current limit, with subsequent steps
increasing this by a ninth every 2ms. In the event that no LEDs
have been conducting during the interval since the last step (for
example if the LEDs are running at a low duty cycle at a low PWM
frequency) then the step will be delayed until the LEDs are
conducting. If the LEDs are disabled and re-enabled again then
soft-start will be restarted when the LEDs are enabled.
Fault Protection and Monitoring
The ISL97678 features extensive protection functions to cover all
the perceivable failure conditions. The failure mode of a LED can
be either open circuit or as a short. The behavior of an open
circuited LED can additionally take the form of either infinite
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resistance or, for some LEDs, a zener diode, which is integrated
into the device in parallel with the now opened LED.
For basic LEDs (which do not have built-in zener diodes), an open
circuit failure of an LED will only result in the loss of one channel
of LEDs without affecting other channels. Similarly, a short circuit
condition on a channel that results in that channel being turned
off does not affect other channels unless a similar fault is
occurring.
Due to the lag in boost response to any load change at its output,
certain transient events (such as significant step changes in LED
duty cycle) can transiently look like LED fault modes. The
ISL97678 uses feedback from the LEDs to determine when it is
in a stable operating region and prevents apparent faults during
these transient events from allowing any of the LED strings to
fault out. See Table 1 for more details.
Short Circuit Protection (SCP)
The short circuit detection circuit monitors the voltage on each
channel and disables faulty channels which are detected above
the programmed short circuit threshold. When an LED becomes
shorted, the action taken is described in Table 1. The short circuit
threshold is 4V.
Open Circuit Protection (OCP)
When one of the LEDs becomes open circuit, it can behave as
either an infinite resistance or a gradually increasing finite
resistance. The ISL97678 monitors the current in each channel
such that any string which reaches the intended output current is
considered “good”. Should the current subsequently fall below
the target, the channel will be considered an “open circuit”.
Furthermore, should the boost output of the ISL97678 reach the
OVP limit or should the lower over-temperature threshold be
reached, all channels which are not “good” will immediately be
considered as “open circuit”. Detection of an “open circuit”
channel will result in a time-out before disabling of the affected
channel.
Some users employ some special types of LEDs that have zener
diode structure in parallel with the LED for ESD enhancement, thus
enabling open circuit operation. When this type of LED goes open
circuit, the effect is as if the LED forward voltage has increased,
but no light will be emitted. Any affected string will not be disabled,
unless the failure results in the boost OVP limit being reached,
allowing all other LEDs in the string to remain functional. Care
should be taken in this case that the boost OVP limit and SCP limit
are set properly, so as to make sure that multiple failures on one
string do not cause all other good channels to be faulted out. This
is due to the increased forward voltage of the faulty channel
making all other channel look as if they have LED shorts. See
Table 1 for details for responses to fault conditions.
Overvoltage Protection (OVP)
The integrated OVP circuit monitors the output voltage and keeps
the voltage at a safe level. The OVP threshold is set as shown in
Equation 5:
OVP = 1.21V   RUPPER + R LOWER   R LOWER
(EQ. 5)
These resistors should be large to minimize the power loss. For
example, a 1Mk RUPPER and 30k RLOWER sets OVP to 41.2V.
FN6998.2
May 6, 2014
ISL97678
Large OVP resistors also allow COUT discharges slowly during the
PWM Off time. Parallel capacitors should be placed across the
OVP resistors such that RUPPER/RLOWER = CLOWER/CUPPER.
Using a CUPPER value of at least 30pF is recommended. These
capacitors reduce the AC impedance of the OVP node, which is
important when using high value resistors.
channel which is outputting current at a level significantly below the
regulation target will be treated as “open circuit” and disabled after
a time-out period. The intention of the lower threshold is to allow
bad channels to be isolated and disabled before they cause enough
power dissipation (as a result of other channels having large
voltages across them) to hit the upper temperature threshold.
Undervoltage Lockout
The upper threshold is set to +150°C. Each time this is reached,
the boost will stop switching and the output current sources will
be switched off and stay off until the control driver is power off
and re-enables it. For the extensive fault protection conditions,
please refer to Figure 27 and Table 1 for details.
If the input voltage falls below the UVLO level of 2.8V, the device
will stop switching and be reset. Operation will restart only if the
device control interface re-enables it once the input voltage is
back in the normal operating range. Also all digital settings will
be reset to their default states.
Over-Temperature Protection (OTP)
The ISL97678 includes two over-temperature thresholds. The lower
threshold is set to +130°C. When this threshold is reached, any
Shutdown
When the EN pin is low the entire chip is shut down to give close
to zero shutdown current. The digital interfaces will not be active
during this time.
VIN
VOUT
DRIVER
IMAX
ILIMIT
LX
FAULT
O/P
SHORT
OVP
FET
DRIVER
LOGIC
CH1
VSC
CH8
VSET/2
REG
THRM
SHDN
REF
OTP
T2
TEMP
SENSOR
T1
VSET
+
Q1 VSET
Q8
-
PWM1/OC1/SC1
CONTROL
LOGIC
+
PWM8/OC8/SC8
DC CURRENT
FIGURE 27. SIMPLIFIED FAULT PROTECTIONS
TABLE 1. PROTECTIONS TABLE
CASE
FAILURE MODE
DETECTION MODE
FAILED CHANNEL ACTION
GOOD CHANNELS ACTION
VOUT REGULATED
BY
1
CH1 Short Circuit
Upper Over-Temperature CH1 ON and burns power
Protection limit (OTP) not
triggered and VIIN0 <
VSC
CH2 through CH8 Normal
Highest VF of CH2
through CH8
2
CH1 Short Circuit
Upper OTP triggered but
VIIN1 < VSC
Same as CH1
Highest VF of CH2
through CH8
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CH1 goes off
FN6998.2
May 6, 2014
ISL97678
TABLE 1. PROTECTIONS TABLE (Continued)
CASE
FAILURE MODE
DETECTION MODE
FAILED CHANNEL ACTION
GOOD CHANNELS ACTION
VOUT REGULATED
BY
3
CH1 Short Circuit
Upper OTP not triggered
but VIIN1 > VSC
CH1 disabled after 6 PWM cycles
time-out.
If 3 channels are already shut
down, all channels will be shut
down. Otherwise CH2-8 will
remain as normal
Highest VF of CH2
through CH8
4
CH1 Open Circuit
with infinite
resistance
Upper OTP not triggered
and VIIN1 < VSC
VOUT will ramp to OVP. CH1 will
time-out after 6 PWM cycles and
switch off. VOUT will drop to normal
level.
CH2 through CH8 Normal
Highest VF of CH2
through CH8
5
CH1 LED Open
Circuit but has
paralleled Zener
Upper OTP not triggered
and VIIN1 < VSC
CH1 remains ON and has highest
VF, thus VOUT increases
CH2 through CH8 ON, Q2 through VF of CH1
Q8 burn power
6
CH1 LED Open
Circuit but has
paralleled Zener
Upper OTP triggered but
VIIN1 < VSC
CH1 goes off
Same as CH1
VF of CH1
7
CH1 LED Open
Circuit but has
paralleled Zener
Upper OTP not triggered
but VIIN1 > VSC
CH1 OFF
CH2 through CH8 Normal
Highest VF of CH2
through CH8
Upper OTP not triggered
but VIINx > VSC
CH1 remains ON and has highest
VF, thus VOUT increases.
VOUT increases then CH-X
switches OFF. This is an
unwanted shut off and can be
prevented by setting OVP and/or
VSC at an appropriate level.
VF of CH1
8
Channel-to-Channel
VF too high
Lower OTP triggered but
VIINx < VSC
Any channel at below the target current will fault out after 6 PWM
cycles.
Remaining channels driven with normal current.
Highest VF of CH1
through CH8
9
Channel-to-Channel
VF too high
Upper OTP triggered but
VIINx < VSC
All channels switched off
Highest VF of CH1
through CH8
10
Output LED string
voltage too high
VOUT > VOVP
Driven with normal current. Any channel that is below the target current Highest VF of CH1
will time-out after 6 PWM cycles.
through CH8
11
VOUT/LX shorted to
GND
LX will not switch
Input Capacitor
Components Selections
According to the inductor Voltage-Second Balance principle, the
change of inductor current during the switching regulator
On-time is equal to the change of inductor current during the
switching regulator Off-time. Since the voltage across an inductor
is as shown in Equation 6:
V L = L  I L  t
(EQ. 6)
and IL @ On = IL @ Off, therefore:
 V I – 0   L  D  tS =  VO – VD – VI   L   1 – D   tS
(EQ. 7)
where D is the switching duty cycle defined by the turn-on time
over the switching periods. VD is Schottky diode forward voltage
that can be neglected for approximation.
Switching regulators require input capacitors to deliver peak
charging current and to reduce the impedance of the input
supply. This reduces interaction between the regulator and input
supply, thereby improving system stability. The high switching
frequency of the loop causes almost all ripple current to flow in
the input capacitor, which must be rated accordingly.
A capacitor with low internal series resistance should be chosen
to minimize heating effects and improve system efficiency, such
as X5R or X7R ceramic capacitors, which offer small size and a
lower value of temperature and voltage coefficient compared to
other ceramic capacitors.
It is recommended that an input capacitor of at least 10µF be
used. Ensure the voltage rating of the input capacitor is suitable
to handle the full supply range.
Rearranging the terms without accounting for VD gives the boost
ratio and duty cycle respectively as Equations 8 and 9:
VO  VI = 1   1 – D 
(EQ. 8)
D =  VO – VI   VO
(EQ. 9)
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ISL97678
Inductor
The selection of the inductor should be based on its maximum
and saturation current (ISAT) characteristics, power dissipation
(DCR), EMI susceptibility (shielded vs unshielded), and size.
Inductor type and value influence many key parameters,
including ripple current, current limit, efficiency, transient
performance and stability.
The inductor’s maximum current capability must be adequate
enough to handle the peak current at the worst case condition.
Additionally, if an inductor core is chosen with too low a current
rating, saturation in the core will cause the effective inductor
value to fall, leading to an increase in peak to average current
level, poor efficiency and overheating in the core. The series
resistance, DCR, within the inductor causes conduction loss and
heat dissipation. A shielded inductor is usually more suitable for
EMI susceptible applications, such as LED backlighting.
The peak current can be derived from the voltage across the
inductor during the Off-period, as expressed in Equation 10:
IL peak =  V O  I O    85%  V I  + 1  2  V I   V O – V I    L  V O  f SW
(EQ. 10)
The choice of 85% is just an average term for the efficiency
approximation. The first term is the average current, which is
inversely proportional to the input voltage. The second term is
the inductor current change, which is inversely proportional to L
and fSW as a result, for a given switching.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
3/22/2014
FN6998.2
Changed PWM dimming “0.8%~100% duty cycle” to “0.4%~100% duty cycle” on the front page.
Changed External PWM Input “25kHz” to “20kHz” in the Features section in order to be consistent with Electrical
Specifications.
Updated Application Circuit and Block Diagram drawings along with the resistor and capacitor names.
Moved the VFSW specification to the BOOST SWITCHING REGULAR section of the Electrical Specifications table.
Changed “/SHUT” to “EN” in order to be consistent with the Pin Descriptions table.
Changed “ISET” to “RSET” for the LED current setting resistor in order to be consistent across the datasheet.
Changed “VISET” to “VRSET” in order to be consistent with the RSET pin name.
Changed “ROSC” to “RFSW” in order to be consistent across the datasheet.
Changed “R1” and “R2” to “RUPPER” and “RLOWER”, respectively in OVP and VOUT Requirement section.
Added FIGURE 1. TYPICAL APPLICATION CIRCUIT: TFT-LCD NOTEBOOK DISPLAY.
Added FIGURE 25. MINIMUM 0.4% PWM DIMMING DUTY CYCLE.
Updated “Package Outline Drawing” on page 16 to the latest revision.
11/5/09
FN6998.1
Changed VSC spec from Changed VSC spec from “3.3min, 4.4max” to “3.3min, 4.6max”.
10/26/09
FN6998.0
Initial Release
About Intersil
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FN6998.2
May 6, 2014
ISL97678
Package Outline Drawing
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 5/10
4X 3.5
5.00
28X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
32
25
1
5.00
24
3 .30 ± 0 . 15
17
(4X)
8
0.15
9
16
0.10 M C A B
+ 0.07
32X 0.40 ± 0.10
TOP VIEW
4 32X 0.23 - 0.05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
C
0 . 90 ± 0.1
BASE PLANE
SEATING PLANE
0.08 C
( 4. 80 TYP )
( 28X 0 . 5 )
SIDE VIEW
(
3. 30 )
(32X 0 . 23 )
C
0 . 2 REF
5
( 32X 0 . 60)
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
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FN6998.2
May 6, 2014
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