DATASHEET

NS
DESIGVoltage
EWOctal
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ISL24010
for TFT/LCD Panels
FN6124.0
High Voltage TFT-LCD Logic Driver
Features
The ISL24010 is a high voltage TFT-LCD logic driver with a
+40V and -20V (momentary absolute max) output voltage
swing capability. It is manufactured using the Intersil’s
proprietary monolithic high voltage bipolar process and is
capable of driving a 3000pF load in 500ns.
• 0V to 5.5V (absolute max) Input Voltage Range
The ISL24010 will level shift a digital input signal to an output
voltage nearly equal to its output supply voltages. The
ISL24010 has 3 supplies. VON1 and VON2 are positive
supplies with a voltage range between +10V and +40V
(absolute max). VOFF is the negative supply with a voltage
range between -5V and -20V (absolute max). Outputs 1
through 6 are connected to VON1 and VOFF. Outputs 7 and 8
are connected to VON2 and VOFF. This configuration
enables outputs 1 through 6 to provide slicing to the row
drivers to reduce flicker, and outputs 7 and 8 to control
possible supply lines. VON2 should remain constant. It is
possible to tie VON1 and VON2 supplies together, if
independent control as described above is not desired.
VON2 is required to be greater than or equal to VON1 at all
times.
The ISL24010 is available in TSSOP-20 pin package. It is
specified for operation over the -40°C to +85°C industrial
temperature range.
Ordering Information
PART
MARKING
TEMP.
RANGE
(°C)
24010IVZ
-40 to +85
20 Ld TSSOP M20.173
(Pb-free)
ISL24010IVZ-T 24010IVZ
(See Note)
-40 to +85
20 Ld TSSOP M20.173
Tape and Reel
(Pb-free)
PART
NUMBER
ISL24010IVZ
(See Note)
PACKAGE
PKG.
DWG. #
• +40V and -20V (momentary absolute max) Output Voltage
Range
• 10mA Output Continuous Current (all 8 channels)
• 25mA Output Peak Current (all 8 channels)
• Rise/Fall Times 150ns/210ns
• Propagation Delay 250ns
• 50kHz Input Logic Frequency
• 20 Ld TSSOP Pb-Free Plus Anneal (RoHS Compliant)
Applications
• TFT-LCD panels
Pinout
20 Ld TSSOP
TOP VIEW
GND
1
20 VON1
IN1
2
19 OUT1
IN2
3
18 OUT2
IN3
4
17 OUT3
IN4
5
16 OUT4
IN5
6
15 OUT5
IN6
7
14 OUT6
IN7
8
13 OUT7
IN8
9
12 OUT8
VOFF 10
11 VON2
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL24010
Functional Diagram
IN1
Connected to VON1
and VOFF
CH1
OUT1
OUT2
CH2
IN2
OUT3
CH3
IN3
OUT4
CH4
IN4
OUT5
CH5
IN5
OUT6
CH6
IN6
IN7
Connected to VON2
and VOFF
CH7
CH8
IN8
2
OUT7
OUT8
ISL24010
Absolute Maximum Ratings (TA = 25°C)
Thermal Information
Driver Positive Supply Voltage Range, (VON) . . . . . . . . +5V to +40V
Power Supply Voltage Range, (VON to VOFF). . . . . . . +10V to +60V
Negative Supply Voltage Range, (VOFF) . . . . . . . . . . . . . -20V to -5V
Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 10V/µs
Input Voltage Range, All Inputs . . . . . . . . . . . . . . . . . . -0.5V to 5.5V
Output Voltage Range, All Outputs . . . . . VOFF -0.5V to VON +0.5V
Thermal Resistance (Typical, Note 1)
JA (°C/W)
20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
140
IOUT (continuous, all 8 channels) . . . . . . . . . . . . . . . . . . . . . . 80mA
TAMBIENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
TJUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +150°C
TSTORAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a HIGH effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
Power
Supplies
VON = 22V, VOFF = -5V, TA = -40°C to +85°C Unless Otherwise Specified. Typical values tested at 25°C
DESCRIPTION
CONDITION
Recommended Operating Voltages
MIN
TYP
-5
(VOFF)
I(VON)
Supply Current
All Inputs low or high
No load
VON = VON1 + VON2
I(VOFF)
Supply Current
All Inputs low or high
No load
-4.0
-1.8
IIN
Input Leakage
Each Input low or high
High = 1.8V, Low = 0.8V
-8.0
± 2.0
VOH
High Level Output Voltage
IOH = -100A
VON = 22V
RL = 100pF in parallel with 5k
(VON - 1.5V)
21.2
VOL
Low Level Output Voltage
IOH = +100A
VOFF = -5V
RL = 100pF in parallel with 5k
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
tplh
Low to High Prop Delay
50% to 50%, Tested with
RL = 100pF in parallel with 5k
f = 50kHz
tphl
High to Low Prop Delay
ttlh
tthl
1.8
-4.3
MAX
UNIT
22
(VON)
V
4.0
mA
mA
8.0
A
V
(VOFF + 1.5V)
1.8
V
V
0.8
V
300
500
ns
Measured at 50% to 50%
f = 50kHz
RL = 100pF in parallel with 5k
250
500
ns
Rise Time
Measured at 10% to 90%
f = 50kHz
RL = 100pF in parallel with 5k
150
500
ns
Fall Time
Measured at 10% to 90%
f = 50kHz
RL = 100pF in parallel with 5k
210
500
ns
3
ISL24010
Pin Descriptions
PIN NUMBER
TSSOP-20
PIN NAME
EQUIVALENT
CIRCUIT
1
GND
4
Ground pin
2
IN1
1
Level shifter input 1
3
IN2
1
Level shifter input 2
4
IN3
1
Level shifter input 3
5
IN4
1
Level shifter input 4
6
IN5
1
Level shifter input 5
7
IN6
1
Level shifter input 6
8
IN7
1
Level shifter input 7
9
IN8
1
Level shifter input 8
10
VOFF
4
Negative output supply for all channels
11
VON2
4
Positive output supply for channels 7 and 8. VON2 is required to be greater than or equal to
VON1.
12
OUT8
3
Lever shifter output 8
13
OUT7
3
Lever shifter output 7
14
OUT6
2
Lever shifter output 6
15
OUT5
2
Lever shifter output 5
16
OUT4
2
Lever shifter output 4
17
OUT3
2
Lever shifter output 3
18
OUT2
2
Lever shifter output 2
19
OUT1
2
Lever shifter output 1
20
VON1
4
Positive output supply for channels 1 through 6. VON1 is required to be less than or equal to
VON2.
DESCRIPTION
VON1
VON2
OUT
OUT
VON2
IN
VOFF
Outputs 1-6
CIRCUIT 1.
VOFF
Outputs 7-8
CIRCUIT 2.
VON2
VON1
ESD CLAMP
VOFF
CIRCUIT 4.
4
GND
VOFF
CIRCUIT 3.
ISL24010
Typical Performance Curves TA = 25°C, Output load parallel RC (RL = 5k, CL = 100pF) unless otherwise specified.
10.0
12.0
VOFF
9.0
8.0
9.6
8.4
6.0
VON1 & 2 = 22V
5.0
VOFF = -5V
mA
mA
7.0
Input 50% Duty Cycle
4.0
7.2
VON1
6.0
VON1 & 2 = 22V
4.8
VON1
3.0
VOFF = -5V
3.6
2.0
Input 50% Duty Cycle
2.4
VON2
1.0
0.0
VOFF
10.8
VON2
1.2
0.0
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
FREQUENCY (kHz)
FREQUENCY (kHz)
FIGURE 1. SUPPLY CURRENT vs FREQUENCY 1 CHANNEL
TOGGELING
FIGURE 2. SUPPLY CURRENT vs FREQUENCY
4 CHANNELS TOGGELING
15.0
15.0
13.5
9.0
VON1 & 2 = 22V
10.5
VOFF = -5V
Input 50% Duty Cycle
7.5
9.0
VOFF
6.0
4.5
4.5
3.0
VON1 & 2 = 22V
VOFF = -5V
Input 50% Duty Cycle
7.5
6.0
VON2
1.5
0.0
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
FREQUENCY (kHz)
FREQUENCY (kHz)
FIGURE 3. SUPPLY CURRENT vs FREQUENCY
6 CHANNELS TOGGLING
FIGURE 4. SUPPLY CURRENT vs FREQUENCY
8 CHANNELS TOGGLING
350
350
Prop Delay
315
280
280
Fall Time
245
210
210
175
ns
ns
Prop Delay
315
Fall Time
245
Rise Time
105
70
20
Rise Time
VON1 & 2 = 20-40V
VON1 & 2 = 20-40V
105
VOFF = -5V
VOFF = -20V
70
Frequency 50kHz
100pF load
35
175
140
140
0
VOFF
3.0
VON2
1.5
0.0
VON1
12.0
mA
mA
10.5
13.5
VON1
12.0
22
24
26
Frequency 50kHz
100pF load
35
28
30
32
34
36
38
VON1 & VON2 (V D.C.)
FIGURE 5. RISE TIME, FALL TIME AND PROP DELAY vs
VON1 & VON2 VOLTAGE WITH VOFF = -5V
5
40
0
20
22
24
26
28
30
32
34
36
38
VON1 & VON2 (V D.C.)
FIGURE 6. RISE TIME, FALL TIME AND PROP DELAY vs
VON1 & VON2 VOLTAGE WITH VOFF = -20V
40
ISL24010
Typical Performance Curves TA = 25°C, Output load parallel RC (RL = 5k, CL = 100pF) unless otherwise specified. (Continued)
2000
1800
1600
2100
VON1 & 2 = 20-40V
VOFF = -5V
50kHz 50% Duty Cycle
1890
1470
1260
1000
ns
ns
1200
1800pF
800
600
1050
1800pF
840
VON1 & 2 = 20-40V
630
400
VOFF = -20V
420
100pF
200
0
22
24
26
28
30
32
34
36
38
0
40
20
22
24
26
VON1 & VON2 (V D.C.)
1800
1600
36
38
40
3300pF
1760
3300pF
1540
1320
1000
ns
ns
34
1980
1800pF
800
600
400
100pF
200
1100
1800pF
880
VON1 & 2 = 20-40V
660
VOFF = -20V
440
50kHz 50% Duty Cycle
100pF
220
20
22
24
26
28
30
32
34
36
38
0
40
20
22
24
26
VON1 & VON2 (V D.C.)
1500
VON1 & 2 = 20-40V
1200
VOFF = -5V
1050
50kHz 50% Duty Cycle
30
32
34
36
38
40
FIGURE 10. FALL TIME vs CAPACITANCE vs SUPPLY
VOLTAGE WITH VOFF = -20V
1500
1350
28
VON1 & VON2 (V D.C.)
FIGURE 9. FALL TIME vs CAPACITANCE vs SUPPLY
VOLTAGE WITH VOFF = -5V
1350
3300pF
1200
VON1 & 2 = 20-40V
VOFF = -5V
50kHz 50% Duty Cycle
3300pF
1050
900
900
750
ns
ns
32
FIGURE 8. RISE TIME vs CAPACITANCE vs SUPPLY
VOLTAGE WITH VOFF = -20V
1200
1800pF
600
750
450
300
300
150
150
100pF
20
22
24
26
28
30
32
34
36
38
VON1 & VON2 (V D.C.)
FIGURE 11. PROP DELAY vs CAPACITANCE vs SUPPLY
VOLTAGE WITH VOFF = -5V
6
1800pF
600
450
0
30
2200
VON1 & 2 = 20-40V
VOFF = -5V
50kHz 50% Duty Cycle
1400
0
28
VON1 & VON2 (V D.C.)
FIGURE 7. RISE TIME vs CAPACITANCE vs SUPPLY
VOLTAGE WITH VOFF = -5V
2000
100pF
50kHz 50% Duty Cycle
210
20
3300pF
1680
3300pF
1400
40
0
100pF
20
22
24
26
28
30
32
34
36
38
VON1 & VON2 (V D.C.)
FIGURE 12. PROP DELAY vs CAPACITANCE vs SUPPLY
VOLTAGE WITH VOFF = -20V
40
ISL24010
2V/DIV
Typical Performance Curves TA = 25°C, Output load parallel RC (RL = 5k, CL = 100pF) unless otherwise specified. (Continued)
Pulse Input
0
100pF
5V/DIV
1500pF
0
VON1 & 2 = 22V
VOFF = -5V
50kHz 50% Duty Cycle
2µs/DIV
FIGURE 13. TRANSIENT RESPONSE vs LOAD CAPACITANCE
Application Information
General
The ISL24010 is an Octal voltage level shifter. The part was
designed to level shifts a digital input signal to +22V and -5V
for TFT-LCD displays. The device is capable of level shifting
a CMOS logic signal between +40V and -20V.
Power Supply Decoupling
The ISL24010 requires a 0.1F decoupling capacitor as
close to the VON1, VON2 and VOFF power supply pins for a
large load equal to 5k in parallel with 100pF (Figure 16).
This will deduce any dv/dt between the different supplies and
prevent the internal ESD clamp from turning on and
damaging the part.
Input Pin Connections
Unused inputs must be tied to ground. Failure to tie unused
input pins to ground will result in a rail to rail oscillations on
the respective output pins and higher unwanted power
dissipation in the part. Under these conditions, the
temperature of the part could get very hot.
Limiting the Output Current
No output short circuit current limit exists on this part. All
applications need to limit the output current to less than
80mA. Adequate thermal heat sinking of the parts is also
required.
Application Diagram (TV)
Power Supply Sequence
The ISL24010 requires that VON2 be greater than or equal to
VON1 at all times. Therefore, if VON1 and Von 2 are different
supplies, then VON2 needs to be turned on before VON1.
The reason for this requirement is shown in Circuit 4 in the
Pin Description Table. The ESD protection diode between
VON2 and Von 1 will forward bias if VON1 becomes a diode
drop greater than VON2. Recommended power supply
sequence: VON2, VON1, VOFF then input logic signals.
The ESD protection scheme is based on diodes from the
pins to the VON2 supply and a dV/dt- triggered clamp. This
dV/dt triggered clamp imposes a maximum supply turn-on
slew rate of 10V/µs. This clamp will trigger if the supply
powers up too fast, causing amps of current to flow. Ground
and VON1 are treated as I/O pins with this protection
scheme. In applications where the dV/dt supply ramp could
exceed 10V/µs, such as hot plugging, additional methods
should be employed to ensure the rate of rise is not
exceeded.
Latch-up Proof
The ISL24010 is manufactured in a high voltage DI process
that isolates every transistor in it’s own tub making the part
latch-up proof.
7
DC/DC
CONVERTER
1.0F
1.0F
TIMING
CONTROLLER
VON1
VOFF
VON2
ISL24010
LEVEL
SHIFTER
1.0F
LCD PANEL
FIGURE 14. TYPICAL TV APPLICATION CIRCUIT
ISL24010
Application Diagram (Monitor)
VON SLICER
CIRCUIT
VON1
DC/DC
CONVERTER
VOFF
VON2
1.0µF
VOFF
VON1
VON2
1.0µF
TIMING
CONTROLLER
1.0µF
ISL24010
LEVEL
SHIFTER
LCD PANEL
FIGURE 15. TYPICAL MONITOR APPLICATION CIRCUIT WITH
SLICER TO REDUCE FLICKER
Test Circuit
VON1
1.0F
VON2
C1
IN1
1.0F
C2
OUT1
ISL24010
5k
OUT8
IN8
VOFF
100pF
C3
1.0F
If the output load is a series 200 resistor and a 3300pF
then C1, C2 and C3 can be reduced to 0.47pF.
INx
tPHL
tPLH
OUTx
tR
tF
FIGURE 16. TEST LOAD AND TIMING DEFINITIONS
8
ISL24010
Thin Shrink Small Outline Plastic Packages (TSSOP)
M20.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
SYMBOL
3
0.05(0.002)
-A-
INCHES
GAUGE
PLANE
-B1
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
B M
L
A
D
-C-
e

A2
A1
b
0.10(0.004) M
0.25
0.010
SEATING PLANE
c
0.10(0.004)
C A M
B S
MIN
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
MILLIMETERS
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.051
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.252
0.260
6.40
6.60
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
NOTES:
MAX

20
0o
20
7
8o
Rev. 1 6/98
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
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