DATASHEET

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DESIG
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Octal
Voltage
Level Shifter
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ISL24011
for TFT/LCD Panels
FN6196.2
High Voltage TFT-LCD Logic Driver
Features
The ISL24011 is a high voltage TFT-LCD logic driver with a
+40V and -20V (momentary absolute max) output voltage
swing capability. It is manufactured using Intersil’s
proprietary monolithic high voltage bipolar process and is
capable of driving a 4700pF load in 500ns.
• 0V to 5.5V (absolute max) Input Voltage Range
The ISL24011 will level shift a digital input signal to an output
voltage nearly equal to its output supply voltages. The
ISL24011 has 3 supplies. VON1 and VON2 are positive
supplies with a voltage range between +10V and +40V
(absolute max). VOFF is the negative supply with a voltage
range between -5V and -20V (absolute max). Outputs 1
through 6 are connected to VON1 and VOFF. Outputs 7 and 8
are connected to VON2 and VOFF. This configuration
enables outputs 1 through 6 to provide slicing to the row
drivers to reduce flicker, and outputs 7 and 8 to control
possible supply lines. VON2 should remain constant. It is
possible to tie VON1 and VON2 supplies together, if
independent control as described above is not desired.
VON2 is required to be greater than or equal to VON1 at all
times.
• 25mA Output Peak Current (all 8 channels)
The ISL24011 is available in a 20 Ld TSSOP package. It is
specified for operation over the -40°C to +85°C industrial
temperature range.
Ordering Information
PART
NUMBER
ISL24011IVZ
(Note)
PART
TEMP.
MARKING RANGE (°C)
24011IVZ
ISL24011IVZ-T 24011IVZ
(Note)
-40 to +85
-40 to +85
PACKAGE
PKG.
DWG. #
20 Ld TSSOP M20.173
(Pb-free)
20 Ld TSSOP M20.173
(Pb-free)
Tape & Reel
• +40V and -20V (momentary absolute max) Output Voltage
Range
• 10mA Output Continuous Current (all 8 channels)
• Rise/Fall Times 260ns/290ns
• Propagation Delay 230ns
• 50kHz Input Logic Frequency
• 20 Ld TSSOP Pb-Free Package
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• TFT-LCD panels
Pinout
ISL24011 (20 LD TSSOP)
TOP VIEW
GND
1
20 VON1
IN1
2
19 OUT1
IN2
3
18 OUT2
IN3
4
17 OUT3
IN4
5
16 OUT4
IN5
6
15 OUT5
IN6
7
14 OUT6
IN7
8
13 OUT7
IN8
9
12 OUT8
VOFF 10
11 VON2
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005-2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL24011
Functional Diagram
CONNECTED TO VON1
IN1
AND VOFF
CH1
OUT1
OUT2
CH2
IN2
OUT3
CH3
IN3
OUT4
CH4
IN4
OUT5
CH5
IN5
OUT6
CH6
IN6
CONNECTED TO VON2
IN7
CH7
OUT7
AND VOFF
CH8
OUT8
IN8
2
FN6196.2
March 28, 2006
ISL24011
Absolute Maximum Ratings (TA = 25°C)
Thermal Information
Driver Positive Supply Voltage Range, (VON) . . . . . . . . +5V to +40V
Power Supply Voltage Range, (VON to VOFF). . . . . . . +10V to +60V
Negative Supply Voltage Range, (VOFF) . . . . . . . . . . . . . -20V to -5V
Supply Turn-On Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 10V/µs
Input Voltage Range, All Inputs . . . . . . . . . . . . . . . . . . -0.5V to 5.5V
Output Voltage Range, All Outputs . . . . . VOFF -0.5V to VON +0.5V
ESD
HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6kV
MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV
Thermal Resistance (Typical, Note 1)
JA (°C/W)
20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
140
IOUT (continuous, all 8 channels) . . . . . . . . . . . . . . . . . . . . . . 80mA
TAMBIENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
TJUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +150°C
TSTORAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a HIGH effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VON = 22V, VOFF = -5V, TA = -40°C to +85°C Unless Otherwise Specified. Typical values tested at 25°C
DESCRIPTION
CONDITION
Power Supplies Recommended Operating Voltages
MIN
TYP
-5
(VOFF)
I(VON)
Supply Current
All Inputs low or high
No load
VON = VON1 + VON2
I(VOFF)
Supply Current
All Inputs low or high
No load
-8.0
-5.0
IIN
Input Leakage
Each Input low or high
High = 1.8V, Low = 0.8V
-10
± 3.5
(VON - 1.5V)
21.2
VOH
High Level Output Voltage IOH = -100A
VON = 22V
RL = 4700pF in parallel with 5k
VOL
Low Level Output Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
tplh
Low to High Prop Delay
50% to 50%, Tested with
RL = 4700pF in parallel with 5k
f = 50kHz
tphl
High to Low Prop Delay
ttlh
tthl
5.0
-4.3
IOH = +100A
VOFF = -5V
RL = 4700pF in parallel with 5k
MAX
UNIT
22
(VON)
V
8.0
mA
mA
10
µA
V
(VOFF + 1.5V)
1.8
V
V
0.8
V
190
400
ns
Measured at 50% to 50%
f = 50kHz
RL = 4700pF in parallel with 5k
230
400
ns
Rise Time
Measured at 10% to 90%
f = 50kHz
RL = 4700pF in parallel with 5k
260
400
ns
Fall Time
Measured at 10% to 90%
f = 50kHz
RL = 4700pF in parallel with 5k
290
500
ns
3
FN6196.2
March 28, 2006
ISL24011
Pin Descriptions
PIN NUMBER
TSSOP-20
PIN NAME
EQUIVALENT
CIRCUIT
1
GND
4
Ground pin
2
IN1
1
Level shifter input 1
3
IN2
1
Level shifter input 2
4
IN3
1
Level shifter input 3
5
IN4
1
Level shifter input 4
6
IN5
1
Level shifter input 5
7
IN6
1
Level shifter input 6
8
IN7
1
Level shifter input 7
9
IN8
1
Level shifter input 8
10
VOFF
4
Negative output supply for all channels
11
VON2
4
Positive output supply for channels 7 and 8. VON2 is required to be greater than or equal to VON1
12
OUT8
3
Lever shifter output 8
13
OUT7
3
Lever shifter output 7
14
OUT6
2
Lever shifter output 6
15
OUT5
2
Lever shifter output 5
16
OUT4
2
Lever shifter output 4
17
OUT3
2
Lever shifter output 3
18
OUT2
2
Lever shifter output 2
19
OUT1
2
Lever shifter output 1
20
VON1
4
Positive output supply for channels 1 through 6. VON1 is required to be less than or equal to
VON2
DESCRIPTION
VON2
IN
VOFF
OUTPUTS 1-6
CIRCUIT 1.
VON1
VON2
OUT
OUT
VOFF
OUTPUTS 7-8
CIRCUIT 2.
VOFF
CIRCUIT 3.
VON2
VON1
ESD CLAMP
GND
VOFF
CIRCUIT 4.
4
FN6196.2
March 28, 2006
ISL24011
Typical Performance Curves TA = 25°C, Output load parallel RC (RL = 5k, CL = 4700pF) unless otherwise specified.
60.0
25.0
22.5
VON1 & VON2 = 22V
20.0
VOFF = -5V
54.0
48.0
VOFF
INPUT 50% DUTY CYCLE
17.5
42.0
INPUT 50% DUTY CYCLE
VON1
36.0
(mA)
15.0
(mA)
VON1 & VON2 = 22V
VOFF = -5V
VON1
12.5
10.0
VOFF
30.0
24.0
18.0
7.5
5.0
12.0
VON2
VON2
6.0
2.5
0.0
10
15
20
25
30
35
40
45
50
55
60
65
70
0.0
10
75
15
20
25
30
FIGURE 1. SUPPLY CURRENT vs FREQUENCY 1 CHANNEL
TOGGLING
VON1 & VON2 = 22V
64.0
VOFF = -5V
56.0
INPUT 50% DUTY CYCLE
90.0
70.5
32.0
24.0
65
70
75
VON1 & VON2 = 22V
VOFF = -5V
INPUT 50% DUTY CYCLE
VON1
50.0
VOFF
40.0
10
15
20
25
30
35
40
45
50
55
60
65
70
VON2
10.0
0.0
10
75
15
20
25
30
FREQUENCY (kHz)
35
40
45
50
55
60
65
70
75
FREQUENCY (kHz)
FIGURE 3. SUPPLY CURRENT vs FREQUENCY
6 CHANNELS TOGGLING
FIGURE 4. SUPPLY CURRENT vs FREQUENCY
8 CHANNELS TOGGLING
500
500
VON1 & VON2 = 10-40V
450
VOFF = -5V
400
50kHz 10% DUTY CYCLE
FALL TIME
300
350
250
PROP DELAY
200
150
100
50
50
15
17
19
22
24
26
28
31
33
35
38
VON1 & VON2 (V)
FIGURE 5. RISE TIME, FALL TIME AND PROP DELAY vs
VON1 & VON2 VOLTAGE WITH VOFF = -5V
5
PROP DELAY
200
100
12
RISE TIME
250
150
10
FALL TIME
300
RISE TIME
(ns)
(ns)
60
20.0
VON2
8.0
0
55
30.0
16.0
350
50
60.0
VOFF
40.0
(mA)
(mA)
80.0
VON1
48.0
400
45
100.0
72.0
450
40
FIGURE 2. SUPPLY CURRENT vs FREQUENCY
4 CHANNELS TOGGLING
80.0
0.0
35
FREQUENCY (kHz)
FREQUENCY (kHz)
40
0
10
VON1 & VON2 = 10-40V
VOFF = -20V
50kHz 10% DUTY CYCLE
12
15
17
19
22
24
26
28
31
33
35
38
40
VON1 & VON2 (V)
FIGURE 6. RISE TIME, FALL TIME AND PROP DELAY vs
VON1 & VON2 VOLTAGE WITH VOFF = -20V
FN6196.2
March 28, 2006
ISL24011
Typical Performance Curves TA = 25°C, Output load parallel RC (RL = 5k, CL = 4700pF) unless otherwise specified. (Continued)
400
500
360
450
320
400
280
350
4700pF
200
3300pF
160
250
3300pF
200
120
150
1800pF
VON1 & VON2 = 10-40V
80
50kHz 10% DUTY CYCLE
10
12
15
17
19
22
24
26
28
31
33
35
38
1800pF
100 VON1 & VON2 = 10-40V
VOFF = -20V
50
50kHz 10% DUTY CYCLE
0
10 12 15 17 19 22 24
VOFF = -5V
40
0
4700pF
300
(ns)
(ns)
240
40
VON1 & VON2 (V)
FIGURE 7. RISE TIME vs CAPACITANCE vs SUPPLY
VOLTAGE WITH VOFF = -5V
500
360
450
320
400
(ns)
(ns)
1800pF
15
17
19
22
40
38
40
VOFF = -20V
24
26
28
31
33
35
38
0
40
50kHz 10% DUTY CYCLE
10
12
15
17
19
VON1 & VON2 (V)
300
270
270
240
240
26
28
31
180
120
(ns)
3300pF
1800pF
120
1800pF
60
VON1 & VON2 = 10-40V
60
VON1 & VON2 = 10-40V
30
VOFF = -5V
30
VOFF = -20V
26
28
31
33
35
38
VON1 & VON2 (V)
FIGURE 11. PROP DELAY vs CAPACITANCE vs SUPPLY
VOLTAGE WITH VOFF = -5V
6
35
3300pF
150
90
90
50kHz 10% DUTY CYCLE
0
10 12 15 17 19 22 24
33
4700pF
210
4700pF
150
24
FIGURE 10. FALL TIME vs CAPACITANCE vs SUPPLY
VOLTAGE WITH VOFF = -20V
300
180
22
VON1 & VON2 (V)
FIGURE 9. FALL TIME vs CAPACITANCE vs SUPPLY
VOLTAGE WITH VOFF = -5V
210
38
1800pF
VON1 & VON2 = 10-40V
50
50kHz 10% DUTY CYCLE
12
40
3300pF
250
100
VOFF = -5V
10
38
4700pF
150
VON1 & VON2 = 10-40V
40
35
200
120
80
33
300
3300pF
200
160
(ns)
31
350
4700pF
240
0
28
FIGURE 8. RISE TIME vs CAPACITANCE vs SUPPLY
VOLTAGE WITH VOFF = -20V
400
280
26
VON1 & VON2 (V)
40
0
50kHz 10% DUTY CYCLE
10
12
15
17
19
22
24
26
28
31
33
35
VON1 & VON2 (V)
FIGURE 12. PROP DELAY vs CAPACITANCE vs SUPPLY
VOLTAGE WITH VOFF = -20V
FN6196.2
March 28, 2006
ISL24011
2V/DIV
Typical Performance Curves TA = 25°C, Output load parallel RC (RL = 5k, CL = 4700pF) unless otherwise specified. (Continued)
PULSE INPUT
0
4700pF
5V/DIV
1800pF
0
VON1 & VON2 = 22V
VOFF = -5V
50kHz 10% DUTY CYCLE
400ns/DIV
FIGURE 13. TRANSIENT RESPONSE vs LOAD CAPACITANCE
Application Information
General
The ISL24011 is an octal voltage level shifter. The part was
designed to level shift a digital input signal to +22V and -5V
for TFT-LCD displays and is capable of level shifting input
logic signals (0V to 5.5V) to outputs as large as +40V and
-20V.
Power Supply Decoupling
The ISL24011 requires a 1.0µF decoupling capacitor as
close to the VON1, VON2 and VOFF power supply pins, as
possible, for a large load equal to 5k in parallel with
4700pF (Figure 16). This will reduce any dv/dt between the
different supplies and prevent the internal ESD clamp from
turning on and damaging the part.
For lighter loads such as a series 200 resistor and a
3300pF capacitance, the decoupling capacitors can be
reduced to 0.47µF.
Latch-up Proof
The ISL24011 is manufactured in a high voltage DI process
that isolates every transistor in its own tub making the part
latch-up proof.
Input Pin Connections
Unused inputs must be tied to ground. Failure to tie unused
input pins to ground will result in rail to rail oscillations on the
respective output pins and higher unwanted power
dissipation in the part. Under these conditions, the
temperature of the part could get very hot.
Limiting the Output Current
No output short circuit current limit exists on this part. All
applications need to limit the output current to less than
80mA. Adequate thermal heat sinking of the parts is also
required.
Application Diagram (TV)
Power Supply Sequence
The ISL24011 requires that VON2 be greater than or equal to
VON1 at all times. Therefore, if VON1 and VON2 are different
supplies, then VON2 needs to be turned on before VON1.
The reason for this requirement is shown in Circuit 4 in the
Pin Description Table. The ESD protection diode between
VON2 and VON1 will forward bias if VON1 becomes a diode
drop greater than VON2. Recommended power supply
sequence: VON2, VON1, VOFF, then input logic signals.
The ESD protection scheme is based on diodes from the
pins to the VON2 supply and a dv/dt-triggered clamp. This
dv/dt-triggered clamp imposes a maximum supply turn-on
slew rate of 10V/µs. This clamp will trigger if the supply
powers up too fast, causing amps of current to flow. Ground
and VON1 are treated as I/O pins with this protection
scheme. In applications where the dv/dt supply ramp could
exceed 10V/µs, such as hot plugging, additional methods
should be employed to ensure the rate of rise is not
exceeded.
7
DC/DC
CONVERTER
1.0µF
1.0µF
TIMING
CONTROLLER
VON1
VOFF
VON2
ISL24011
LEVEL
SHIFTER
1.0µF
LCD PANEL
FIGURE 14. TYPICAL TV APPLICATION CIRCUIT
FN6196.2
March 28, 2006
ISL24011
Application Diagram (Monitor)
Test Circuit
VON1
VON1
DC/DC
CONVERTER
VOFF
VON SLICER
CIRCUIT
1.0µF
VON2
1.0µF
C1
IN1
VOFF
C2
OUT1
ISL24011
OUT8
5k
4700pF
1.0µF
VOFF
ISL24011
LEVEL SHIFTER
1.0µF
IN8
VON1
VON2
1.0µF
TIMING
CONTROLLER
VON2
C3
1.0µF
LCD PANEL
If the output load is a series 200 resistor and a 3300pF
then C1, C2 and C3 can be reduced to 0.47pF.
INx
tPLH
FIGURE 15. TYPICAL MONITOR APPLICATION CIRCUIT WITH
SLICER TO REDUCE FLICKER
tPHL
OUTx
tR
tF
FIGURE 16. TEST LOAD AND TIMING DEFINITIONS
8
FN6196.2
March 28, 2006
Thin Shrink Small Outline Plastic Packages (TSSOP)
M20.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
SYMBOL
3
0.05(0.002)
-A-
INCHES
GAUGE
PLANE
-B1
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
B M
0.25
0.010
SEATING PLANE
L
A
D
-C-
e

A1
b
A2
c
0.10(0.004)
0.10(0.004) M
C A M
B S
MIN
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
MILLIMETERS
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.051
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.252
0.260
6.40
6.60
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
NOTES:
MAX

20
0o
20
7
8o
Rev. 1 6/98
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
FN6196.2
March 28, 2006
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