EL5525I Demo Board ® Technical Brief February 23, 2004 TB427 Control Software The EL5525I demo board is designed for demonstrating the operation of Intersil's high precision reference voltage generator, EL5525. For detail description, please refer to the data sheet. A parallel port Visual Basic program is used to drive the SDI, SCLK, ENA pins for the channel and voltage selection. A Visual basic program is used to drive the parallel port to output the data stream for SDI and SCLK inputs. To install the software, just copy the EL5525.exe to your window desktop. If your operating system is win98, copy the files "ntport.dll and zntport.sys" to the directory: C:\windows\system. If your operating system is NT, Win2000 or WinXP, copy the files "ntport.dll, zntport.sys, comdlg32.ocx and tabctl32.ocx" to the directory: C:\winnt\system32. 18 Channel Circuit Description Please refer to the demo board circuit.. On the board, VS is the supply voltage (5V to 16.5V). VSD is the digital supply (3.3V to 5V). REFH is the high reference output voltage (REFL < REFH ≤ VS). REFL is the low reference output voltage (0 ≤ REFL < REFH). In order to save power supplies, the REFH and REFL are generated from Intersil's EL5220IY amplifier. REFH can be adjusted by changing R18 and REFL can be adjusted by changing R19. By default setting, the R18 and R19 are set to have a 10V REFH and 1V REFL. The user can confirm the voltages by measuring the REFH and REFL pins on J1 and J2. Demo Board Control (18 Channel) Click the EL5525I.exe icon on your windows desktop, a control panel shows up. On the panel, you can set your reference high and reference low voltage. You can set the voltage for each channel. Click the SendAll or Send button and the data will be sent out through the parallel port. TEST SETUP R20 to R26, R28 to R34 and R41 to R46 are 1.5K load resistors. C6, C12 and C18 are 0.1µF local bypass capacitors. C1 to C5, C7, C8, C10, C12 to C15 and C26 to C31 are 180pF load capacitors. If bigger capacitors are required, then, a serial resistor (20Ω to 100Ω) should be use between the output and the capacitor. 1. Apply a 15V to VS, 5V to VSD and ground to GND. 2. Confirm the voltages of REFH and REFL on J1 and J2. Adjust R18 until REFH = 10V and R19 until REFL = 1V. 3. Connect the parallel cable from the computer to the board. 4. Program and confirm the output voltages on each channel. FIGURE 1. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. Schematics REFL VSD VS J1A J1B BUSS J1C J1D SDI J1E SCLK J1G LOAD J1H VS VSD REFH J1I J4A EXT_OSC J1J J4B VSD J4C J4D R2 open D2 MMBD4148 D1 MMBD4148 R4 open R6 open D3 MMBD4148 SDO LOAD SDI J4E SCLK SCLK J4F J4G R24 LOAD LOAD J4H 1K R25 J3C J4I SDI EXT_OSC 1K R27 J3D J4J SCLK 1K J3R J3S R16 J3T 10K BG 3 REFH SHORT J3W U2A 1 1 J3X R17 10K VS J3Y 8 VS D4 BAT42 REFL 6 5 R19 10K C23 PARALLEL PORT 3 JP1 EL5220CY 2 J3V 2 2 R18 10K J3U U2B 7 EL5220CY 1 3 JP2 SHORT .1uf U2C VSD EL5220CY VS VSD REFH REFL + C17 4.7uf + C16 4.7uf + C25 OPEN C19 OPEN + C24 OPEN C22 OPEN GND2 GND3 GND4 Title EL5525IRE DEMO BOARD GND Size: Date: 7/2/03 FIGURE 2. Revision: B Sheet 1 of 2 Technical Brief 427 J3B 4 2 J1F Schematics (Continued) VSD VS REFLREFH BUSS U1 LOAD 1 SDI 2 SCLK 3 SDO 4 EXT_OSC S1 EXT_OSC SDI OUTB SCLK OUTC SDO GND 38 36 3 8 EXT-OSC OUTD 34 9 OSC_SEL VS OUTE VSD OUTF NC OUTG 32 10 11 NC OUTH OSC_SEL OUTI VS GND 12 13 R48 14 BG 15 J2H 0.0 J2I R9 J2J J2K R10 J2L R11 J2M 0.0 29 J2N R12 0.0 J2O 28 REFH OUTJ REFL OUTK GND OUTL 27 CAP GND 26 J2P R13 J2Q 0.0 J2R R14 J2S 0.0 25 R15 J2T 0.0 J2U 24 J2V 16 17 VS OUTM NC OUTN OUTR OUTO 23 18 19 OUTQ OUTP 22 R35 J2W 0.0 J2X R36 J2Y 0.0 21 20 R37 J2Z 0.0 J2[ R38 J2\ 0.0 R39 J2] 0.0 J2^ R40 J2_ 0.0 J2` J2a J2b J2c SDO R46 C31 1.5K 180pf R45 C30 1.5K 180pf R44 C29 1.5K 180pf R43 C28 1.5K 180pf R42 C27 1.5K 180pf R41 C26 1.5K 180pf R34 C15 1.5K 180pf R33 C14 1.5K 180pf R32 C13 1.5K 180pf R31 C12 1.5K 180pf R30 C10 1.5K 180pf R29 1.5K C8 180pf R28 1.5K C7 180pf R26 1.5K C5 180pf R23 1.5K C4 180pf R22 1.5K C3 180pf R21 1.5K C2 180pf R20 1.5K C1 180pf EXT_OSC All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com J2e J2f LOAD J2g SCLK FIGURE 3. J2d SDI J2h Technical Brief 427 VS .1uf R49 OPEN J2G R8 0.0 30 REFL OPEN C11 J2E R7 REFH OPEN C21 .1uf J2D 0.0 31 VS BG J2C R5 0.0 33 S2 C9 10pf R47 J2B 0.0 35 .1uf C20 10pf J2A R3 0.0 VSD 7 C32 10pf R1 0.0 37 VS 6 C18.1uf OUTA J2F 5 C6 EL5525CR ENA