DATASHEET

SIGNS
R NEW DE
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MME
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RECOMMEDataIS
Sheet
L9 7 6 4 5 A
EL7520, EL7520A
July 12, 2005
FN7318.0
4-Channel DC/DC Controller
Features
EL7520 and EL7520A are 4-channel DC/DC controllers that
provide a complete power supply system for TFT-LCD
applications. They consist of a 1MHz PWM boost controller,
which generates the main voltage for the column driver, and
three LDO controllers for VON, VOFF, and VLOGIC supplies.
They also include integrated start-up sequence and start-up
delay control.
• Complete TFT-LCD supply controller
- 1MHz PWM boost controller
- VON LDO controller
- VOFF LDO controller
- Logic supply LDO controller
EL7520 and EL7520A operate from 3V to 5.5V. The boost
controller can drive a wide range of output current
depending on the external FET. It can be programmed to
operate in either P-mode for fast transient response or PImode for improved load regulation. The EL7520 and
EL7520A also integrate fault protection for all four output
channels. When a fault is detected, the device is latched off
until either the input supply voltage or enable is cycled.
Therefore, they are ideal to use in any size of TFT-LCD
panels.
The EL7520 and EL7520A are available in a 20 Ld 4x4 QFN
package with maximum height of 0.9mm and is specified for
operation of the -40°C to +85°C temperature range.
• Integrated start-up sequence for VLOGIC/VBOOST, VOFF,
VON or VLOGIC, VOFF, VBOOST, VON
- VLOGIC permanently enabled in 'A version (EL7520A)
• Programmable sequence delay
• In-rush current control
• Fully fault protected
• Thermal shutdown
• Internal soft-start
• 3V to 5.5V VDD
• 20 Ld 4x4 QFN package
• Low cost
• Pb-Free plus anneal available (RoHS compliant)
Ordering Information
Applications
PACKAGE
(Pb-FREE)
TAPE &
REEL
PKG.
DWG. #
• LCD monitors (15”+)
EL7520ILZ
20 Ld 4x4 QFN
-
MDP0046
• LCD-TV (up to 40”+)
EL7520ILZ-T7
20 Ld 4x4 QFN
7”
MDP0046
• Notebook displays (up to 16”)
EL7520ILZ-T13
20 Ld 4x4 QFN
13”
MDP0046
• Industrial/medical LCD displays
EL7520AILZ
20 Ld 4x4 QFN
-
MDP0046
EL7520AILZ-T7
20 Ld 4x4 QFN
7”
MDP0046
EL7520AILZ-T13
20 Ld 4x4 QFN
13”
MDP0046
16 DRVP
17 EN
18 VDD
EL7520 AND EL7520A
(20 LD 4X4 QFN)
TOP VIEW
19 VDDP
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Pinout
20 PG
CDLY 1
15 FBP
DRVB 2
14 DRVL
THERMAL
PAD
PGND 3
13 FBL
12 DRVN
ISAD 4
ISIN 5
1
VREF 10
CINT 9
FBB 8
DELB 6
11 FBN
SGND 7
PART NUMBER
(NOTE)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL7520, EL7520A
Absolute Maximum Ratings (TA = 25°C)
Thermal Information
VDELB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25V
VDRVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
VDRVN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20V
VDDP, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
Thermal Resistance (Typical, Notes 1, 2) JA (°C/W) JC (°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . .
40
7.5
VDRVL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Continuous Junction Temperature . . . . . . . . . . . . . 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
VDD = 5V, VBOOST = 11V, ILOAD = 40mA, VON = 15V, VOFF = -5V, VLOGIC = 2.5V, over temperature from 40°C to 85°C, unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
5.5
V
1.6
2.5
mA
5
30
µA
640
800
µA
900
1000
1100
kHz
1.19
1.215
1.235
V
1.187
1.215
1.238
V
SUPPLY
VS
Supply Voltage
IS
Quiescent Current
3
Enabled, LX not switching
Disabled, EL7520
Disabled, EL7520A
FOSC
Oscillator Frequency
BOOST
VREF
Reference Voltage
CREF
VREF Capacitor
VFBB
Feedback Reference Voltage
VF_FBB
FBB Fault Trip Point
DMAX
Maximum Duty Cycle
TA = 25°C
100
TA = 25°C
1.192
1.205
1.218
V
1.188
1.205
1.222
V
VFBB falling
1
%
Test with 24m RDS(ON) MOSFET,
ILOAD = 400mA
90
Feedback Input Bias Current
PI mode, VFBB = 1.35V
50
VBOOST/
VIN
Line Regulation
CINT = 2.2nF, IOUT = 200mA
VIN = 3V to 5.5V
VBOOST/
IBOOST
Load Regulation - “P” Mode
CINT pin strapped to VDD
VBOOST/
IBOOST
Load Regulation - “PI” Mode
IOUT = 10mA to 200mA
I(VREF)
VCINT_T
V
85
Boost Efficiency
Eff
nF
CINT Pl Mode Select Threshold
%
500
nA
0.05
%/V
3
%
0.1
%
4.7
4.8
V
VON LDO
FBP Regulation Voltage
IDRVP = 0.2mA, TA = 25°C
1.181
1.211
1.229
V
IDRVP = 0.2mA
1.177
1.211
1.233
V
FBP Fault Trip Point
VFBP falling
0.95
1
1.05
V
IFBP
FBP Input Bias Current
VFBP = 1.35V
-250
250
nA
GMP
FBP Effective Transconductance
VDRVP = 25V, IDRVP = 0.2 to 2mA
VFBP
VF_FBP
2
50
mS
FN7318.0
July 12, 2005
EL7520, EL7520A
Electrical Specifications
VDD = 5V, VBOOST = 11V, ILOAD = 40mA, VON = 15V, VOFF = -5V, VLOGIC = 2.5V, over temperature from 40°C to 85°C, unless otherwise specified. (Continued)
PARAMETER
VON/I(VON)
IDRVP
IL_DRVP
DESCRIPTION
VON Load Regulation
CONDITION
MIN
I(VON) = 0mA to 20mA
DRVP Sink Current
VFBP = 1.1V, VDRVP = 25V
DRVP Leakage Current
VFBL = 1.5V, VDRVL = 35V
FBN Regulation Voltage
IDRVN = 0.2mA, TA = 25°C
TYP
MAX
-0.5
2
UNIT
%
4
mA
0.1
5
µA
0.173
0.203
0.233
V
VOFF LDO
VFBN
IDRVN = 0.2mA
0.171
0.203
0.235
V
FBN Fault Trip Point
VFBN falling
0.38
0.4
0.48
V
IFBN
FBN Input Bias Current
VFBN = 1.25V
-250
250
nA
GMN
FBN Effective Transconductance
VDRVN = -6V, IDRVN = 0.2mA to 2mA
VOFF/
I(VOFF)
VOFF Load Regulation
I(VOFF) = 0mA to 20mA
IDRVN
DRVN Source Current
VFBN = 0.3V, VDRVN = -6V
DRVN Leakage Current
VFBN = 0V, VDRVN = -20V
FBL Regulation Voltage
IDRVL = 1mA, TA = 25°C
IDRVL = 1mA
VF_FBN
IL_DRVN
2
50
mS
-0.15
%
4
mA
0.1
5
µA
1.176
1.2
1.224
V
1.174
1.2
1.226
V
1
1.05
V
500
nA
VLOGIC LDO
VFBL
FBL Fault Trip Point
VFBL falling
0.90
IFBL
FBL Input Bias Current
VFBL = 1.25V
-500
GML
FBL Effective Transconductance
VDRVL = 2.5V, IDRVP = 1mA to 8mA
200
mS
VLOGIC Load Regulation
I(VLOGIC) = 0mA to 500mA
-0.5
%
DRVL Sink Current
VFBL = 1.1V, VDRVL = 2.5V
16
mA
DRVL Leakage Current
VFBL = 1.5V, VDRVL = 5.5V
0.1
tON
Turn On Delay
CDLY = 0.1µF
30
ms
tSS
Soft-start Time
CDLY = 0.1µF
2
ms
tDEL1
Delay Between AVDD and VOFF
CDLY = 0.1µF
10
ms
tDEL2
Delay Between VON and VOFF
CDLY = 0.1µF
17
ms
tDEL3
Delay Between VOFF and Delayed
VBOOST
CDLY = 0.1µF
10
ms
IDELB
DELB Pull-down Current
VDELB > 0.6V
50
µA
VDELB < 0.6V
1.4
mA
100
nF
VF_FBL
VLOGIC/
I(VLOGIC)
IDRVL
IL_DRVL
5
5
µA
SEQUENCING
CDEL
Delay Capacitor
FAULT DETECTION
TFAULT
Fault Time Out
OT
Over-temperature Threshold
IPG
PG Pull-down Current
CDLY = 0.1µF
50
ms
140
°C
VPG > 0.6V
15
µA
VPG < 0.6V
1.7
mA
LOGIC
VHI
Logic High Threshold
VLO
Logic Low Threshold
ILOW
Logic Low bias Current
-1
IHIGH
Logic High bias Current
12
3
2.2
V
0.8
V
0.1
1
µA
18
24
µA
FN7318.0
July 12, 2005
EL7520, EL7520A
Typical Performance Curves
100
100
VIN = 5V
90
EFFICIENCY (%)
EFFICIENCY (%)
VIN = 5V
VIN = 3V
80
70
VIN = 3V
80
70
60
0
500
1000
IOUT (mA)
60
1500
0
0
0
-0.5
-0.01
-1
-0.015
-1.5
-0.02
-2
-0.025
LOAD REGULATION (%)
-0.005
-0.03
2
3
4
400
600
800
1000
1200
5
VIN = 3V
-0.05
-0.1
VIN = 5V
-0.15
-0.2
-0.25
-0.3
-0.35
PI MODE
-2.5
1
200
FIGURE 2. VBOOST EFFICIENCY vs IOUT (P MODE)
P MODE
0
0
IOUT (mA)
FIGURE 1. VBOOST EFFICIENCY vs IOUT (PI MODE)
LINE REGULATION (%)
90
-0.4
6
0
500
1000
1500
IOUT (mA)
VIN (V)
FIGURE 4. VBOOST LOAD REGULATION (PI MODE)
FIGURE 3. VBOOST LINE REGULATION
0
-1
LOAD REGULATION (%)
LOAD REGULATION (%)
0
VIN = 3V
-2
VIN = 5V
-3
-4
-5
-6
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
0
200
400
600
800
1000
1200
IOUT (mA)
FIGURE 5. VBOOST LOAD REGULATION (P MODE)
4
0
20
40
60
80
IOUT (mA)
FIGURE 6. VON LOAD REGULATION
FN7318.0
July 12, 2005
EL7520, EL7520A
(Continued)
0
0
-0.2
-0.2
LOAD REGULATION (%)
LOAD REGULATION (%)
Typical Performance Curves
-0.4
-0.6
-0.8
-1
-1.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
0
20
40
60
80
0
100
100
200
300
400
500
600
700
IOUT (mA)
IOUT (mA)
FIGURE 7. VOFF LOAD REGULATION
FIGURE 8. VLOGIC LOAD REGULATION
VCDLY
VCDLY
EN
VBOOST
VLOGIC
VLOGIC
CDLY=0.1µF
VREF
TIME (20ms/DIV)
FIGURE 9. EL7520 START-UP SEQUENCE
CDLY=0.1µF
VREF
TIME (20ms/DIV)
FIGURE 10. EL7520 START-UP SEQUENCE
VBOOST-DELAY
VBOOST
VLOGIC
VLOGIC
VOFF
VOFF
CDLY=0.1µF
CDLY=0.1µF
VON
VON
TIME (10ms/DIV)
FIGURE 11. EL7520 START-UP SEQUENCE
5
TIME (20ms/DIV)
FIGURE 12. EL7520 START-UP SEQUENCE
FN7318.0
July 12, 2005
EL7520, EL7520A
Typical Performance Curves
(Continued)
VCDLY
VCDLY
VBOOST
EN
VLOGIC
VLOGIC
VREF
VREF
CDLY=0.1µF
CDLY=0.1µF
TIME (20ms/DIV)
TIME (20ms/DIV)
FIGURE 13. EL7520A START-UP SEQUENCE
FIGURE 14. EL7520A START-UP SEQUENCE
VBOOST
VBOOST-DELAY
VLOGIC
VLOGIC
VOFF
VOFF
VON
VON
CDLY=0.1µF
CDLY=0.1µF
TIME (20ms/DIV)
TIME (20ms/DIV)
FIGURE 16. EL7520A START-UP SEQUENCE
FIGURE 15. EL7520A START-UP SEQUENCE
0.5µs/DIV
FIGURE 17. LX WAVEFORM-DISCONTINUOUS MODE
6
FN7318.0
July 12, 2005
EL7520, EL7520A
Typical Performance Curves
(Continued)
0.5µs/DIV
FIGURE 18. LX WAVEFORM-CONTINUOUS MODE
CH1=VBOOST, 100mV/DIV
CH4=LOAD CURRENT, 200mA/DIV
0.2ms/DIV
FIGURE 20. VBOOST TRANSIENT RESPONSE
CH1=VON, 100mV/DIV
CH4=LOAD CURRENT, 50mA/DIV
50µs/DIV
FIGURE 22. VON TRANSIENT RESPONSE
7
20mV/DIV
FIGURE 19. VBOOST OUTPUT VOLTAGE RIPPLE
CH1=VLOGIC, 20mV/DIV
CH4=LOAD CURRENT, 100mA/DIV
50µs/DIV
FIGURE 21. VLOGIC TRANSIENT RESPONSE
CH1=VOFF, 50mV/DIV
CH4=LOAD CURRENT, 50mA/DIV
50µs/DIV
FIGURE 23. VOFF TRANSIENT RESPONSE
FN7318.0
July 12, 2005
EL7520, EL7520A
Pin Descriptions
PIN NUMBER
PIN NAME
FUNCTION DESCRIPTION
1
CDLY
With a capacitor connected from this pin to GND sets the delay time for start-up sequence and sets the fault
timeout time
2
DRVB
Gate driver output for the external N channel switch; the pulse voltage follows the input voltage
3
PGND
Power GND
4
ISAD
With a resistor connected from this pin to GND sets the current limit of the external N channel FET
5
ISIN
Sense the drain voltage of the external N channel FET and connected to the internal current limit comparator
6
DELB
Active low control output for optional delay control for external VBOOST P channel FET; when fault is detected,
this pin goes to high
7
SGND
Low noise signal ground
8
FBB
Boost regulator voltage feedback input pin; regulates to 1.2V nominal
9
CINT
VBOOST integrator output, connect 2.2nF to analog GND for PI mode or connect to VREF for P mode operation
10
VREF
Bandgap voltage bypass terminal; bypass with a 0.1µF to analog GND; can be used as charge pump reference
11
FBN
12
DRVN
13
FBL
14
DRVL
Logic LDO base drive; open drain of an internal N channel MOSFET
15
FBP
Positive LDO voltage feedback input pin; regulates to 1.2V nominal
16
DRVP
17
EN
18
VDD
19
VDDP
20
PG
Negative LDO voltage feedback input pin; regulates to 0.2V nominal
Negative LDO base drive; open drain of an internal P channel MOSFET
Logic LDO voltage feedback input pin; regulates to 1.2V nominal
Positive LDO base drive; open drain of an internal N channel MOSFET
Enable pin for the chip; high enable; low disabled
Positive supply for all internal circuitry except DRVB
Positive supply for external N channel FET gate drive (DRVB)
Output gate drive of the external fault protection P channel FET; when chip is disabled or when a fault has
been detected, this pin is high
8
FN7318.0
July 12, 2005
EL7520, EL7520A
Typical Application
LX
NODE 1
Q1
VIN
L1 6.8µH
1000pF
C1
C0
R0
500k
C3
10µF
D1
10µFx2
CDELAY DELB
R20
R13
7K
EN
Q11
DRVP
R12
10K
0.1µF
20K
C22
230K
R11
DRVL
C24
C15
1µF
C12
0.1µF
D11
20V
VON
0.1µF
LX
Q21
DRVN
R42
21.7K
R41
C25
0.1µF
R22
FBN
FBL
10µF
D12
3K
500
C31
C14
0.1µF
R23
Q31
2.5V
R16
20K
FBP
VREF
VREF
R43
VLGC
C11
0.1µF
C13
0.1µF
C23 2.2nF
VDD
4.7µF
0.1µF
LX
200K
CINT
R7
C41
0.1µF
R8
10K
ISAD
R6
NODE 1
0.01µF
FBB
C7
10
C6
C9
R1
7.5K
DRVB
0.1µF
C16
C2
1M
10µF
R2
ISIN
VDDP
C10
0.1µF
R9
62.5K
Q2
PG
12V
VBOOST
Q3
20K
20K
SGND
PGND
104K
R21
D21
-8V
VOFF
C20
4.7µF
VREF
Applications Information
TABLE 1. RECOMMENDED COMPONENTS (Continued)
The EL7520 and EL7520A provide a multiple output power
supply solution for TFT-LCD applications. The system
consists of a high efficiency boost controller and three low
cost linear-regulator controllers (VON, VOFF, and VLOGIC).
DESIGNATION
Q1
-2.4 -20V P-channel 1.8V specified
PowerTrench MOSFET (SuperSOT-3)
Fairchild FDN304P
The block diagram of the whole part is shown in Figure 24.
Table 1 lists the recommended components.
Q2
6.3A 30V single N-channel logic level
PowerTrench MOSFET (SOT-23)
Fairchild FDC655AN
Q3
-2A –30V single P-channel logic level
PowerTrench MOSFET (SuperSOT-3)
Fairchild FDN360P
TABLE 1. RECOMMENDED COMPONENTS
DESIGNATION
DESCRIPTION
DESCRIPTION
C1, C2, C3, C31
10µF, 16V, X7R ceramic capacitor (1206)
TDK C3216X7R1C106M
Q11
200mA 40V PNP amplifier (SOT-23)
Fairchild MMBT3906
C20
4.7µF, 16V X5R ceramic capacitor (1206)
TDK C3216X5R1A475K
Q21
200mA 40V NPN amplifier (SOT-23)
Fairchild MMBT3904
C15
1µF, 25V X7R ceramic capacitor (1206)
TDK C3216X7R1E105K
Q31
1A 30V PNP low saturation amplifier (SOT-23)
Fairchild FMMT549
D1
1A 20V low leakage schottky rectifier (CASE
457-04) ON SEMI MBRM120ET3
D11, D12, D21
200mA 30V schottky barrier diode (SOT-23)
Fairchild BAT54S
L1
6.8mH 1.3A inductor
TDK SLF6025T-6R8M1R3-PF
9
FN7318.0
July 12, 2005
EL7520, EL7520A
VREF
REFERENCE
GENERATOR
OSCILLATOR
SLOPE
COMPENSATION
LX
OSC
PWM
LOGIC
CONTROLLER

DRVB
BUFFER
VOLTAGE
AMPLIFIER
FBB
GM
AMPLIFIER
ISIN
CINT
CURRENT
AMPLIFIER
UVLO
COMPARATOR
CURRENT LIMIT
COMPARATOR
SHUTDOWN
& STARTUP
CONTROL
EN
VREF
CURRENT
LIMIT REF
GENERATOR
ISAD
SS
+
DRVP
BUFFER
THERMAL
SHUTDOWN
FBP
UVLO
COMPARATOR
SS
+
DRVN
SS
0.2V
-
VREF
+
DRVL
-
BUFFER
BUFFER
FBN
0.4V
FBL
UVLO
COMPARATOR
UVLO
COMPARATOR
FIGURE 24. BLOCK DIAGRAM
Boost Converter
The main boost converter is a current mode PWM controller
operating at a fixed frequency. The 1MHz switching
frequency enables the use of low profile inductor and
multilayer ceramic capacitors, which results in a compact,
low-cost power system for LCD panel design.
The boost converter can operate in continuous or
discontinuous inductor current mode. The EL7520 and
EL7520A are designed for continuous current mode, but
they can also operate in discontinuous current mode at light
load. In continuous current mode, current flows continuously
in the inductor during the entire switching cycle in steady
state operation. The voltage conversion ratio in continuous
current mode is given by:
V BOOST
1
------------------------ = ------------1–D
V IN
Figure 25 shows the function diagram of the boost controller.
It uses a summing amplifier architecture consisting of GM
stages for voltage feedback, current feedback and slope
compensation. A comparator looks at the peak inductor
current cycle by cycle and terminates the PWM cycle if the
current limit is reached.
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 60k is recommended.
The boost converter output voltage is determined by the
following equation:
R1 + R2
V BOOST = ---------------------  V REF
R1
Where D is the duty cycle of switching MOSFET.
10
FN7318.0
July 12, 2005
EL7520, EL7520A
VREF
VIN
REFERENCE
GENERATOR
OSCILLATOR
SLOPE
COMPENSATION
OSC
VBOOST
PWM
LOGIC
CONTROLLER

DRVB
BUFFER
VOLTAGE
AMPLIFIER
GM
AMPLIFIER
ISIN
CURRENT
AMPLIFIER
SHUTDOWN
& STARTUP
CONTROL
UVLO
COMPARATOR
CURRENT
LIMIT REF
GENERATOR
ISAD
CURRENT LIMIT
COMPARATOR
FIGURE 25. FUNCTION DIAGRAM OF THE BOOST CONTROLLER
The internal current limit circuitry is shown in Figure 26. The
circuit senses the voltage across the RDS(ON) when the
MOSFET is on; then compare it to the internal voltage
reference to realize the current limit. The internal voltage
reference is generated by a 10µA current and any additional
current set at ISAD pin flowing through an 8k resistor. The
voltage reference is based on the following equation:
VDD
10µA
+
VREF
 V ISAD

V THRESHOLD =  ----------------- + 10A  8K
 R1

Where VISAD is the voltage at pin ISAD.
LX
ISIN
1K
8K
LOGIC
CONTROLLER
DRVB
ISAD
R1
V ISAD = V REF – V BE – 1K  I SAD
FIGURE 26. CURRENT LIMIT BLOCK DIAGRAM
V ISAD
I SAD = ----------------R1
Hence the maximum output current is determined by the
following equation:
Where VBE  0.7V
The external resistor R1 should be chosen in the order of
100K to generate µA of current.
V IN
 V THRESHOLD I L
I OMAX =  --------------------------------------- – --------   --------R DSON
2  VO

Where IL is the peak to peak inductor ripple current, and is
set by:
V IN D
I L = ---------  ----L
fS
fS is the switching frequency; D is the duty cycle.
V O – V IN
D = -----------------------VO
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EL7520, EL7520A
Input Capacitor
The input capacitor is used to supply the current to the
converter. It is recommended that CIN be larger than 10µF.
The reflected ripple voltage will be smaller with larger CIN.
The voltage rating of input capacitor should be larger than
maximum input voltage.
Boost Inductor
A 3.3µH inductor is recommended due to the fixed internal
slope compensation. The inductor must be able to handle
the following average and peak current:
Compensation
The EL7520 and EL7520A can operate in either P mode or
PI mode. Connecting CINT pin directly to VIN will enable
P mode. For better load regulation, use PI mode with a
2.2nF capacitor between CINT and ground.
Linear-Regulator Controllers (VON, VLOGIC, and
VOFF)
IO
I LAVG = ------------1–D
I L
I LPK = I LAVG + -------2
Switching MOSFET
Due to the parasitic inductance of the trace, the MOSFET
will experience spikes higher that the output voltage when
the MOSFET turns off. Thus, a MOSFET with enough
voltage margin is needed.
The RDS(ON) of the MOSFET is critical for power dissipation
and current limit. A MOSFET with low RDS(ON) is desired to
get high efficiency and output current, but very low RDS(ON)
will reduce the loop stability. A MOSFET with 20m to 50m
RDS(ON) is recommended. Some recommended MOSFETs
are shown in following table.
TABLE 2. RECOMMENDED MOSFETs
PART
NUMBER
For low ESR ceramic capacitors, the output ripple is
dominated by the charging and discharging of the output
capacitor. The voltage rating of the output capacitor should
be greater than the maximum output voltage.
MANUFACTURER
FEATURE
FDC655AN
Fairchild
Semiconductor
6.3A, 30V, RDS(ON) = 23m
FDS4488
Fairchild
Semiconductor
7.9A, 30V, RDS(ON) = 22m
Si7844DP
Vishay
10A, 30V, RDS(ON) = 22m
SI6928DQ
Vishay
20A, 30V, RDS(ON) = 30m
Rectifier Diode
A high-speed diode is desired due to the high switching
frequency. Schottky diodes are recommended because of
their fast recovery time and low forward voltage. The rectifier
diode must meet the output current and peak inductor
current requirements.
Output Capacitor
The output capacitor supplies the load directly and reduces the
ripple voltage at the output. Output ripple voltage consists of
two components: the voltage drop due to the inductor ripple
current flowing through the ESR of output capacitor, and the
charging and discharging of the output capacitor.
The EL7520, EL7520A include three independent linearregulator controllers, in which two are positive output voltage
(VON and VLOGIC), and one is negative. The VON, VOFF,
and VLOGIC linear-regulator controller functional diagrams,
applications circuits are shown in Figures 27, 28, and 29
respectively.
Calculation of the Linear Regulator Base-Emitter
Resistors (RBL, RBP and RBN)
For the pass transistor of the linear regulator, low frequency
gain (Hfe) and unity gain freq. (fT) are usually specified in the
datasheet. The pass transistor adds a pole to the loop transfer
function at fp = fT/Hfe. Therefore, in order to maintain phase
margin at low frequency, the best choice for a pass device is
often a high frequency low gain switching transistor. Further
improvement can be obtained by adding a base-emitter resistor
RBE (RBP, RBL, RBN in the Functional Block Diagram), which
increase the pole frequency to: fp = fT*(1+ Hfe *re/RBE)/Hfe,
where re = KT/qIc. So choose the lowest value RBE in the
design as long as there is still enough base current (IB) to
support the maximum output current (IC).
We will take as an example the VLOGIC linear regulator. If a
Fairchild FMMT549 PNP transistor is used as the external
pass transistor, Q31 in the application diagram, then for a
maximum VLOGIC operating requirement of 500mA the data
sheet indicates Hfe_min = 100.
The base-emitter saturation voltage is: Vbe_max = 1.25V (note
this is normally a Vbe ~ 0.7V, however, for the Q5 transistor an
internal Darlington arrangement is used to increase it's current
gain, giving a 'base-emitter' voltage of 2 x VBE).
(Note that using a high current Darlington PNP transistor for
Q5 requires that VIN > VLOGIC + 2V. Should a lower input
voltage be required, then an ordinary high gain PNP
transistor should be selected for Q5 so as to allow a lower
collector-emitter saturation voltage).
For the EL7520, EL7520A, the minimum drive current is:
I_DRVL_min = 8mA
IO
V O – V IN
1
V RIPPLE = I LPK  ESR + ------------------------  ----------------  ----f
V
C
O
12
OUT
S
FN7318.0
July 12, 2005
EL7520, EL7520A
The minimum base-emitter resistor, RBL, can now be
calculated as:
VIN OR VPROT
(3V TO 6V)
RBL_min = VBE_max/(I_DRVL_min - Ic/Hfe_min) =
1.25V/(8mA - 500mA/100) = 417
LDO_LOG
0.9V
PG_LDOL
This is the minimum value that can be used - so, we now
choose a convenient value greater than this minimum value;
say 500. Larger values may be used to reduce quiescent
current, however, regulation may be adversely affected, by
supply noise if RBL is made too high in value.
VBOOST
LX
0.1µF
RBL
500
+
-
Q5
VLOGIC
(1.3V TO 3.6V)
DRVL
RL1
CLOG
10µF
FBL
+
GML
RL2
20k
LDO_ON
0.9V
1: N1
PG_LDOP
CP (TO 36V)
36V
ESD
CLAMP
+
-
RBP
7k
0.1µF
Q3
VON (TO 35V)
DRVP
RP1
FBP
CON
RP2
20k
+
GMP
1: Np
FIGURE 27. VON FUNCTIONAL BLOCK DIAGRAM
LX
0.1µF
CP (TO -26V)
LDO_OFF
PG_LDON
VREF
+
0.1µF
RN2
20k
0.4V
FBN
1: Nn
RN1
VOFF (TO -20V)
+
GMN
DRVN
36V
ESD
CLAMP
RBN
3k
Q2
COFF
FIGURE 28. VOFF FUNCTIONAL BLOCK DIAGRAM
13
FIGURE 29. VLOGIC FUNCTIONAL BLOCK DIAGRAM
The VON power supply is used to power the positive supply
of the row driver in the LCD panel. The DC/DC consists of an
external diode-capacitor charge pump powered from the
inductor (LX) of the boost converter, followed by a low
dropout linear regulator (LDO_ON). The LDO_ON regulator
uses an external PNP transistor as the pass element. The
onboard LDO controller is a wide band (>10MHz)
transconductance amplifier capable of 4mA drive current,
which is sufficient for up to 40mA or more output current
under the low dropout condition (forced beta of 10). Typical
VON voltage supported by EL7520, EL7520A range from
+15V to +36V. A fault comparator is also included for
monitoring the output voltage. The under-voltage threshold
is set at 25% below the 1.2V reference.
The VOFF power supply is used to power the negative
supply of the row driver in the LCD panel. The DC/DC
consists of an external diode-capacitor charge pump
powered from the inductor (LX) of the boost converter,
followed by a low dropout linear regulator (LDO_OFF). The
LDO_OFF regulator uses an external NPN transistor as the
pass element. The onboard LDO controller is a wide band
(>10MHz) transconductance amplifier capable of 4mA drive
current, which is sufficient for up to 40mA or more output
current under the low dropout condition (forced beta of 10).
Typical VOFF voltage supported by EL7520, EL7520A range
from -5V to -20V. A fault comparator is also included for
monitoring the output voltage. The undervoltage threshold is
set at 200mV above the 0.2V reference level.
The VLOGIC power supply is used to power the logic circuitry
within the LCD panel. The DC/DC may be powered directly
from the low voltage input, 3.3V or 5.0V, or it may be powered
through the fault protection switch. The LDO_LOGIC regulator
uses an external PNP transistor as the pass element. The
onboard LDO controller is a wide band (>10MHz)
transconductance amplifier capable of 16mA drive current,
which is sufficient for up to 160mA or more output current
FN7318.0
July 12, 2005
EL7520, EL7520A
under the low dropout condition (forced beta of 10). Typical
VLOGIC voltage supported by EL7520, EL7520A range from
+1.3V to VDD-0.2V. A fault comparator is also included for
monitoring the output voltage. The undervoltage threshold is
set at 25% below the 1.2V reference.
Set-Up LDOs Output Voltage
Refer to Typical Application Diagram, the output voltages of
VON, VOFF, and VLOGIC are determined by the following
equations:
R 12

V ON = V REF   1 + ----------
R 11

R 22
V OFF = V REFN + ----------   V REFN – V REF 
R 21
R 42

V LOGIC = V REF   1 + ----------
R 41

Where VREF = 1.2V, VREFN = 0.2V.
Charge Pump
To generate an output voltage higher than VBOOST, single or
multi stages of charge pumps are needed. The number of
stage is determined by the input and output voltage. For
positive charge pump stages:
V OUT + V CE – V INPUT
N POSITIVE  -------------------------------------------------------------V INPUT – 2  V F
where VCE is the dropout voltage of the pass component of
the linear regulator. It ranges from 0.3V to 1V depending on
the transistor. VF is the forward-voltage of the charge pump
rectifier diode.
The number of negative charge pump stages is given by:
V OUTPUT + V CE
N NEGATIVE  ------------------------------------------------V INPUT – 2  V F
To achieve high efficiency and low material cost, the lowest
number of charge pump stages, which can meet the above
requirements, is always preferred.
Charge Pump Output Capacitors
A ceramic capacitor with low ESR is recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be
chosen by the following equation:
Start-Up Sequence
Figures 30 and 31 show detailed start-up sequence
waveforms, EL7520 and EL7520A, respectively. For a
successful power-up, there should be six peaks at VCDLY.
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
If EN is L, the device is powered down. If EN is H, and the
input voltage (VDD) exceeds 2.5V, an internal current source
starts to charge CDLY to an upper threshold using a fast
ramp followed by a slow ramp. If EN is low at this point, the
CDLY ramp will be delayed until EN goes high.
The first four ramps on CDLY (two up, two down) are used to
initialize the fault protection switch and to check whether
there is a fault condition on CDLY or VREF. If a fault is
detected, the outputs and the input protection will turn off and
the chip will power down. For EL7520A, VREF will stay on.
If no fault is found, CCDLY continues ramping up and down
until the sequence is completed.
During the second ramp, the device checks the status of
VREF and over temperature. At the peak of the second ramp,
PG output goes low and enables the input protection PMOS
Q1. Q1 is a controlled FET used to prevent in-rush current into
VBOOST before VBOOST is enabled internally. Its rate of turn
on is controlled by Co. When a fault is detected, Q1 will turn
off and disconnect the inductor from VIN.
With the input protection FET on, NODE1 (See Typical
Application Diagram) will rise to ~VIN. Initially the boost is not
enabled so VBOOST rises to VIN-VDIODE through the output
diode. Hence, there is a step at VBOOST during this part of the
start-up sequence. If this step is not desirable, an external
PMOS FET can be used to delay the output until the boost is
enabled internally. The delayed output appears at AVDD.
For EL7520, VBOOST and VLOGIC soft-start at the beginning
of the third ramp. The soft-start ramp depends on the value
of the CDLY capacitor. For CDLY of 220nF, the soft-start time
is ~2ms. EL7520A is the same as EL7520 except that VREF
and VLOGIC turn on once input voltage exceeds 2.5V.
VOFF turns on at the start of the fourth peak. At the fifth
peak, DELB gate goes low to turn on the external PMOS Q4
to generate a delayed VBOOST output.
VON is enabled at the beginning of the sixth ramp. AVDD,
PG, VOFF, DELB and VON are checked at end of this ramp.
I OUT
C OUT  -----------------------------------------------------2  V RIPPLE  f OSC
Where fSOC is the switching frequency.
14
FN7318.0
July 12, 2005
CHIP DISABLED
FAULT DETECTED
VON SOFT-START
DELB ON
VOFF ON
AVDD, VLOGIC
SOFT-START
PG ON
VREF ON
EL7520, EL7520A
VCDLY
EN
VREF
VBOOST
tON
tOS
VLOGIC
VOFF
tDEL1
DELAYED
VBOOST
tDEL2
FAULT
PRESENT
START-UP SEQUENCE
TIMED BY CDLY
NORMAL
OPERATION
VON
FIGURE 30. EL7520 START-UP SEQUENCE
15
FN7318.0
July 12, 2005
CHIP DISABLED
FAULT DETECTED
VON SOFT-START
DELB ON
VOFF ON
AVDD SOFT-START
PG ON
VREF, VLOGIC ON
EL7520, EL7520A
VCDLY
VIN
EN
VREF
VBOOST
tON
tOS
VLOGIC
VOFF
tDEL1
DELAYED
VBOOST
tDEL2
START-UP SEQUENCE
TIMED BY CDLY
FAULT
PRESENT
tDEL3
NORMAL
OPERATION
VON
FIGURE 31. EL7520A START-UP SEQUENCE
16
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July 12, 2005
EL7520, EL7520A
Over-Temperature Protection
An internal temperature sensor continuously monitor the die
temperature. In the event that the die temperature exceeds
the thermal trip point, the device will shut down. The upper
and lower trigger points are typically set to 130°C and -90°C
respectively.
Layout Recommendation
The device's performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
There are some general guidelines for layout:
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
2. Place VREF and VDD bypass capacitors close to the pins.
3. Reduce the loop with large AC amplitudes and fast slew
rate.
4. The feedback network should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point.
A demo board is available to illustrate the proper layout
implementation.
17
FN7318.0
July 12, 2005
EL7520, EL7520A
QFN Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil
website at <http://www.intersil.com/design/packages/index.asp>
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
18
FN7318.0
July 12, 2005
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