DATASHEET

EL7581
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T
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8
1-88
March 9, 2006
3-Channel DC/DC Converter
Features
The EL7581 is a 3-channel DC/DC converter IC which is
designed primarily for use in TFT/LCD applications. It
features a PWM boost converter with 2.7V to 14V input
capability and 5V to 17V output, which powers the column
drivers and provides up to 720mA @12V, 570mA @ 15V
from 5V input. A pair of charge pump control circuits provide
regulated outputs of VON and VOFF supplies at 8V to 40V
and -5V to -40V, respectively, each at up to 60mA.
• TFT/LCD display supply
- Boost regulator
- VON charge pump
- VOFF charge pump
FN7100.5
• 2.7V to 14V VIN supply
• 5V < VBOOST < 17V
• 5V < VON < 40V
The EL7581 features adjustable switching frequency,
adjustable soft start, and a separate output VON enable
control to allow selection of supply start-up sequence. An
over-temperature feature is provided to allow the IC to be
automatically protected from excessive power dissipation.
• VBOOST = 12V @ 720mA
The EL7581 is available in a 20 Ld HTSSOP package and is
specified for operation over the full -40°C to +85°C
temperature range.
• Over 90% efficient DC/DC boost converter capability
• VBOOST = 15V @ 570mA
• High frequency, small inductor DC/DC boost circuit
• Adjustable frequency
• Adjustable soft-start
Ordering Information
PART
NUMBER
• -40V < VOFF < 0V
PART
TAPE &
MARKING REEL
PACKAGE
PKG.
DWG. #
EL7581IRE
7581IRE
-
20 Ld HTSSOP MDP0048
EL7581IRE-T7
7581IRE
7”
20 Ld HTSSOP MDP0048
EL7581IRE-T13
7581IRE
13”
20 Ld HTSSOP MDP0048
EL7581IREZ
(Note)
7581IREZ
-
20 Ld HTSSOP MDP0048
(Pb-Free)
EL7581IREZ-T7
(Note)
7581IREZ
7”
20 Ld HTSSOP MDP0048
(Pb-Free)
EL7581IREZ-T13 7581IREZ
(Note)
13”
20 Ld HTSSOP MDP0048
(Pb-Free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
• Adjustable outputs
• Small parts count
• Pb-free plus anneal available (RoHS compliant)
Applications
• TFT-LCD panels
• PDAs
Pinout
EL7581
(20 LD HTSSOP)
TOP VIEW
VSSB 1
20 ROSC
SS 2
19 ENP
FBB 3
18 ENBN
VDDB 4
17 VREF
LX 5
LX 6
THERMAL
PAD*
16 PGND
15 PGND
LX 7
14 DRVP
DRVN 8
13 VDDP
VDDN 9
12 FBP
FBN 10
11 VSSP
*Refer to PCB layout guideline.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL7581
Absolute Maximum Ratings (TA = 25°C)
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Die Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
VIN Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14V
VDDB, VDDP, VDDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18V
LX Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . . . .1A
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VIN = 3.3V, VBOOST = 12V, ROSC = 100k, TA = 25°C Unless Otherwise Specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
DC/DC BOOST CONVERTER
IQ1_B
Quiescent Current - Shut-down
ENBN = ENP = 0V
0.8
10
µA
IQ2_B
Quiescent Current - Switching
ENBN = VDDB
4.8
8
mA
V(FBB)
Feedback Voltage
1.275
1.300
1.325
V
VREF
Reference Voltage
1.260
1.310
1.360
V
VROSC
Oscillator Set Voltage
1.260
1.325
1.390
V
I(FBB)
Feedback Input Bias Current
VDDB
Boost Converter Supply Range
2.7
DMAX
Maximum Duty Cycle
85
I(LX)MAX
Peak Internal FET Current
RDS-ON
Switch On Resistance
at VBOOST = 10V, I(LX) total = 500mA
ILEAK-SWITCH
Switch Leakage Current
I(LX) total
VBOOST
Output Range
VBOOST > VIN + VDIODE
VBOOST/VIN
Line Regulation
2.7V < VIN < 13.2V, VBOOST = 15V
0.1
%
VBOOST/IO1
Load Regulation
50mA < IO1 < 300mA
0.5
%
FOSC-RANGE
Frequency Range
ROSC range = 240k to 60k
200
FOSC1
Switching Frequency
ROSC = 100k
620
0.1
µA
17
V
92
%
2.75
A
0.15

5
680
2
µA
17
V
1000
kHz
750
kHz
POSITIVE REGULATED CHARGE PUMP (VON)
Most positive VON output depends on the magnitude of the VDDP input voltage (normally connected to VBOOST) and the external component
configuration (doubler or tripler)
VDDP
Supply Input for Positive Charge Pump
Usually connected to VBOOST output
IQ1(VDDP)
Quiescent Current - Shut-down
ENP = 0V
IQ2(VDDP)
Quiescent Current - Switching
ENBN = ENP = VDDB
V(FBP)
Feedback Reference Voltage
I(FBP)
Feedback Input Bias Current
I(DRVP)
RMS DRVP Output Current
1.245
VDDP = 12V
VDDP = 6V
ILR_VON
Load Regulation
5mA < IL < 15mA
FPUMP
Charge Pump Frequency
Frequency set by ROSC - see boost section
2
5
17
V
11.5
20
µA
2.3
5
mA
1.310
1.375
V
0.1
µA
60
mA
15
-0.5
mA
0.03
0.5*FOSC
0.5
%/mA
EL7581
Electrical Specifications
PARAMETER
VIN = 3.3V, VBOOST = 12V, ROSC = 100k, TA = 25°C Unless Otherwise Specified. (Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
NEGATIVE REGULATED CHARGE PUMP (VOFF)
Most negative VOFF output depends on the magnitude of the VDDN input voltage (normally connected to VBOOST) and the external component
configuration (doubler or tripler)
VDDN
Supply Input for Negative Charge Pump
Usually connected to VBOOST output
IQ1(VDDN)
Quiescent Current - Shut-down
ENBN = 0V
IQ2(VDDN)
Quiescent Current - Switching
ENBN = VDDB
V(FBN)
Feedback Reference Voltage
I(FBN)
Feedback Input Bias Current
Magnitude of input bias
0.1
µA
I(DRVN)
RMS DRVN Output Current
VDDN = 12V
60
mA
5
-80
VDDN = 6V
ILR_VOFF
Load Regulation
-15mA < IL < -5mA
FPUMP
Charge Pump Frequency
Frequency set by ROSC - see boost section
17
V
1.2
10
µA
2.3
5
mA
0
+80
mV
15
-0.5
mA
0.03
0.5
%/mA
0.5*FOSC
ENABLE CONTROL LOGIC
VHI-ENX
Enable Input High Threshold
X = “BN”, “P”
VLO-ENX
Enable Input Low Threshold
X = “BN”, “P”
IL(EN”X”)
Logic Low Bias Current
X = “BN”, “P” = 0V
0.1
IL(ENBN)
Logic High Bias Current
ENBN = 5V
7.5
15
µA
IL(ENP)
Logic High Bias Current
ENP = 5V
3.3
7.5
µA
1.4
V
0.6
V
µA
OVER-TEMPERATURE PROTECTION
TOT
Over-temperature Threshold
130
°C
THYS
Over-temperature Hysteresis
40
°C
3
EL7581
Pin Descriptions I = Input, O = Output, S = Supply
PIN NUMBER
PIN NAME
PIN TYPE
1
VSSB
S
Ground for DC/DC boost and reference circuits; chip substrate
2
SS
I
Soft-start input; the capacitor connected to this pin sets the current limited start time
3
FBB
I
Voltage feedback input for boost circuit; determines boost output voltage, VBOOST
4
VDDB
S
Positive supply input for DC/DC boost circuits
5
LX
O
Boost regulator inductor drive connected to drain of internal NFET
6
LX
O
Boost regulator inductor drive connected to drain of internal NFET
7
LX
O
Boost regulator inductor drive connected to drain of internal NFET
8
DRVN
O
Driver output for the external generation of negative charge pump voltage, VOFF
9
VDDN
S
Positive supply for input for VOFF generator
10
FBN
I
Voltage feedback input to determine negative charge pump output, VOFF
11
VSSP
S
Negative supply pin for both the positive and negative charge pumps
12
FBP
I
Voltage feedback to determine positive charge pump output, VON
13
VDDP
S
Positive supply input for VON generator
14
DRVP
O
Voltage driver output for the external generation of positive charge pump, VON
15
PGND
O
Power ground, connected to source of internal NFET
16
PGND
O
Power ground, connected to source of internal NFET
17
VREF
I
Voltage reference for charge pump circuits; decouple to ground
18
ENBN
I
Enable pin for boost (VBOOST generation) and negative charge pump (VOFF generation);
active high
19
ENP
I
Enable for DRVP (VON generation); active high
20
ROSC
I
Connected to an external resistor to ground; sets the switching frequency of the DC/DC boost
4
PIN FUNCTION
EL7581
Typical Performance Curves
95
95
9V
85
15V
90
12V
EFFICIENCY (%)
EFFICIENCY (%)
90
80
75
70
65
0
200
400
600
800
85
9V
15V
80
1K
70
IOUT (mA)
1K
15V
85
90
5V
12V
EFFICIENCY (%)
EFFICIENCY (%)
800
95
9V
90
80
75
70
65 V = 5V
IN
FS = 700kHz
60
0
200
85
9V
80
15V
70
65
VIN = 3.3V
FS = 1MHz
60
400
600
800
12V
75
0
1K
200
400
600
800
1K
IOUT (mA)
IOUT (mA)
FIGURE 4. EFFICIENCY vs IOUT
FIGURE 3. EFFICIENCY vs IOUT
3
2
VIN = 3.3V
FS = 1MHz
1
0.5
0
15V
5V
9V
-1
12V
-1.5
250
VIN = 5V
FS = 1MHz
2.5
LOAD REGULATION (%)
1.5
LOAD REGULATION (%)
600
FIGURE 2. EFFICIENCY vs IOUT
95
-2
50
400
IOUT (mA)
FIGURE 1. EFFICIENCY vs IOUT
-0.5
12V
75
65 VIN = 3.3V
FS = 700kHz
60
0
200
VIN = 5V
FS = 1MHz
60
5V
2
1.5
1
0.5
0
-0.5
9V
-1
450
650
850
IOUT (mA)
FIGURE 5. LOAD REGULATION
5
1050
-1.5
50
15V
250
450
12V
650
850
IOUT (mA)
FIGURE 6. LOAD REGULATION
1050
EL7581
Typical Performance Curves (Continued)
3
VIN = 3.3V
FS = 700kHz
3
2
1
0
5V
-1
9V
15V
-2
50
250
VIN=5V
FS = 700kHz
2.5
LOAD REGULATION (%)
LOAD REGULATION (%)
4
12V
2
1.5
1
0.5
0
-0.5
-1
450
650
850
-2
50
1050
250
450
IOUT (mA)
1050
6.5
19
VDDN = 15V
6
VDDP = 15V
VDDN = 12V
5.5
18
VDDP = 12V
VOFF (-V)
VON (V)
850
FIGURE 8. LOAD REGULATION
20
17
16
5
4.5
4
15
3.5
14
0
10
20
30
40
50
60
70
0
80
10
20
30
40
50
60
70
80
ILOAD (mA)
ILOAD (mA)
FIGURE 10. VOFF vs IOFF
FIGURE 9. VON vs ION
f(MHz) = 1/(0.0118 ROSC + 0.378)
6
SWITCHING PERIOD (µs)
1200
FREQUENCY (kHz)
650
9V
IOUT (mA)
FIGURE 7. LOAD REGULATION
1400
12V
15V
-1.5
1000
800
600
400
200
SWITCHING PERIOD (µs) = 0.0118 ROSC + 0.378
5
4
3
2
1
0
0
0
50
100
150
200
250
300
ROSC (k)
FIGURE 11. FS vs ROSC
6
350
400 450
0
50
100
150
200
250
300
350
400
ROSC (k)
FIGURE 12. SWITCHING PERIOD vs ROSC
450
EL7581
Typical Performance Curves (Continued)
ROSC = 61.9k
970
1.27
1.265
968
VOLTAGE (V)
FREQUENCY (kHz)
969
967
966
965
1.26
1.255
964
963
962
3
3.5
4
4.5
5
5.5
6
1.25
-50
0
50
100
TEMPERATURE (°C)
VDDB (V)
FIGURE 14. VREF vs TEMPERATURE
FIGURE 13. FS vs VDDB
IO = 5mA, VON = 18V, CON = 2.2µF
VIN = 5V, VBOOST = 13V, IO = 100mA, CBOOST = 22µF
VLX
(10V/DIV)
50mV/DIV
VBOOST
(20mV/DIV)
0.5µs/DIV
2µs/DIV
FIGURE 15. BOOST STAGE
FIGURE 16. VON RIPPLE
IO = 5mA, VOFF = -6V, COFF = 3.3µF
IO = 18mA, VON = 18V, CON = 2.2µF
20mV/DIV
50mV/DIV
2µs/DIV
FIGURE 17. VON RIPPLE
7
10µs/DIV
FIGURE 18. VOFF RIPPLE
150
EL7581
Typical Performance Curves (Continued)
IO = 15mA, VOFF = -6V, COFF = 3.3µF
VBOOST = 13V, IO = 100mA to 420mA, CBOOST = 22µF
IO
20mV/DIV
VO
(100mV/DIV)
2µs/DIV
20µs/DIV
FIGURE 19. VOFF RIPPLE
FIGURE 20. BOOST CONVERTER TRANSIENT RESPONSE
CSS = 0.1µF
CSS = 0.033µF
VIN
2V/DIV
VIN
2V/DIV
IIN
0.5A/DIV
IIN
0.5A/DIV
1mA/DIV
1ms/DIV
FIGURE 21. START-UP VOLTAGE AND CURRENT
FIGURE 22. START-UP VOLTAGE AND CURRENT
CSS = 0.1µF
CSS = 0.1µF
VBOOST
VBOOST
100mA
5V/DIV
5V/DIV
10V/DIV
2V/DIV
VON
10V/DIV
VOFF
2V/DIV
1ms/DIV
FIGURE 23. POWER-UP, NO DELAY RC NETWORK ON
ENABLE PINS
8
VON
VOFF
200ms/DIV
FIGURE 24. POWER-DOWN, NO DELAY RC NETWORK ON
ENABLE PINS
EL7581
Typical Performance Curves (Continued)
CSS = 0.1µF
CSS = 0.1µF
VBOOST
VBOOST
5V/div
5V/DIV
10V/DIV
VON
VON
10V/DIV
VOFF
2V/DIV
1ms/DIV
200ms/DIV
FIGURE 26. POWER-UP, 100K AND 0.1µF DELAY NETWORK
ON ENP
FIGURE 25. POWER-DOWN, 100K AND 0.1µF DELAY
NETWORK ON ENP
VIN = 3.3V
VOUT = 11.3V
IOUT = 50mA
VIN = 3.3V
VOUT = 11.3V
IOUT = 250mA
FIGURE 28. LX WAVEFORM - CONTINUOUS MODE
FIGURE 27. LX WAVEFORM - DISCONTINUOUS MODE
3.5
50
20-PIN HTSSOP THERMAL PAD
SOLDERED TO 2-LAYER PCB WITH
0.039" THICKNESS AND 1-oz COPPER
ON BOTH SIDES
40
POWER DISSIPATION (W)
JA (°C/W)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
HTSSOP EXPOSED DIEPAD SOLDERED TO PCB
PER JESD51-5
CONDITION:
45
VOFF
2V/DIV
35
30
2.857W
3
2.5

JA
2
1.5
HT
=3
SS
O
P2
5°
0
C/
W
1
0.5
0
25
1
2
3
4
5
6
7
8
9
PCB AREA (in2)
FIGURE 29. 20-PIN HTSSOP THERMAL RESISTANCE vs PCB
AREA, NO AIR FLOW
9
0
25
50
75 85
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 30. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
EL7581
Typical Performance Curves (Continued)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
POWER DISSIPATION (W)
0.9
800mW
0.8
0.7

JA
=
0.6
0.5
HT
S
12
0.4
SO
5°
C/
P2
0
W
0.3
0.2
0.1
0
0
25
50
75 85
125
100
150
AMBIENT TEMPERATURE (°C)
FIGURE 31. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Block Diagram
VOUT
10µH
R2
R1
13k
VIN
110k
49
10µF
10µF
0.1µF
FBB
LX
VDDB
MAX_DUTY
ROSC
REFERENCE
GENERATOR
R3
62k
VREF
VRAMP
PWM
COMPARATOR
PWM
LOGIC
0.15
ENBN
12µA
START-UP
OSCILLATOR
+
ILOUT
VSSB
7.2K
80m
SS
0.1µF
10
PGND
EL7581
Applications Information
Steady-State Operation
The EL7581 is high efficiency multiple output power solution
designed specifically for thin-film transistor (TFT) liquid
crystal display (LCD) applications. The device contains one
high current boost converter and two low power charge
pumps (VON and VOFF).
When the output reaches the preset voltage, the regulator
operates at steady state. Depending on the input/output
condition and component, the inductor operates at either
continuous-conduction mode or discontinuous-conduction
mode.
The boost converter contains an integrated N-channel
MOSFET to minimize the number of external components.
The converter output voltage can be set from 5V to 18V with
external resistors. The VON and VOFF charge pumps are
independently regulated to positive and negative voltages
using external resistors. Output voltages as high as 40V can
be achieved with additional capacitors and diodes.
In the continuous-conduction mode, the inductor current is a
triangular waveform and LX voltage a pulse waveform. In the
discontinuous-conduction mode, the inductor current is
completely ‘dried-out’ before the MOSFET is turned on
again. The input voltage source, the inductor, and the
MOSFET and output diode parasitic capacitors forms a
resonant circuit. Oscillation will occur in this period. This
oscillation is normal and will not affect the regulation.
Boost Converter
The boost converter operates in constant frequency pulsewidth-modulation (PWM) mode. Quiescent current for the
EL7581 is only 5mA when enabled, and since only the low
side MOSFET is used, switch drive current is minimized.
90% efficiency is achieved in most common application
operating conditions.
A functional block diagram with typical circuit configuration is
shown on the previous page. Regulation is performed by the
PWM comparator which regulates the output voltage by
comparing a divided output voltage with an internal
reference voltage. The PWM comparator outputs its result to
the PWM logic. The PWM logic switches the MOSFET on
and off through the gate drive circuit. Its switching frequency
is external adjustable with a resistor from timing control pin
(ROSC) to ground. The boost converter has 200kHz to
1.2MHz operating frequency range.
Start-Up
After VDDB reaches a threshold of about 2V, the power
MOSFET is controlled by the start-up oscillator, which
generates fixed duty-ratio of 0.5 - 0.7 at a frequency of
several hundred kilohertz. This will boost the output voltage,
providing the initial output current load is not too great
(<250mA).
When VDDB reaches about 3.7V, the PWM comparator
takes over the control. The duty ratio will be decided by the
multiple-input direct summing comparator, Max_Duty signal
(about 90% duty-ratio), and the Current Limit Comparator,
whichever is the smallest.
The soft-start is provided by the current limit comparator. As
the internal 12µA current source charges the external softstart capacitor, the peak MOSFET current is limited by the
voltage on the capacitor. This in turn controls the rising rate
of output voltage.
The regulator goes through the start-up sequence as well
after the ENBN signal is pulled to HI.
11
At very low load, the MOSFET will skip pulse sometimes.
This is normal.
Current Limit
The MOSFET current limit is nominal ILMT = 2.75A. This
restricts the maximum output current IOMAX based on the
following formula:
V IN
L
I OMAX =  I LMT – -------  --------
2  VO
where:
• IL is the inductor peak-to-peak current ripple and is
decided by:
V IN D
I L = ---------  ------L
FS
• D is the MOSFET turn-on radio and is decided by:
V O - V IN
D = -----------------------VO
• FS is the switching frequency.
The following table gives typical values:
(Margins are considered in deriving IOMAX. They are 10%,
3%, 20%, 10%, and 20% on VIN, VO, L, FS, and ILMT,
respectively.)
TABLE 1. MAXIMUM CONTINUOUS OUTPUT CURRENT
VIN (V)
VO (V)
L (µH)
FS (kHz)
IOMAX (mA)
3.3
5
10
1000
1200
3.3
9
10
1000
660
3.3
12
10
1000
490
3.3
15
10
1000
390
5
9
10
1000
980
5
12
10
1000
720
5
15
10
1000
570
12
15
10
1000
1300
12
18
10
1000
1100
EL7581
Component Considerations
Input Capacitor
It is recommended that CIN is larger than 10µF.
Theoretically, the input capacitor has ripple current of IL.
Due to high-frequency noise in the circuit, the input current
ripple may exceed the theoretical value. Larger capacitor will
reduce the ripple further.
Boost Inductor
The inductor has peak and average current decided by:
I L
I LPK = I LAVG + -------2
Elantec demo board, MBRM120 is selected. Its forward
voltage drop is 450mV at 1A forward current.
Output Capacitor
The EL7581 is specially compensated to be stable with
capacitors which have a worst-case minimum value of 10µF
at the particular VOUT being set. Output ripple voltage
requirements also determine the minimum value and the
type of capacitors. Output ripple voltage consists of two
components - the voltage drop caused by the switching
current though the ESR of the output capacitor and the
charging and discharging of the output capacitor:
V OUT - V IN
I OUT
V RIPPLE = I LPK  ESR + --------------------------------  -----------------------------V
C
 FS
OUT
IO
I LAVG = ------------1-D
The inductor should be chosen to be able to handle this
current. Furthermore, due to the fixed internal
compensation, it is recommended that maximum inductance
of 10µH and 15µH to be used in the 5V and 12V or higher
output voltage, respectively.
The output diode has average current of IO, and peak
current the same as the inductor's peak current. Schottky
diode is recommended and it should be able to handle those
currents.
Feedback Resistor Network
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 200k is
recommended. The boost converter output voltage is
determined by the following relationship:
R1 + R2
V BOOST = ---------------------  V FBB
R1
Where VFBB is 1.300V as specified.
A 3.9nF compensation capacitor across the feedback
resistor to ground is recommended to keep the converter in
stable operation at low output current and high frequency
conditions.
Schottky Diode
Speed, forward voltage drop, and reverse current are the
three most critical specifications for selecting the Schottky
diode. The entire output current flows through the diode, so
the diode average current is the same as the average load
current and the peak current is the same as the inductor
peak current. When selecting the diode, one must consider
the forward voltage drop at the peak diode current. On the
12
OUT
For low ESR ceramic capacitors, the output ripple is
dominated by the charging/discharging of the output
capacitor.
In addition to the voltage rating, the output capacitor should
also be able to handle the RMS current is given by:
I CORMS =
2


I L
1
 1 - D    D + --------------------  ------   I LAVG

2 12 
I LAVG


Positive and Negative Charge Pump (VON and
VOFF)
The EL7581 contains two independent charge pumps (see
charge pump block and connection diagram.) The negative
charge pump inverts the VDDN supply voltage and provides
a regulated negative output voltage. The positive charge
pump doubles the VDDP supply voltage and provides a
regulated positive output voltage. The regulation of both the
negative and positive charge pumps is generated by the
internal comparator that senses the output voltage and
compares it with and internal reference. The switching
frequency of the charge pump is set to ½ the boost converter
switching frequency.
The pumps use pulse width modulation to adjust the pump
period, depending on the load present. The pumps are shortcircuit protected to 180mA at 12V supply and can provide
15mA to 60mA for 6V to 12V supply.
EL7581
VDDN
5V to
17V
VDDP
5V to
17V
0.1µF
RONP
0.1µF
CCPP
RONP
DRVN
OSC
DRVP
CCPN
VOFF
RONN
COUT2
RONN
3.3µF
R21
FBN
2.2µF
FBP
+
+
-
V
COUT1ON
R12
VSSP
VSSN
+
-
VFBP
R11
RON is 30 - 40 for VDD 6V to 17V
R22
VREF
(1.32V)
Positive Charge Pump Design Considerations
A single stage charge pump is shown above. The maximum VON output voltage is determined by the following equation:
1
1
V ON  max   2  V DDCPP - I OUT  2   R ONN + R ONP  - 2  V DIODE - I OUT  -------------------------------------------- - I OUT  -----------------------------------------------0.5  F  C
0.5  F  C
S
where:
• RONN and RONP resistance values depend on the VDDP
voltage levels. For 12V supply, RON is typically 33. For
6V supply, RON is typically 45.
If additional stage is required, the LX switching signal is
recommended to drive the additional charge pump diodes.
The drive impedance at the LX switching is typically 150m.
The figure on the next page illustrates an implementation for
two-stage positive charge pump circuit.
13
CPP
S
OUT1
EL7581
Two-Stage Positive Charge Pump Circuit
VDDP
VBOOST
(5V-17V)
RONP
VLX
CCPP
DRNP
VON
CCPP
RONN
COUT1
COUT1
VSSP
R12
+
FBP
1.265V
+
-
R11
The maximum VON output voltage for N+1 stage charge pump is:
1
V ON  max   2  V DDP - I OUT  2   R ONN + R ONP  - 2  V DIODE - I OUT  -------------------------------------------- - I OUT 
0.5  F S  C CPP
1
1
1
------------------------------------------------ + N  V LX  max  - N   2  V DIODE + I OUT  -------------------------------------------- + I OUT  ------------------------------------------------ 

0.5  F S  C OUT1
0.5  F S  C CPP
0.5  F S  C OUT1 
R11 and R12 set the VON output voltage:
R 11 + R 12
V ON = V FBP  --------------------------R
11
Where VFPB is nominal 1.310V.
Negative Charge Pump Design Considerations
The criteria for the negative charge pump is similar to the
positive charge pump. For a single stage charge pump, the
maximum VOFF output voltage is:
1
1
V OFF  max   I OUT  2   R ONN + R ONP  + 2  V DIODE - IOUT  -------------------------------------------- - I OUT  ------------------------------------------------ - V DDN
0.5  F S  C CPN
0.5  F S  C OUT2
Similar to positive charge pump, if additional stage is
required, the LX switching signal is recommended to drive
the additional charge pump diodes. The figure on the next
page shows a two stage negative charge pump circuit.
14
EL7581
Two-Stage Negative Charge Pump Circuit
VDDN
5V-17V
VLX
RONP
CCPN
DRVN
RONN
VOFF
CCPN
COUT2
COUT2
VSSN
+
-
R21
FBN
R22
VREF
The maximum VOFF output voltage for N+1 stage charge pump is:
1
1
V OFF  max   I OUT  2   R ONN + R ONP  + 2  V DIODE - I OUT  -------------------------------------------- - I OUT  ------------------------------------------------ 0.5  F  C
0.5  F  C
S
CPN
1
1
V DDN - N  V LX  max  + N   2  V DIODE + I OUT  -------------------------------------------- + I OUT  ------------------------------------------------ 


0.5  F  C
0.5  F  C
S
CPN
S
S
OUT2
OUT2
R21 and R22 determine VOFF output voltage:
R 21
V OFF = – V REF  ---------R 22
Where VREF is nominal 1.310V.
Over-Temperature Protection
An internal temperature sensor continuously monitors the
die temperature. In the event that die temperature exceeds
the thermal trip point, the device will shut down and disable
itself. The upper and lower trip points are typically set to
130°C and 90°C respectively.
PCB Layout Guidelines
Careful layout is critical in the successful operation of the
application. The following layout guidelines are
recommended to achieve optimum performance.
• VREF and VDDB bypass capacitors should be placed next
to the pins.
• Place the boost converter diode and inductor close to the
LX pins.
• Place the boost converter output capacitor close to the
PGND pins.
• Locate feedback dividers close to their respected
feedback pins to avoid switching noise coupling into the
high impedance node.
• Place the charge pump feedback resistor network after the
diode and output capacitor node to avoid switching noise.
15
• Thermal pad needs to be connected to PGND pins
electrically, and it should be soldered to PCB with thermal
vias connecting to ground plane for maximum heat
dissipation.
• All low-side feedback resistors should be connected
directly to VSSB. VSSB should be connected to the power
ground close at one point only.
A demo board is available to illustrate the proper layout
implementation.
EL7581
Typical Application Circuit
R2
R3
110K
C7
C10
1 VSSB
ROSC 20
61.9K
ENP 19
2 SS
0.1µF
OPEN
R1
13K
R4
49.9
VBOOST
(12V@
500mA)
C5
10µF
+
VOFF
(-6V@
15mA)
GND
L1
C1
10µF
+
C2
4.7µF
ENBN 18
4 VDDB
VREF 17
5 LX
PGND 16
6 LX
PGND 15
10µH
7 LX
DRVP 14
8 DRVN
VDDP 13
9 VDDN
C21
FBP 12
R21
154K
C27
0.1µF
C26
3.3µF
0.1µF
10 FBN
VSSP 11
R6
0
C8
C50
0.1µF
OPEN
1nF
C12
0.1µF
VON
([email protected])
D11**
C22
0.1µF
499K
C9
D1*
22µF
OPEN
VIN
0.1µF
C3
C4
C6
3 FBB
R5
C11
0.1µF
C16
C17
R12
0.1µF
2.2µF
51K
R11
3.9K
D21**
R22
33.2K
* MBRM120LT3
** BAT54S
16
EL7581
Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
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