DATASHEET

EL1881
®
Data Sheet
September 15, 2011
FN7018.2
Sync Separator, Low Power
Features
The EL1881 video sync separator is manufactured using
Elantec’s high performance analog CMOS process. This
device extracts sync timing information from both standard
and non-standard video input. It provides composite sync,
vertical sync, burst/back porch timing, and odd/even field
detection. Fixed 70mV sync tip slicing provides sync edge
detection when the video input level is between 0.5VP-P and
-2VP-P (sync tip amplitude 143mV to 572mV). A single
external resistor sets all internal timing to adjust for various
video standards. The composite sync output follows video in
sync pulses and a vertical sync pulse is output on the rising
edge of the first vertical serration following the vertical
pre-equalizing string. For non-standard vertical inputs, a
default vertical pulse is output when the vertical signal stays
low for longer than the vertical sync default delay time. The
odd/even output indicates field polarity detected during the
vertical blanking interval. The EL1881 is plug-in compatible
with the industry-standard LM1881 and can be substituted
for that part in 5V applications with lower required supply
current.
• NTSC, PAL, SECAM, non-standard video sync separation
The EL1881 is available in the 8 Ld PDIP and SOIC
packages and is specified for operation over the full -40°C to
+85°C temperature range
• Fixed 70mV slicing of video input levels from 0.5VP-P to
2VP-P
• Low supply current - 1.5mA typ.
• Single +5V supply
• Composite, vertical sync output
• Odd/even field output
• Burst/back porch output
• Available in 8 Ld PDIP and SOIC packages
• Pb-free available (RoHS Compliant)
Applications
• Video amplifiers
• PCMCIA applications
• A/D drivers
• Line drivers
• Portable computers
• High-speed communications
• RGB applications
Pinout
• Broadcast equipment
EL1881
(8 LD PDIP, SOIC)
TOP VIEW
COMPOSITE SYNC OUT 1
8
• Active filtering
Demo Board
VDD 5V
COMPOSITE VIDEO IN 2
7 ODD/EVEN OUTPUT
VERTICAL SYNC OUT 3
6
GND
A dedicated demo board is available.
RSET
5 BUST/BACK
PORCH OUTPUT
4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2004, 2011. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL1881
Pin Descriptions
PIN NUMBER
PIN NAME
PIN FUNCTION
1
Composite Sync
Out
Composite sync pulse output; sync pulses start on a falling edge and end on a rising edge
2
Composite Video
In
AC coupled composite video input; sync tip must be at the lowest potential (positive picture phase)
3
Vertical Sync Out
Vertical sync pulse output; the falling edge of vert sync is the start of the vertical period
4
GND
Supply ground
5
Burst/Back Porch
Output
Burst/back porch output; low during burst portion of composite video
6
RSET (Note 1)
An external resistor to ground sets all internal timing; a 681k 1% resistor will provide correct timing for
NTSC signals
7
Odd/Even Output
Odd/even field output; high during odd fields, low during even fields; transitions occur at start of vert sync
pulse
8
VDD 5V
Positive supply (5V)
NOTE:
1. RSET must be a 1% resistor
Ordering Information
PART NUMBER
PART MARKING
PACKAGE
PKG. DWG. #
EL1881CN
EL1881CN
8 Ld PDIP
E8.3
EL1881CS
1881CS
8 Ld SOIC
M8.15E
EL1881CS-T7 (Note 2)
1881CS
8 Ld SOIC (Tape & Reel)
M8.15E
EL1881CSZ (Notes 3, 4)
1881CSZ
8 Ld SOIC (Pb-free)
M8.15E
EL1881CSZ-T7 (Notes 2, 3, 4)
1881CSZ
8 Ld SOIC (Pb-free, Tape & Reel)
M8.15E
EL1881CSZ-T13 (Notes 2, 3, 4))
1881CSZ
8 Ld SOIC (Pb-free, Tape & Reel)
M8.15E
NOTES:
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
4. For Moisture Sensitivity Level (MSL), please see device information page for EL1881. For more information on MSL, please see Technical Brief
TB363.
2
FN7018.2
September 15, 2011
EL1881
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VCC Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V
Thermal Resistance (Typical, Note 5)
θJA (°C/W)
8 Lead PDIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
8 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
95 to 120
Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
VDD = 5V, TA = +25°C, RSET = 681kΩ, unless otherwise specified.
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
IDD, Quiescent
VDD = 5V
0.75
1.5
3
mA
Clamp Voltage
Pin 2, ILOAD = -100µA
1.35
1.5
1.65
V
Clamp Discharge Current
Pin 2 = 2V
6
12
16
µA
Clamp Charge Current
Pin 2 = 1V
-1.3
-1
0.7
mA
RSET Pin Reference Voltage
Pin 6
1.1
1.22
1.35
V
VOL Output Low Voltage
IOL = 1.6mA
0.24
0.5
V
VOH Output High Voltage
IOH = -40µA
4
4.8
V
IOH = -1.6mA
3
4.6
V
MIN
TYP
MAX
UNIT
Dynamic Specifications
PARAMETER
DESCRIPTION
Comp Sync Prop Delay, tCS
See Figure 20
20
35
75
ns
Vertical Sync Width, tVS
Normal or Default Trigger, 50% to 50%
190
230
300
µs
Vertical Sync Default Delay, tVSD
See Figure 21
35
62
85
µs
Burst/Back Porch Delay, tBD
See Figure 20
120
200
300
ns
Burst/Back Porch Width, tB
See Figure 20
2.5
3.5
4.5
µs
Input Dynamic Range
Video Input Amplitude to Maintain 50% Slice Spec
0.5
2
VP-P
Slice Level
VSLICE/VCLAMP
55
85
mV
3
70
FN7018.2
September 15, 2011
EL1881
Typical Performance Curves
1.535
RSET = 681kΩ
1.525
5V
1.55
4.5V
1.50
1.45
5V
4.5V
1.515
1.505
1.495
1.40
1.35
-50
-25
0
25
50
75
1.485
-50
100
-25
5.5V
1.230
5V
11.1
4.5V
10.9
5V
1.225
4.5V
1.220
1.215
1.205
-25
0
25
50
75
1.200
-50
100
-25
TEMPERATURE (°C)
1.10
75
100
800
RSET (kΩ)
1.00
4.5V
0.95
50
1000
5.5V
5V
25
FIGURE 4. VRSET vs TEMPERATURE
RSET = 681kΩ
1.05
0
TEMPERATURE (°C)
FIGURE 3. CLAMP DISCHARGE CURRENT vs
TEMPERATURE
CLAMP CHARGE CURRENT (mA)
100
1.210
10.8
600
400
200
0.90
0.85
-50
75
RSET = 681kΩ
5.5V
1.235
11.2
50
1.240
RSET = 681kΩ
11.3
10.7
-50
25
FIGURE 2. VCLAMP VOLTAGE vs TEMPERATURE
VRSET (V)
CLAMP DISCHARGE CURRENT (µA)
FIGURE 1. SUPPLY CURRENT vs TEMPERATURE
11.4
0
TEMPERATURE (°C)
TEMPERATURE (°C)
11.0
RSET = 681kΩ
5.5V
5.5V
1.60
VCLAMP (V)
SUPPLY CURRENT (mA)
1.65
-25
0
25
50
75
100
TEMPERATURE (°C)
FIGURE 5. CLAMP CHARGE CURRENT vs TEMPERATURE
4
0
10
15
20
25
30
35
40
45
FREQUENCY (kHz)
FIGURE 6. RSET vs HORIZONTAL FREQUENCY
FN7018.2
September 15, 2011
EL1881
Typical Performance Curves (Continued)
350
VDD = 5V, TA= +25°C
BURST/BACK PORCH DELAY (ns)
6
BURST WIDTH (µs)
5
4
3
2
1
200
400
600
800
VDD = 5V, TA= +25°C
300
250
200
150
100
50
0
200
1000
400
600
VERTICAL SYNC WIDTH (µs)
VDD = 5V, TA= +25°C
300
250
200
150
100
50
0
200
400
800
600
1000
120
VDD = 5V, TA= +25°C
100
80
60
40
20
0
200
400
600
RSET (kΩ)
1000
FIGURE 10. VERTICAL DEFAULT DELAY vs RSET
3.9
41
BURST/BACK PORCH WIDTH (µS)
COMPOSITE SYNC PROP DELAY (ns)
800
RSET (kΩ)
FIGURE 9. VERTICAL SYNC WIDTH vs RSET
39
37
35
33
31
-50
1000
FIGURE 8. BURST/BACK PORCH DELAY vs RSET
VERTICAL SYNC DEFAULT DELAY (µs)
FIGURE 7. BURST/BACK PORCH WIDTH vs RSET
350
800
RSET (kΩ)
RSET (kΩ)
-25
25
0
50
75
TEMPERATURE (°C)
FIGURE 11. COMPOSITE SYNC PROP DELAY vs
TEMPERATURE
5
100
3.8
3.7
3.6
5.5V
3.5
5V
3.4
4.5V
3.3
3.2
3.1
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
FIGURE 12. BURST/BACK PORCH WIDTH vs TEMPERATURE
FN7018.2
September 15, 2011
EL1881
Typical Performance Curves (Continued)
VERTICAL SYNC PULSE WIDTH (µs)
BURST/BACK PORCH DELAY (ns)
250
5.5V
200
150
5V
4.5V
100
50
RSET = 681kΩ
0
-50
-25
0
25
50
75
100
239
RSET = 681kΩ
5V
235
233
4.5V
231
229
-50
-25
0
25
FIGURE 13. BURST/BACK PORCH DELAY vs TEMPERATURE
100
20
5.5V
62.5
5V
61.5
4.5V
4.5V
18
tCS-VS (ns)
63.5
60.5
16
5V
14
5.5V
12
RSET = 681kΩ
RSET = 681kΩ
59.5
-50
-25
0
25
50
75
10
-50
100
-25
0
TEMPERATURE (°C)
1.4
POWER DISSIPATION (W)
RSET = 681kΩ
4.5V
23
5V
21
19
5.5V
17
0
25
50
75
100
TEMPERATURE (°C)
FIGURE 17. COMPOSITE SYNC TO ODD/EVEN DELAY TIME
6
75
100
JEDEC JESD51-3 Low Effective Thermal
Conductivity Test Board
1.2
1.25W
θ
1.0
PD
IP
8
+1
00
°C
/W
SO
θJ
8
A=
+1
60
°C
/W
JA
=
0.8
781mW
0.6
0.4
0.2
0
-25
50
FIGURE 16. COMPOSITE SYNC TO VERTICAL SYNC DELAY
TIME
27
25
25
TEMPERATURE (°C)
FIGURE 15. VERTICAL SYNC DEFAULT DELAY TIME vs
TEMPERATURE
tCS-OE (ns)
75
FIGURE 14. VERTICAL SYNC PULSE WIDTH vs
TEMPERATURE
64.5
15
-50
50
TEMPERATURE (°C)
TEMPERATURE (°C)
VERTICAL SYNC DEFAULT
DELAY TIME (µs)
5.5V
237
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7018.2
September 15, 2011
EL1881
Timing Diagrams
(Note 6)
Note 6
(Note 7)
(Note 8)
(Note 9)
(Note 10)
See Figures 20 and 21
See Figure 22
NOTES:
6. Signal 1a drawing reproduced with permission from EIA.
7. The composite sync output reproduces all the video input sync pulses, with a propagation delay.
8. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a
propagation delay.
9. Odd-even output is low for even field, and high for odd field.
10. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that
for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with
propagation delay).
FIGURE 19. STANDARD (NTSC INPUT) TIMING
7
FN7018.2
September 15, 2011
EL1881
Expanded Timing Diagrams
FIGURE 20. STANDARD VERTICAL TIMING
FIGURE 21. NON-STANDARD VERTICAL TIMING
8
FN7018.2
September 15, 2011
EL1881
Expanded Timing Diagrams (Continued)
FIGURE 22. STANDARD VERTICAL TIMING
Applications Information
Video In
Figure 24 shows a “Simplified Block Diagram” on page 11.
1mA. Here t = 590ns, about 12% of the sync pulse width of
4.7µs. It is important to choose C1 large enough so that the
droop voltage does not approach the switching threshold of
the internal comparator.
An AC-coupled video signal is input to Video In pin 2 via, C1
nominally 0.1µF. Clamp charge current will prevent the
signal on pin 2 from going any more negative than Sync Tip
Ref, about 1.5V. This charge current is nominally about 1mA.
A clamp discharge current of about 10µA is always
attempting to discharge C1 to Sync Tip Ref, thus charge is
lost between sync pulses that must be replaced during sync
pulses. The droop voltage that will occur can be calculated
from It = CV, where V is the droop voltage, I is the discharge
current, t is the time between sync pulses
(sync period - sync tip width), and C is C1.
Fixed Gain Buffer
An NTSC video signal has a horizontal frequency of
15.73kHz, and a sync tip width of 4.7µs. This gives a period
of 63.6µs and a time t = 58.9µs. The droop voltage will then
be V = 5.9mV. This is < 2% of a nominal sync tip amplitude
of 286mV. The charge represented by this droop is replaced
in a time given by t = CV/I, where I = clamp charge current =
Vertical Sync
9
The clamped video signal then passes to the fixed gain
buffer which places the sync slice level at the equivalent
level of 70mV above sync tip. The output of this buffer is
presented to the comparator, along with the slice reference.
The comparator output is level shifted and buffered to TTL
levels, and sent out as Composite Sync to pin 1.
Burst
A low-going Burst pulse follows each rising edge of sync,
and lasts approximately 3.5µs for an RSET of 681kΩ.
A low-going Vertical Sync pulse is output during the start of
the vertical cycle of the incoming video signal. The vertical
cycle starts with a pre-equalizing phase of pulses with a duty
cycle of about 93%, followed by a vertical serration phase
FN7018.2
September 15, 2011
EL1881
that has a duty cycle of about 15%. Vertical Sync is clocked
out of the EL1881 on the first rising edge during the vertical
serration phase. In the absence of vertical serration pulses,
a vertical sync pulse will be forced out after the vertical sync
default delay time, approximately 60µs after the last falling
edge of the vertical equalizing phase for RSET = 681kΩ.
Odd/Even
Because a typical television picture is composed of two
interlaced fields, there is an odd field that includes all the
odd lines, and an even field that consists of the even lines.
This odd/even field information is decoded by the EL1881
during the end of picture information and the beginning of
vertical information. The odd/even circuit includes a
T-flip-flop that is reset during full horizontal lines, but not
during half lines or vertical equalization pulses. The
T-flip-flop is clocked during each falling edge of these
half-period pulses. Even fields will toggle until a low state is
clocked to the odd/even pin 7 at the beginning of vertical
sync, and odd fields will cause a high state to be clocked to
the odd/even pin at the start of the next vertical sync pulse.
Odd/even can be ignored if using non-interlaced video, as
there is no change in timing from one field to the next.
RSET
An external RSET resistor, connected from RSET pin 6 to
ground, produces a reference current that is used internally
as the timing reference for vertical sync width, vertical sync
default delay, burst gate delay and burst width. Decreasing
the value of RSET increases the reference current, which in
turn decreases reference times and pulse widths. A higher
frequency video input necessitates a lower RSET value.
Chroma Filter
A chroma filter is suggested to increase the S/N ratio of the
incoming video signal. Use of the optional chroma filter is
shown in Figure 23. It can be implemented very simply and
inexpensively with a series resistor of 620Ω and a parallel
capacitor of 500pF, which gives a single pole roll-off
frequency of about 500kHz. This sufficiently attenuates the
3.58MHz (NTSC) or 4.43MHz (PAL) color burst signal, yet
passes the approximately 15kHz sync signals without
appreciable attenuation. A chroma filter will increase the
propagation delay from the composite input to the outputs.
FIGURE 23.
10
FN7018.2
September 15, 2011
EL1881
Simplified Block Diagram
CLAMP
SYNC TIP
REF
1.5V
C1
RF
620Ω
VDD
SLICE
1.57V
510pF
RSET
C3
RSET*
0.1µF
5V
C2
COMP.
0.1µF
GND
VDD
0.1µF
COMPOSITE
VIDEO IN
2
CF
8
+
1
COMPOSITE
SYNC
5
BURST/BACK
PORCH OUT
3
VERTICAL
SYNC OUT
7
ODD/EVEN
4
BURST
6
REF
GEN
SYNC
TIP
70mV
SLICE
VERT SYNC
ODD/EVEN
NOTE: * RSET MUST BE AT 1% RESISTOR
FIGURE 24.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN7018.2
September 15, 2011
EL1881
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
SEATING
PLANE
A2
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
0.204
C
D
0.355
0.400
9.01
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
eA
0.300 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
eB
-
L
0.115
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
5
D1
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
0.355
10.16
N
8
2.54 BSC
7.62 BSC
0.430
-
0.150
2.93
8
6
10.92
7
3.81
4
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
12
FN7018.2
September 15, 2011
EL1881
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
13
FN7018.2
September 15, 2011
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