DATASHEET

EL4501
®
Data Sheet
November 12, 2010
FN7327.3
Video Front End
Features
The EL4501 is a highly-integrated Video Front End (VFE)
incorporating all of the key signal conditioning functions for
analog video signals. It provides a flexible front-end interface
for analog or analog/digital video sub-systems. The VFE
contains a high bandwidth DC-restore, an advanced sync
separator and a data slicer with an adjustable threshold,
configurable output and power-down mode.
• DC-restore and sync separator
The VFE performs restoration of the DC level (blanking
level) of a video signal and the recovery of all signal timing
necessary for synchronization and control. Additionally, data
embedded in the active video or VBI regions of the video
signal may be extracted using the flexible data slicer
incorporated into the VFE. The advanced sync separator
exhibits excellent noise immunity by incorporating a digital
brick wall filter and signal qualification algorithm. The
DC-restored video amplifier is unity gain stable with an
unloaded -3dB bandwidth of 100MHz. The input common
mode voltage range extends from the negative rail to within
1.5V of the positive rail. When driving a 75Ω double
terminated coaxial cable, the amplifier can drive to within
150mV of either rail. With 200V/µs slew rate, the amplifier is
well suited for composite and component video applications.
• Diff gain/phase = 0.05%/0.03°, RL = 10kΩ, AV = 1
The VFE operates from a single 5V supply from -40°C to
+85°C and is available in a reduced footprint 24 Ld QSOP
package.
Ordering Information
PART
NUMBER
PART
TAPE &
MARKING REEL
PACKAGE
PKG.
DWG. #
• Wideband (100MHz) DC-restore
• Advanced sync separator
• Programmable data slicer
• Single 5V operation
• Low power (<75mW)
• Pb-free plus anneal available (RoHS compliant)
Applications
• Video capture & editing
• Video projectors
• Set top boxes
• Security video
• Embedded data recovery
Pinout
EL4501
(24 LD QSOP)
TOP VIEW
VFB 1
VIDEO IN 2
23 DS OUT
DS MODE 3
22 DS REF
DS ENABLE 4
EL4501IU
EL4501IU
-
24 Ld QSOP
MDP0040
EL4501IU-T7
EL4501IU
7”
24 Ld QSOP
MDP0040
EL4501IU-T13
EL4501IU
13”
24 Ld QSOP
MDP0040
GNDD 6
EL4501IUZ
(See Note)
EL4501IUZ
-
24 Ld QSOP
(Pb-free)
MDP0040
RFREQ 7
EL4501IUZ-T7
(See Note)
EL4501IUZ
7”
24 Ld QSOP
(Pb-free)
MDP0040
24 Ld QSOP
(Pb-free)
MDP0040
EL4501IUZ-T13 EL4501IUZ
(See Note)
13”
1
GND 5
FSEL 8
SYNC IN 9
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
24 VIDEO OUT
LOS 10
21 REF IN
20 REF OUT
19 VS
18 VSD
17 SYNC AMP
16 SLICE MODE
15 BACK PORCH
COMPOSITE 11
14 ODD/EVEN
HORIZONTAL 12
13 VERTICAL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
Copyright © Intersil Americas Inc. 2003-2004, 2006, 2010. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL4501
Absolute Maximum Ratings (TA = 25°C)
Supply Voltage (VS to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V
Pin Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . .GND -0.3V, VS +0.3V
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Continuous Current (VIDEO OUT) . . . . . . . . . . . . . 50mA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS = VSD = 5V, GND = 0V, TA = 25°C, Input Video = 1VP-P, RFREQ = 130kΩ
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
ISA
Input Supply Current
No load
7.5
10.5
13.5
mA
ISD
Digital Supply Current
No load, VIN = 0V
1.9
2.3
4
mA
VS
Input Supply Voltage Range
4.5
5.5
V
VSD
Digital Input Supply Voltage Range
4.5
5.5
V
VIDEO AMPLIFIER SECTION
VOP
Positive Output Voltage Swing (VIDEO OUT) RL = 150Ω to VS/2
(Note 1)
RL = 150Ω to GND
RL = 1kΩ to VS/2
VON
4.65
4.70
V
4.20
4.60
V
4.85
4.90
V
Negative Output Voltage Swing (VIDEO OUT) RL = 150Ω to VS/2
(Note 1)
RL = 150Ω to GND
RL = 1kΩ to VS/2
0.15
0.30
V
0.06
0.25
V
0.05
0.20
V
+IOUT
Positive Output Current (VIDEO OUT)
RL = 10Ω to VS/2
60
70
mA
-IOUT
Negative Output Current (VIDEO OUT)
RL = 10Ω to VS/2
-50
-60
mA
dG
Differential Gain Error (VIDEO OUT) (Note 2) AV = 1, RL = 10kΩ, RF = 0Ω
0.05
%
dP
Differential Phase Error (VIDEO OUT)
(Note 2)
AV = 1, RL = 10kΩ, RF = 0Ω
0.03
°
BW
Bandwidth
-3dB, G = 1, RL = 10kΩ to GND, RF = 0
100
MHz
-3dB, G = 1, RL = 150Ω to GND, RF = 0
60
MHz
8
MHz
96
V/µs
0/3.5
V
35
ns
BW1
Bandwidth
±0.1dB, G = 2, RL = 150Ω to GND
SR
Slew Rate
25% to 75%, 3.5VP-P, RL = 150Ω, RF = 0
VRL
Ref Level Range
tS
Settling Time
RIN
Input Resistance (VIDEO IN)
115
kΩ
CIN
Input Capacitance (VIDEO IN)
1.5
pF
AVOL
Open Loop Voltage Gain
RL = no load, VOUT = 0.5V to 3V
65
dB
RL = 150Ω to GND, VOUT = 0.5V to 3V
50
dB
0/3.5
V
±20
mV
10
µV/°C
80
to 0.1%, VIN = 0V to 3V
DC-RESTORE SECTION
CMIR
Common Mode Input Range (REF IN)
VOS
Input Offset Voltage
TCVOS
Input Offset Voltage Temperature Coefficient
IB
Input Bias Current (REF IN)
2
DC restored
VCM = 0V to 3.5V
-10
0.001
10
µA
EL4501
Electrical Specifications
PARAMETER
VS = VSD = 5V, GND = 0V, TA = 25°C, Input Video = 1VP-P, RFREQ = 130kΩ (Continued)
DESCRIPTION
VREF
Reference Output Voltage (REF OUT)
IRMAX
Available Restore Current (VFB)
CONDITIONS
IOUT = +2mA to -0.5mA
MIN
TYP
MAX
UNIT
1.15
1.3
1.4
V
18.5
µA
DATA SLICER SECTION
IIH
Input High Current (DS MODE & DS ENABLE) VIH = 5V
6
10
µA
IIL
Input Low Current (DS MODE & DS ENABLE) VIL = 0V
200
350
nA
VIH
Input High Voltage (DS MODE & DS ENABLE)
VIL
Input Low Voltage (DS MODE & DS ENABLE)
VOH
Output High Voltage (DS OUT)
IOUT = -1mA
VOL
Output Low Voltage (DS OUT)
IOUT = +1mA
IOUT
Short Circuit Current (DS OUT)
RL = 10Ω to 2.5V
IB
Input Bias Current (DS REF)
DS REF = 0V to 5V
VOS
Input Offset Voltage
VHYS
Hysteresis
tPD
Propagation Delay
tR/F
Rise/Fall Time
4.5
V
0.5
4.75
4.9
0.1
8
11
-10
0.001
-20
V
V
0.25
V
mA
10
µA
+20
mV
±5
mV
50% to 50%
18
ns
10% to 90%, RL = 150kΩ, CL = 5pF
1.2
ns
1000
Ω
SYNC SEPARATOR SECTION
ZSOURCE (MAX) Maximimum source impedance driving
SYNC IN
IIH
Input High Current (FSEL & SYNC MODE)
VIH = 5V
-1
1
µA
IIL
Input Low Current (FSEL & SYNC MODE)
VIL = 0V
-1
1
µA
VIH
Input High Voltage (FSEL & SYNC MODE)
VIL
Input Low Voltage (FSEL & SYNC MODE)
VOH
Output High Voltage
IOH = -1.6mA
VOL
Output Low Voltage
IOL = +1.6mA
VTHRSHA
Adaptive Slice Level
SYNC MODE = 0V
40
VTHRSHF
Fixed Slice Threshold
SLICE MODE = VS
80
VSI
SYNC IN Reference Voltage
1.8
V
RINSI
SYNC IN Input Impedance
115
kΩ
VRANGE
Input Dynamic Range
tCD
COMPOSITE Delay
FSEL = 0, from 50% of sync leading edge
25
tCDF
COMPOSITE Delay
FSEL = 1, from 50% of sync leading edge
tBD
BACK PORCH Delay
tBDF
4.5
V
0.5
4.6
V
V
0.4
V
50
60
%
100
120
mV
2.0
VP-P
35
45
ns
150
225
280
ns
FSEL = 0, from 50% of trailing sync edge
125
170
225
ns
BACK PORCH Delay
FSEL = 1, from 50% of trailing sync edge
250
420
550
ns
tHD
HORIZONTAL Delay
FSEL = 0/1, from 50% of sync leading edge
365
470
585
ns
tBW
BACK PORCH Width
FSEL = 0/1
2.8
3.2
4.1
µs
tHW
HORIZONTAL Width
FSEL = 0
1.1
1.3
1.5
µs
tHWF
HORIZONTAL Width
FSEL = 1
1.2
1.5
1.8
µs
tVW
VERTICAL Width
FSEL = 0/1, standard NTSC
196
198
200
µs
tVDD
VERTICAL Default Delay
FSEL = 0
26.5
31.2
35.9
µs
tVDDF
VERTICAL Default Delay
FSEL = 1
3
0.5
31.5
µs
EL4501
Electrical Specifications
PARAMETER
VS = VSD = 5V, GND = 0V, TA = 25°C, Input Video = 1VP-P, RFREQ = 130kΩ (Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
15
MAX
UNIT
130
kHz
fH
Horiz Scan Rate
VLOSE
Analog LOS Enable Threshold
Minimum sync amplitude to enable outputs
120
mV
VLOSD
Analog LOS Disable Threshold
Maximum sync amplitude to disable outputs
80
mV
tJIT
Output Jitter
All sync separator outputs
5
ns
ASA
SYNC AMP Gain
RSA
SYNC AMP Output Impedance
VRFREQ
RFREQ Reference Voltage
1.7
2.0
2.3
Ω
200
RFREQ = 13kΩ to 130kΩ
1.15
1.28
1.4
V
NOTES:
1. RL is Total Load Resistance due to Feedback Resistor and Load Resistor.
2. AC signal amplitude = 286mVPP, F = 3.58MHz, REF IN is swept from 0.8V to 3.4V, RL is DC coupled.
Typical Performance Curves
45
VREF_IN=1.3V
RL=150Ω
2
AV=1
RF=0Ω
0
AV=2
RF=1kΩ
-2
AV=5
RF=1kΩ
-4
-6
100K
1M
AV=1
RF=0Ω
0
PHASE (°)
NORMALIZED MAGNITUDE (dB)
4
AV=2
RF=1kΩ
-45
-90
AV=5
RF=1kΩ
-135
10M
VREF_IN=1.3V
RL=150Ω
-180
100K
100M
1M
FREQUENCY (Hz)
FIGURE 2. NON-INVERTING FREQUENCY RESPONSE
(PHASE)
8
RL=10kΩ
RL=1kΩ
0
RL=150Ω
-2
VREF_IN=1.3V
RF=0Ω
AV=1
-6
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 3. FREQUENCY RESPONSE FOR VARIOUS RL
4
NORMALIZED MAGNITUDE (dB)
NORMALIZED MAGNITUDE (dB)
4
2
100M
FREQUENCY (Hz)
FIGURE 1. NON-INVERTING FREQUENCY RESPONSE (GAIN)
-4
10M
CL=39pF
CL=15pF
4
0
CL=0pF
-4
-8
VREF_IN=1.3V
RF=150Ω
AV=1
-12
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 4. FREQUENCY RESPONSE FOR VARIOUS CL
EL4501
Typical Performance Curves (Continued)
4
4
2
RL=10kΩ
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
RF=2kΩ
RF=1kΩ
0
RF=500Ω
-2
-4
AV=2
RL=150Ω
-6
100K
1M
10M
2
RL=150Ω
0
RL=75Ω
-2
-4
AV=2
RF=1kΩ
-6
100K
100M
1M
FREQUENCY (Hz)
FIGURE 5. FREQUENCY RESPONSE FOR VARIOUS RF
CL=100pF
100
CL=68pF
2
CL=47pF
0
CL=15pF
-2
-4
CL=0pF
VREF_IN=1.3V
RF=1kΩ
RL=150Ω
AV=2
-6
100K
1M
10M
AV=1
RF=0Ω
10
1
0.1
10K
100M
100K
FIGURE 7. FREQUENCY RESPONSE FOR VARIOUS CL
PHASE
RL=10kΩ
50
30
-90
GAIN
RL=150Ω
-135
10
-10
1K
-45
-180
10K
100K
1M
10M
-270
100M
FREQUENCY (Hz)
FIGURE 9. OPEN LOOP GAIN AND PHASE vs FREQUENCY
5
PSRR, CMRR (dB)
GAIN
RL=10kΩ
10
PHASE (°)
GAIN (dB)
70
100M
10M
FIGURE 8. CLOSED LOOP OUTPUT IMPEDANCE
0
PHASE
RL=150Ω
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
90
100M
FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS RL
IMPEDANCE (Ω)
NORMALIZED MAGNITUDE (dB)
4
10M
FREQUENCY (Hz)
-10
-30
PSRR
VS
CMRR
-50
PSRR
VSD
-70
1K
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 10. PSRR AND CMRR vs FREQUENCY - VIDEO AMP
EL4501
Typical Performance Curves (Continued)
0.25
DIFFERENTIAL GAIN (%)
VOLTAGE NOISE (nV/√Hz)
10K
1K
100
10
10
100
1K
100K
10K
1M
10M
RF=0Ω
AV=1
0.2
0.15
RL=150Ω
0.1
0.05
0
RL=10kΩ
-0.05
-0.1
0.5
100M
1
1.5
FIGURE 11. VOLTAGE NOISE vs FREQUENCY - VIDEO AMP
0.04
RL=10kΩ
-0.04
RL=150Ω
-0.08
1
2
1.5
2.5
3
0.3
RL=150Ω
0.2
0.1
0
RL=10kΩ
-0.1
-0.2
0.5
3.5
1
1.5
RL=10kΩ
ACQUISITION TIME (µs)
DIFFERENTIAL PHASE (°)
1600
-0.05
-0.15
RL=150Ω
1
RF=1kΩ
AV=2
2
1.5
2.5
3
3.5
VOUT (V)
FIGURE 15. DIFFERENTIAL PHASE FOR RL TIED TO 0V
6
2.5
3
3.5
FIGURE 14. DIFFERENTIAL GAIN FOR RL TIED TO 0V
0.15
-0.35
0.5
2
VOUT (V)
FIGURE 13. DIFFERENTIAL PHASE FOR RL TIED TO 0V
-0.25
3.5
RF=1kΩ
AV=2
0.4
VOUT (V)
0.05
3
0.5
RF=0Ω
AV=1
0
-0.12
0.5
2.5
FIGURE 12. DIFFERENTIAL GAIN FOR RL TIED TO 0V
DIFFERENTIAL GAIN (%)
DIFFERENTIAL PHASE (°)
0.08
2
VOUT (V)
FREQUENCY (Hz)
AV=2
RF=1kΩ
RL=150Ω
1200
VIN=1V STEP
VREF_IN=13.V
800
400
0
0
100
200
300
400
500
HOLD CAPACITANCE (pF)
FIGURE 16. ACQUISITION TIME vs HOLD CAPACITANCE
EL4501
Typical Performance Curves (Continued)
25
RESTORE CURRENT (µA)
OFFSET VOLTAGE (mV)
25
20
15
10
5
0
0
0.5
1
2
1.5
2.5
3
3.5
20
15
10
5
0
-40
4
-20
VREF_IN (V)
HOLD STEP VOLTAGE (mV)
DROOP CURRENT (nA)
60
10
1
0.1
0.01
0.001
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
80
100
ΔV=ΔQ/CH
1
0.1
0.01
1
10
TEMPERATURE (°C)
1K
100
HOLD CAPACITANCE (pF)
FIGURE 19. DROOP CURRENT vs TEMPERATURE
FIGURE 20. HOLD STEP VOLTAGE vs HOLD CAPACITANCE
160
DR=ΔVRAMP/ΔT
140
10
LINE RATE (kHz)
DROOP RATE (mV/ms)
40
FIGURE 18. DC-RESTORE CURRENT vs TEMPERATURE
IDROOP=CH*(ΔVRAMP/ΔT)
100
20
TEMPERATURE (°C)
FIGURE 17. DC OFFSET VOLTAGE AT VOUT vs VREF_IN
10
0
1
0.1
120
100
80
60
40
20
0.01
1
10
100
1K
HOLD CAPACITANCE (pF)
FIGURE 21. DROOP RATE vs HOLD CAPACITANCE
7
0
0
20
40
60
80
100
120
RFREQ (kΩ)
FIGURE 22. LINE RATE vs RFREQ
140
EL4501
Typical Performance Curves (Continued)
4
BACK PORCH WIDTH,
HORIZONTAL SYNC WIDTH (µs)
160
LINE RATE (kHz)
140
120
100
80
60
40
20
0
10
100
3.5
3
BACK PORCH
2.5
HORIZONTAL
(FSEL=1)
2
1.5
1
HORIZONTAL
(FSEL=0)
0.5
0
200
0
20
40
RFREQ (kΩ)
FIGURE 23. LINE RATE vs RFREQ
DELAY TIME (ns)
500
HORIZONTAL
BACK PORCH
(FSEL=1)
200
100
0
BACK PORCH
(FSEL=0)
0
20
40
60
80
100
120
COMPOSITE SYNC DELAY (ns)
44
300
40
38
36
20
HORIZONTAL SYNC DELAY (ns)
COMPOSITE SYNC DELAY (ns)
500
236
232
228
20
40
60
80
100
TEMPERATURE (°C)
FIGURE 27. COMPOSITE DELAY vs TEMPERATURE FSEL = 1
8
0
20
40
60
80
100
FIGURE 26. COMPOSITE DELAY vs TEMPERATURE FSEL = 0
240
0
140
TEMPERATURE (°C)
RFREQ=130kΩ
20
120
42
34
-40
140
FIGURE 25. DELAY TIME vs RFREQ
224
-40
100
RFREQ=130kΩ
RFREQ (kΩ)
244
80
FIGURE 24. BACK PORCH AND HORIZONTAL SYNC WIDTH
vs RFREQ
600
400
60
RFREQ (kΩ)
RFREQ=130kΩ
495
490
485
480
475
470
-40
20
0
20
40
60
80
100
TEMPERATURE (°C)
FIGURE 28. HORIZONTAL DELAY vs TEMPERATURE
EL4501
Typical Performance Curves (Continued)
182
RFREQ=130kΩ
BACK PORCH DELAY (ns)
DATA SLICER DELAY (ns)
35
34
33
32
31
30
-40
20
0
20
40
60
80
RFREQ=130kΩ
180
178
176
174
172
170
168
-40
100
0
20
TEMPERATURE (°C)
FIGURE 29. DATA SLICER DELAY vs TEMPERATURE DS MODE = 1
3.72
RFREQ=130kΩ
435
430
425
420
415
410
-40
20
0
20
40
60
80
100
RFREQ=130kΩ
3.68
3.66
3.64
3.62
3.6
3.58
-40
100
0
20
20
40
80
60
100
TEMPERATURE (°C)
FIGURE 31. BACK PORCH DELAY vs TEMPERATURE FSEL = 1
FIGURE 32. BACK PORCH WIDTH vs TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
210
1.4
200
POWER DISSIPATION (W)
VERTICAL SYNC WIDTH (µs)
80
60
3.7
TEMPERATURE (°C)
190
180
170
160
RFREQ=130kΩ
150
-40
40
FIGURE 30. BACK PORCH DELAY vs TEMPERATURE FSEL = 0
BACK PORCH WIDTH (µs)
BACK PORCH DELAY (ns)
440
20
TEMPERATURE (°C)
20
0
20
40
60
80
100
TEMPERATURE (°C)
FIGURE 33. VERTICAL SYNC WIDTH vs TEMPERATURE
9
1.2
1
870mW
0.8
θ
QS
JA =
0.6
OP
11
5°
0.4
24
C/
W
0.2
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 34. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
EL4501
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
POWER DISSIPATION (W)
1.4
1.136W
1.2
1
θ
Q
JA
=
0.8
88
0.6
SO
P2
°C
/W
4
0.4
0.2
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 35. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Timing Diagrams
FIELDS ONE AND THREE
(ODD) COMPOSITE SIGNAL
COMPOSITE SYNC OUTPUT
BURST/BACK PORCH OUTPUT
HORIZONTAL SYNC OUTPUT
VERTICAL SYNC OUTPUT
ODD/EVEN OUTPUT
FIELDS TWO AND FOUR (EVEN)
COMPOSITE SIGNAL
COMPOSITE SYNC OUTPUT
BURST/BACK PORCH OUTPUT
HORIZONTAL SYNC OUTPUT
VERTICAL SYNC OUTPUT
ODD/EVEN OUTPUT
10
EL4501
Timing Diagrams
VIDEO IN
COMPOSITE SYNC OUTPUT
BURST/BACK PORCH OUTPUT
tCD
tBD
tBW
tHD
HORIZONTAL SYNC OUTPUT
tHW
VIDEO IN
VERTICAL SYNC OUTPUT
tCD+t
t<< tCD
tCD+2t
ODD/EVEN
Standard (NTSC Input) H. Sync Detail
tCD
tBW
11
EL4501
Pin Descriptions
PIN
NUMBER
PIN NAME
PIN TYPE
1
VFB
Input
PIN DESCRIPTION
Connection for gain and feedback resistors, RF and
RG
EQUIVALENT CIRCUIT
VS
GND
CIRCUIT 1
2
VIDEO IN
Input
Input to DC-restore amplifier; input coupling capacitor
connects from here to video source
VS
GND
CIRCUIT 2
3
DS MODE
Input
Sets the mode of the DS comparator; logic low selects
a standard logic output; logic high selects an open
drain/collector
VS
GND
CIRCUIT 3
4
DS ENABLE
Input
Enables the output of the comparator; a logic high
enables the comparator; a logic low three-states it
VS
GND
CIRCUIT 4
5
GND
Input
Analog ground
6
GNDD
Input
Digital ground
7
RFREQ
Input
Connection for bias resistor that sets the overall timing
VS
GND
CIRCUIT 5
12
EL4501
Pin Descriptions
PIN
NUMBER
PIN NAME
PIN TYPE
PIN DESCRIPTION
8
FSEL
Input
Enable/bypass internal brick wall filter; a logic high is
used to enable the filter; a logic low to disable it
EQUIVALENT CIRCUIT
VD
GND
CIRCUIT 6
9
SYNC IN
Input
Input to the sync separator; connects to the video
source via a coupling capacitor or to a color burst input
filter
VD
GND
CIRCUIT 7
10
LOS
Output
Loss of signal output; goes high if no input video signal
is detected
VS
GND
CIRCUIT 8
11
COMPOSITE
Output
Composite sync output
Reference circuit 8
12
HORIZONTAL
Output
Horizontal sync output
Reference circuit 8
13
VERTICAL
Output
Vertical sync output
Reference circuit 8
14
ODD/EVEN
Output
Odd/even field indicator output
Reference circuit 8
15
BACK PORCH
Output
Back porch output
Reference circuit 8
16
SLICE MODE
Input
17
SYNC AMP
Output
Low = 50% slicing level; high = 70mV fixed slicing level Reference circuit 8
Amplitude of sync tip; can be used to control AGC
circuit
VS
GND
CIRCUIT 9
18
VSD
Input
Digital power supply; nominally +5V
VSD
VS
GND
CIRCUIT 10
19
VS
Input
13
Analog power supply; nominally +5V
Reference circuit 10
EL4501
Pin Descriptions
PIN
NUMBER
PIN NAME
PIN TYPE
PIN DESCRIPTION
20
REF OUT
Output
Voltage reference for use as blanking level in low cost
system
EQUIVALENT CIRCUIT
VS
GND
CIRCUIT 11
21
REF IN
Input
DC voltage on this pin sets the DC-restore voltage and
output blanking level
VS
GND
CIRCUIT 12
22
DS REF
Input
Sets the slicing level or reference level for the
comparator
VS
GND
CIRCUIT 13
23
DS OUT
Output
Output of the data slicing comparator; the output is
either open drain or standard symmetrical logic
depending on the DS MODE pin
VS
GND
CIRCUIT 14
24
VIDEO OUT
Output
Output of DC-restore amplifier
VS
GND
CIRCUIT 15
14
EL4501
Block Diagram
VS
VSD
DS REF
DS MODE
+
-
DS OUT
DS ENABLE
INPUT
VIDEO
VIDEO IN
+
-
0.1µF
VIDEO OUT
RF
VFB
CHOLD
+
-
RG
REF IN
REF OUT
TRACK/
HOLD
SYNC IN
0.1µF
FILTER
1.3V
CREF
BACK PORCH
FSEL
COMPOSITE
SYNC
SEPARATOR
SYNC AMP
HORIZONTAL
LOS
VERTICAL
RFREQ
ODD/EVEN
GND
Applications Information
Product Description
The EL4501 is a video front-end sub-system comprised of a
video amplifier with DC-restore, an adjustable threshold data
slicer, and an advanced sync separator. The prime function
of the system is to DC-stabilize and buffer AC-coupled
analog video signals and to extract timing reference signals
embedded in the video signal. An adjustable threshold data
slicer incorporated into the EL4501 may be used to extract
data embedded within the active video or VBI regions of a
video signal.
Theory of Operation
DC-RESTORE LOOP
When video signals are distributed, it is common to employ
capacitive coupling to prevent DC current flow due to
differences in local grounds or signal reference levels.
However, the coupling capacitor causes the DC level of the
signal post capacitor to be dependent on the video
(luminance) content of the waveform. A DC-restore loop is
used to correct this behavior by moving a portion of the
video waveform to a DC reference level in response to a
control signal. When the loop is operating, DC drift
15
+
-
SLICE
MODE
GNDD
accumulates over a single line only, before it is corrected.
The peak value of drift is limited by the rate of the control
signal (typically video line rate) and the AC coupling time
constant.
The restore loop is comprised of a 100MHz forward video
amplifier, combined with a nulling amplifier and sample and
hold circuit. For maximum flexibility the hold capacitor is
placed off-chip, allowing the loop response rate to be tailored
for specific applications and minimizing hold-step problems.
The loop provides a restore current peak of ±20µA at room
temperature. Figure 36 shows the amplifier and S/H
connection. During normal operation the internally generated
DC-restore control signal is timed to the back porch of the
video waveform. Figure 37 shows an NTSC video signal,
along with the EL4501 BACK PORCH output. In operation,
BACK PORCH activates the S/H switch, completing the
nulling feedback loop and driving the video amplifier output
towards the reference voltage. At the end of BACK PORCH,
the external capacitor holds the correction voltage for the
remainder of the video line. In the absence of a valid input
signal, the chip generates a repetitive, arbitrary restore
control signal at the line rate set by the external resistor
RFREQ. Although uncorrelated to the input, the pulse
EL4501
prevents the amplifier output drifting significantly from the
DC-restore reference level. This improves start-up behavior
and speeds recovery after a signal drop-out. For ease of
use, the EL4501 provides a buffered 1.3V DC level normally
connected directly to the restore loop reference input (REF
IN). Alternatively, an external voltage between 0V and 3.5V,
connected to REF IN, can be used to set the restored level.
0.1µF
~1.8V
+
-
VIN
VOUT
CH
gM
GBWP = --------------2πC H
S/H
+
-
gM
VREF_IN
FIGURE 36. DC-RESTORE AMPLIFIER AND S/H
CONFIGURATION
INPUT
VIDEO
SIGNAL
BACK
PORCH
OUTPUT
CH1=500mV/DIV
CH3=5V/DIV
M=10µs
FIGURE 37. NTSC VIDEO SIGNAL WITH BACK PORCH
OUTPUT
Auto-Zero Loop Bandwidth
The gain bandwidth product (GBWP) of the auto-zero loop is
determined by the size of the hold capacitor and the
transconductance (gM1) of the sample and hold amplifier.
GBWP = gM1/(2π * CH), gM1 is about 1/(29kΩ), for
CH = 270pF, GBWP is 20kHz. For CH = 100pF, GBWP is
about 55kHz.
quantity is called the droop current. This droop current
produces a ramp in the hold capacitor voltage, which in turn
produces a similar voltage at the video amplifier output. The
droop rate at the video amplifier output can be found using
the following equation:
ΔV RAMP
DroopRate = -----------------------Δt
Assuming CH = 100pF, from the Droop Rate vs Hold
Capacitance curve, the droop rate is about 0.31mV/ms at the
video amplifier output at room temperature. In NTSC
applications, there is about 60µs between auto-zero periods.
Thus, there is (0.31mV/ms) * 60µs = 18.6µV. It is much less
than 0.5IRE (3.5mV). This drift is negligible.
Choice of Hold Capacitor
The EL4501 allows the user to choose the hold capacitor as
low as 1pF and it is still stable. A smaller hold capacitor has
a faster acquisition time and faster auto-zero loop response,
but would increase the droop and hold step error. Also, if the
acquisition time is too fast, it would probably give an image
with clamp streaking and low frequency noise with noisy
signals. Increasing the hold capacitor would increase the
acquisition time, lower the auto-zero loop response, lower
the droop and hold step error. See the performance curves
for the trade-off. Normally, in video (NTSC and PAL)
applications, a smooth acquisition might takes about 10 to
20 scan lines. For a hold capacitor equal to 270pF, the
acquisition time is about 10 lines. In the worse case, ambient
temperature is 85°C, the droop current is 2.2nA which
causes the output voltage ramp to about 0.49mV for 60µs.
This drift is negligible in most applications. Figure 38 shows
the input and output waveforms of the video amplifier while
the S/H is in sample mode. Applying a 1V step to the video
amplifier input, the output of the video amplifier jumps to
2.3V. Then, the auto-zero system tries to drive the video
output to the reference voltage, which is 1.3V. The
acquisition time takes about 10 NTSC scan lines.
CH=270pF
Charge Injection and Hold Step Error
Charge injection refers to the charge transferred to the hold
capacitor when switching to the hold mode. The charge
should ideally be 0, but due to stray capacitive coupling and
other effects, it is typically 6fC. This charge changes the hold
capacitor voltage by ΔV = ΔQ/CH and will shift the output
voltage of the video amplifier by ΔV. However, this shift is
small and can be negligible for the EL4501 (see the Hold
Step Voltage Error vs Hold Capacitance curve). Assuming
CH = 100pF, ΔV is about 60µV. There will be 60µV change at
the video amplifier output.
Droop Rate
When the S/H amplifier is in the hold mode, there is a small
current that leaks from the switch to the hold capacitor. This
16
VIDEO
AMP
OUTPUT
VIDEO
AMP
INPUT
CH1=500mV/DIV
CH2=1V/DIV
M=100µs
Auto-zero mechanism restores amplifier output to
1.3V after +1V step at input
FIGURE 38. INPUT AND OUTPUT WAVEFORMS WITH S/H IN
SAMPLE MODE
EL4501
DATA SLICER
The data slicer is a fast comparator with the output of the
video amplifier connected to its inverting input and the
DS REF connected to its non-inverting input. The DS OUT is
logical inverse of the video output sliced at the DS REF
voltage. The propagation delay from the video amplifier
output to the DS OUT is about 18ns. There is about 10mV
hysteresis added internally in the comparator to prevent the
oscillation at the DS OUT when the voltages at the two
inputs are very close or equal. An adjustable DS REF
voltage may be used to extract data embedded within the
active video or video blanking interval regions of a video
signal. Logic low at the DS ENABLE pin enables the
comparator and logic low lets the DS OUT be three-state.
The DS MODE pin sets the mode of the DS comparator.
Logic low at the DS MODE pin selects a standard logic
output and a logic high selects an open drain/collector
output.
VIDEO AMPLIFIER
The EL4501 DC-restore block incorporates a wide
bandwidth, single supply, low power, rail-to-rail output,
voltage feedback operational amplifier. The amplifier is
internally compensated for closed loop feedback gains of +1
or greater. Larger gains are acceptable but bandwidth will be
reduced according to the familiar Gain-Bandwidth product.
Connected in a voltage follower mode and driving a high
impedance load, the amplifier has a -3dB bandwidth of
100MHz. Driving a 150Ω load, the -3dB bandwidth reduces
to 60MHz while maintaining a 200V/µs slew rate.
CHOICE OF FEEDBACK RESISTOR, RF
The video amplifier is optimized for applications that require
a gain of +1. Hence, no feedback resistor is required.
However, for gains greater than +1, the feedback resistor
forms a pole with the hold capacitance. As this pole
becomes larger, phase margin is reduced. This causes
ringing in the time domain and peaking in the frequency
domain. Therefore, RF has some maximum value that
should not be exceeded for optimum performance. If a large
value of RF must be used, a small capacitor in the few
picofarad range in parallel with RF can help to reduce ringing
and peaking at the expense of reducing the bandwidth. As
far as the output stage of the amplifier is concerned, RF +
RG appear in parallel with RL for gains other than +1. As this
combination gets smaller, the bandwidth falls off.
Consequently RF also has a minimum value that should not
be exceeded for optimum performance.
• For AV = +1, RF = 0Ω is optimum
• For AV = +2, RF between 300Ω and 1kΩ is optimum
VIDEO PERFORMANCE
For good video signal integrity, an amplifier is required to
maintain the same output impedance and frequency
response as DC levels are changed at the output. This can
17
be difficult when driving a standard video load of 150Ω
because of the change in output current with DC level. A
look at the Differential Gain and Differential Phase curves
will help to obtain optimal performance. Curves are provided
for AV = +1 and +2, and RL = 150Ω and 10kΩ. As with all
video amplifiers, there is a common mode sweet spot for
optimum differential gain/differential phase. For example,
with AV = +1 and RL = 150Ω and the video level kept
between 1V and 3V, the amplifier will provide dG/dP
performance of 0.17%/0.07°. This condition is representative
of using the amplifier as a buffer driving a DC coupled,
double terminated, 75Ω coaxial cable. Driving high
impedance loads, such as signals on computer video cards
gives much better dG/dP performance. For AV = 1,
RL = 10kΩ, and the video level kept between 1V and 3V, the
dG/dP are 0.03%/0.02°.
SHORT-CIRCUIT CURRENT LIMIT
The EL4501 video amplifier has no internal short circuit
protection circuitry. Short circuit current of 90mA sourcing
and 65mA sinking typically will flow if the output is shorted
midway between the rails. If the output is shorted indefinitely,
the power dissipated could easily increase the die
temperature such that the part will be destroyed. Maximum
reliability is maintained if the output current never exceeds
±50mA. This limit is set by internal metal interconnect
limitations. Obviously, short circuit conditions must not be
allowed to persist or internal metal connections will be
damaged or destroyed.
DRIVING CABLES AND CAPACITIVE LOADS
The EL4501 video amplifier can drive 39pF loads in parallel
with 150Ω with 5dB of peaking. For less peaking in theses
applications a small series resistor of between 5Ω and 50Ω
can be placed in series with the output. However, this will
obviously reduce the gain slightly. If your gain is greater than
1, the gain resistor RG can be adjusted to make up for any
lost gain caused by the additional output resistor. Peaking
may also be reducing by adding a “snubber” circuit at the
output. A snubber is a resistor in series with a capacitor,
150Ω and 100pF being typical values. The advantage of a
snubber is that it does not draw DC load current.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, the back-termination series resistor decouples
the video amplifier from the cable and enables extensive
capacitive drive. However, other applications may have high
capacitive loads without a back-termination resistor. Again, a
small series resistor at the output can reduce peaking.
VIDEO SYNC SEPARATOR
The EL4501 includes an advanced sync separator, which is
used to generate the DC-restore control signal and seven
major sync outputs. The advanced sync separator operates
at a 5V DC (pin VSD) single-supply voltage. The input signal
source is composite video with levels of 0.5VP-P to 2.0VP-P.
EL4501
Low jitter, temperature-stable timing signals are generated
using a master time-base, embedded within the system. Line
rate is adjustable from 10kHz to 135kHz using a single
external resistor (RFREQ). An integrated, pin-selectable
digital filter tracks line rate and rejects high frequency noise
and video artifacts, such as color burst. In addition to the
digital filter, a window-based, time qualification scheme is
employed to improve recovered signal quality. During loss of
signal, all outputs are blanked to prevent output chatter
caused by input noise.
The maximum total source impedance driving the SYNC IN
pin should be 1kΩ or lower. Source impedances greater than
1kΩ may reduce the ability of the EL4501 to reliably recover
the sync signal.
Odd and Even Output
For a composite video signal that is interlaced, there is an
odd field that includes all the odd lines, and an even field that
consists of the even lines. The odd and even circuit tracks
the relationship of the horizontal pulses to the leading edge
of the vertical output and will switch on every field at the start
of vertical sync pulse interval. ODD/EVEN, pin 14 is high
during the odd field and low during the even field.
Sync Amplitude Output
The output voltage at the SYNC AMP output (pin 17) is
about 2 times the sync tip voltage. This signal can be used
for AGC applications. When there is no sync signal at the
input, the SYNC AMP output is 0V.
Loss of Sync Output
Composite Sync Output
The composite sync output is a reproduction of the signal
waveform below the composite video black level, with the
video completely removed. The composite video signal is
AC-coupled to SYNC IN (pin 9). The video signal passes
through a comparator whose threshold is controlled by the
SLICE MODE pin. The output of the comparator is buffered
to the COMPOSITE output (pin 11) as a CMOS logic signal.
Horizontal Sync Output
The horizontal circuit triggers on the falling edge of the sync
tip of the input composite video signal and produces a
horizontal output with pulse widths about 12 times the
internal oscillator clock. For NTSC video input, the pulse
width of the horizontal sync is 1.5µs, with the digital filter
selected. The half line pulses present in the input signal
during vertical blanking are removed with an internal
2H-eliminator circuit.
Vertical Sync Output
A low-going vertical sync pulse is generated during the start
of the vertical cycle of the incoming composite video signal.
The vertical output pulse is started on the first serration
pulse in the vertical interval and is ended on the second
rising edge during the vertical serration phase. In the
absence of vertical serration pulses, a vertical sync pulse will
be forced out after the vertical sync default delay time,
approximately 31µs after the last falling edge of the vertical
pre-equalizing pulse for RFREQ = 130kΩ.
Loss of video signal can be detected by monitoring the LOS
output at pin 10. LOS goes low indicating the EL4501 has
locked to the right line rate. LOS goes high indicating the
EL4501 is out of lock. When there is loss of sync, all the
sync outputs go high, except ODD/EVEN.
Digital Filter Operation
The EL4501 contains a user-selectable digital filter which
tracks the line rate and rejects high frequency noise and
video artifacts, such as color burst. Basically, the digital filter
delays all signals and filters out the pulses which are shorter
than the filters delay time. The digital filter greatly reduces
the jitters in the outputs. With the digital filter on, the jitter at
the composite sync output is only 2ns. Figure 39 shows the
jitter at the output when the digital filter is selected. However,
the output waveforms will be delayed from 150ns to 300ns
due to this filter. Refer to the performance curves for details.
Applying logic high to the FSEL pin, the digital filter is
enabled. Applying a logic low to the FSEL pin, the digital
filter is disabled.
Back Porch Output
In a composite video signal, the chroma burst is located on
the back porch of the horizontal blanking period and is also
the black level reference for the subsequent video scan line.
The back porch is triggered from the rising edge of the sync
tip. The pulse width of the back porch is about 29 times the
internal oscillator clock cycle. For the NTSC video input, the
pulse width of the back porch is about 3.5µs. In EL4501, the
back porch pulse controls the sample and hold switch of the
DC-restored loop.
18
CH2=2V/DIV
M=2ns
FIGURE 39. JITTER AT THE OUTPUTS WITH FSEL=1
RFREQ
An external RFREQ resistor, connected from pin 7 to ground,
produces a reference current that is used internally as the
timing reference for all the sync output delay time and output
pulse widths. Decreasing the value of RFREQ increases the
reference current and frequency of the internal oscillator,
EL4501
which in turn decreases the reference time and pulse width.
A higher frequency video input requires a lower RFREQ
value. The Line Rates vs RFREQ performance curve shows
the variation of line rate with RFREQ.
Slice Mode and Operation with VCRs
Normally the signal source for the EL4501 is assumed to be
clean and relatively noise free. If that is the case, the SLICE
MODE pin (pin 16) should be connected to ground, which
sets the slice level to 50% of the sync tip. Some signal
sources may have excessive video peaking, causing high
frequency video and chroma components to extend below
the black level reference, such as VCR signals which
generate lots of head switching noise. In this case, the
SLICE MODE pin should be connected to logic high which
sets the slice level to a fixed 100mV above the sync tip. Also,
a single pole chroma filter is required at the composite video
input to increase the S/N ratio of the incoming noisy video
signal. When the source impedance is low, typically 75Ω, a
620Ω resistor in series with the source and 470pF capacitor
to ground will form a low pass filter with a roll-off frequency of
about 550kHz. This bandwidth sufficiently attenuates the
3.58MHz (NTSC) or 4.43MHz (PAL) color burst signal and
high frequency spikes, yet passes the sync pulse portion
without appreciable attenuation. The chroma filter will
increase the propagation delay from the composite sync
input to the outputs. Applying a chroma filter, setting the
SLICE MODE pin and FSEL pin to high greatly improve the
noise immunity performance in VCR applications.
Output Drive Capability
The outputs of the sync separator are not designed to drive
heavy loads. For a 5V VDS, if the output is driving 5kΩ load
to ground, the output high voltage is about 4.9V. If the output
is driving 500Ω load, the output high voltage is down to 4.2V.
General
Power Dissipation
With the high output drive capability of the EL4501 video
amplifier, it is possible to exceed the 125°C Absolute
Maximum junction temperature under certain load current
conditions. It is important to calculate the maximum junction
temperature for a given application to determine if load
conditions or package type need to be modified for the
amplifier to remain in its safe operating region.
The maximum power dissipation allowed in a package is
determined according to:
T JMAX - T AMAX
P DMAX = --------------------------------------------Θ JA
where:
• TJMAX = Maximum junction temperature (125°C)
• TAMAX = Maximum ambient temperature (85°C)
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation in the package
The maximum power dissipation actually produced by an IC
is the product of total quiescent supply current and power
supply voltage, plus the power in the IC due to the load.
Assume no load at the sync separator outputs:
V OUT
P DMAX = V S × I SMAX + V SD × I SDMAX + ( V S - V OUT ) × ---------------RL
where:
• VS = Supply voltage
• VSD = Digital supply
• ISMAX = Maximum supply current
• ISDMAX = Maximum digital supply current
• VOUT = Maximum output voltage
• RL = Load resistance tied to ground
Board Layout
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance. Ground
plane construction is highly recommended. Lead lengths
should be as short as possible. The power supply pin must
be well bypassed to reduce the risk of oscillation. In normal
operation, where the GND pin is connected to the ground
plane, a single 4.7µF tantalum capacitor in parallel with a
0.1µF ceramic capacitor from VS to GND will suffice. To
reduce cross talk between the analog signal path and the
embedded sync separator, a separate digital supply pin, VSD
is included on the EL4501. This pin should be bypassed in a
similar manner to VS. For additional isolation a ferrite bead
may be added in line with the supply connections to both
pins. For good AC performance, parasitic capacitance
should be kept to a minimum. Use of wire wound resistors
should be avoided because of their additional series
inductance.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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19
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