DATASHEET

Auto-Adjusting Sync Separator for HD and SD Video
ISL59885
Features
The ISL59885 video sync separator extracts sync timing
information from both standard and non-standard video inputs
in the presence of Macrovision pulses. The ISL59885 provides
horizontal, vertical, and composite sync outputs as well as
SD/HDTV detection. An auto input frequency detect feature
automatically adapts to a wide range of video standards (it
does not need a different RSET resistor for different
frequencies). The vertical sync pulse is output on the rising
edge of the first vertical serration following the vertical
pre-equalizing string. For non-standard vertical inputs, a
default vertical pulse is output when the vertical signal stays
low for longer than the vertical sync default delay time. The
horizontal output gives horizontal timing with pre/post
equalizing pulses. Fixed 70mV sync tip slicing provides sync
edge detection when the video input level is between 0.5VP-P
and 2VP-P.
• NTSC, PAL, SECAM, HDTV, Non-standard Video Sync
Separation
The ISL59885 is available in an 8 Ld SOIC package and is
specified for operation over the full -40°C to +85°C
temperature range.
• Fixed 70mV Slicing of Video Input Levels from 0.5VP-P to
2VP-P
• Single 3V to 5V Supply
• Composite Sync Output
• Vertical Output
• Horizontal Output
• HDTV Detection
• Macrovision Compatible
• Available in 8 Ld SOIC Package
• Pb-free (RoHS Compliant)
Applications
• High-definition Video Equipment
Related Literature
• AN1269, “One Transistor Enables Clean HDTV and NTSC
Video Sync Separation”
• AN1316, “One Transistor Enables Clean HDTV and NTSC
Video Sync Separation”
• TB476, “Regenerating HSYNC from Corrupted SOG or CSYNC
during VSYNC”
CLAMP
SYNC TIP REF
1.5V
C1
RF
620Ω
CF
510pF
VDD
8
VDD
5V
C2
0.1µF
COMPOSITE
VIDEO IN
2
SLICE
1.57V
0.1µF
COMP.
+
1 COMPOSITE
SYNC
GND 4
CSET
C3
56nF
6
REF
GEN
SYNC
TIP
70mV
SLICE
HD
DETECTOR
5 HD
V SYNC
3 VERTICAL
SYNC OUT
H SYNC
7 HORIZONTAL
SYNC OUT
2H
ELIMINATOR
FIGURE 1. SIMPLIFIED BLOCK DIAGRAM
October 31, 2011
FN7442.8
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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ISL59885
Pin Configuration
Pin Descriptions
ISL59885
(8 LD SOIC)
TOP VIEW
COMPOSITE SYNC OUT 1
PIN
NUMBER
7 HORIZONTAL OUTPUT
VERTICAL SYNC OUT 3
6 CSET
GND 4
5 HD
PIN FUNCTION
1
Composite
Sync Out
Composite sync pulse output; sync pulses
start on a falling edge and end on a rising
edge.
2
Composite
Video In
AC-coupled composite video input; sync tip
must be at the lowest potential (positive
picture phase).
3
Vertical
Sync Out
Vertical sync pulse output; the falling edge
of vertical sync is the start of the vertical
period.
4
GND
5
HD
6
CSET
7
Horizontal
Output
8
VDD
8 VDD
COMPOSITE VIDEO IN 2
PIN NAME
Supply ground
Low when input horizontal frequency is
greater than 25kHz.
(An external capacitor to ground); bypass
pin for internal bias generator.
Horizontal output; falling edge active
Positive supply
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
ISL59885ISZ
59885 ISZ
ISL59885ISZ-EVAL
Evaluation Board
TEMP RANGE
(°C)
-40 to +85
PACKAGE
(Pb-free)
8 Ld SOIC
PKG. DWG. #
M8.15E
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL59885. For more information on MSL, please see Tech Brief TB363.
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ISL59885
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VDD Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VCC +0.5V
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld SOIC Package (Notes 4, 5) . . . . . . . . .
120
66
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Ambient Temperature Range . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For θJC, the “case temp” location is taken at the package top center.
DC Electrical Specifications
operating temperature range, -40°C to +85°C.
VDD = 3.3V, TA = +25°C, CSET = 56nF, unless otherwise specified. Boldface limits apply over the
PARAMETER
DESCRIPTION
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
1
2.2
4
mA
1.35
1.5
1.65
V
IDD, Quiescent
VDD = 3.3V
Clamp Voltage
Pin 2, ILOAD = -100µA
Clamp Discharge Current
Pin 2 = 2V
6
15
30
µA
Clamp Charge Current
Pin 2 = 1V
-9
-7.2
-5.2
mA
VOL Output Low Voltage
IOL = 1.6mA
0.24
0.5
V
VOH Output High Voltage
IOH = -40µA
3
3.2
V
IOH = -1.6mA
2.5
3.0
V
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Dynamic Characteristics
Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
DESCRIPTION
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
Comp Sync Prop Delay, tCS
(See Figure 9)
35
75
ns
Horizontal Sync Delay, tHS
(See Figure 9)
40
80
ns
Horizontal Sync Width, tHS-PW
(See Figure 9)
3.8
5.2
6.2
µs
Vertical Sync Width, tVS
Normal or default trigger, 50% to 50%
(see Figure 7)
230
280
350
µs
Vertical Sync Default Delay, tVSD
(See Figure 10)
28
50
68
µs
70
80
90
%
2
VP-P
90
mV
Hsync Blanking Window
Input Dynamic Range
Video input amplitude to maintain slice level
spec, VDD = 3.3V
0.5
Slice Level
VSLICE above VCLAMP
50
HD Pin Level
720p, 1080i, 1080p
3
70
0
V
FN7442.8
October 31, 2011
ISL59885
Typical Performance Curves
VDD = 3.3 AND 5.0V
VCSET (V)
HSYNC PULSE WIDTH (ns)
VDD = 3.3 AND 5.0V
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
HSYNC FREQUENCY (Hz)
HSYNC (Hz)
FIGURE 2. HSYNC vs VCSET (RSET = OPEN)
FIGURE 3. HSYNC PULSE WIDTH vs HSYNC FREQUENCY
(RSET = OPEN)
HSYNC BLANKING TIME (µs)
VDD = 3.3 AND 5.0V
VIN
0.5V/DIV
5V/DIV
HSYNC
5V/DIV
VSYNC
5V/DIV
CSYNC
100µs/DIV
VCSET (V)
FIGURE 4. HSYNC vs VCSET (RSET = OPEN)
MAX POWER DISSIPATION (W)
1.2
1.0
FIGURE 5. MACROVISION COMPATIBILITY (NTSC)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
8 PIN SOIC PACKAGE
θJA= 120°C/W
0.8
0.6
0.4
0.2
0
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
AMBIENT TEMPERATURE (°C)
FIGURE 6. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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ISL59885
SIGNAL 1a. COMPOSITE VIDEO INPUT, FIELD ONE
1.5µs ±0.1µs
TIME
VERTICAL BLANKING INTERVAL = 20H
3H
H SYNC
INTERVAL
H
3H
3H
2
3
4
START OF
H
FIELD ONE
PREEQUALIZING
PULSE INTERVAL
H
1
+63.5µs
+H
1271µs
-0µs
-H
5
6
7
8
9
10
0.5H
VERTICAL SYNC
PULSE INTERVAL
POSTEQUALIZING
PULSE INTERVAL
9 LINE VERTICAL INTERVAL
19
20
21
H
REF SUBCARRIER PHASE,
COLOR FIELD ONE
SIGNAL 1b. COMPOSITE SYNC OUTPUT, PIN 1
SIGNAL 1c. VERTICAL SYNC OUTPUT, PIN 3
tVS
SIGNAL 1d. HORIZONTAL SYNC OUTPUT, PIN 7
NOTES:
7. The composite sync output reproduces all the video input sync pulses, with a propagation delay.
8. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay.
9. Horizontal sync output produces the “H” pulses of nominal width of 5µs. It has the same delay as the composite sync.
FIGURE 7. TIMING DIAGRAM
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ISL59885
CONDITIONS: VDD = 3.3V/5V, TA = +25°C
WHITE LEVEL
COLOR BURST
INPUT
DYNAMIC
RANGE
0.5V TO 2V
VIDEO
SYNC LEVEL
SYNC IN
VSLICE
50%
SYNC
TIP
tdSYNCOUT
VBLANK
(BLANKING LEVEL
VOLTAGE)
SYNC
VSYNC
(SYNC TIP
VOLTAGE)
DEPENDS ON WIDTH OF INPUT SYNC AT 50% LEVEL
SYNC OUT
HOUT
tdHOUT
tHOUT
FIGURE 8. HORIZONTAL INTERVAL 525/625 LINE COMPOSITE
PARAMETER
DESCRIPTION
CONDITIONS
TYP
(Note 10)
UNIT
tdSYNCOUT
SYNCOUT Timing Relative to Input
(See Figure 8)
65
ns
tdHOUT
HOUT Timing Relative to Input
(See Figure 8)
470
ns
tHOUT
Horizontal Output Width
(See Figure 8)
5.2
µs
NOTES:
10. Delay variation is less than 2.5ns over-temperature range.
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October 31, 2011
ISL59885
SIGNAL 2a.
COMPOSITE
VIDEO INPUT
SLICE LEVEL
70mV
tCS COMP SYNC
PROP DELAY
SIGNAL 2b.
COMPOSITE
SYNC OUTPUT
tCS-VS COMP SYNC VERT SYNC DELAY
SIGNAL 2c.
VERTICAL
SYNC OUTPUT
SIGNAL 2d.
HORIZONTAL
SYNC OUTPUT
tHS
tHS-PW
FIGURE 9. STANDARD VERTICAL TIMING
LINES
SIGNAL 3a.
COMPOSITE
VIDEO INPUT
2
3
4
5
(NO VERTICAL SYNC PULSES)
tVSD
SIGNAL 3b.
VERTICAL
SYNC OUTPUT
VERT SYNC
DEFAULT DELAY
FIGURE 10. NON-STANDARD VERTICAL TIMING
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ISL59885
COMPOSITE VIDEO INPUT, BEGINNING OF FIELD ONE
START OF FIELD ONE
622
623
624
625
1
2
3
4
5
6
7
23
24
SYNCOUT OUTPUT
VOUT OUTPUT
tVS
HOUT OUTPUT
NOTES:
11. The composite sync output reproduces all the video input sync pulses, with a propagation delay.
12. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay.
FIGURE 11. EXAMPLE OF VERTICAL INTERVAL (625)
SYNCIN
1123
1124
1125
560
561
562
1
2
3
564
565
4
5
6
567
568
7
8 ...
21
569
570 ... 583
SYNCOUT
HOUT
VOUT
SYNCIN
563
566
SYNCOUT
HOUT
VOUT
FIGURE 12. EXAMPLE OF HDTV 1080I/30 LINE COMPOSITE VIDEO: INTERLACED
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ISL59885
SYNCIN
1245
1246
1247
1248
1249
1250
620
621
622
623
624
625
1
2
3
4
5 ...
48
SYNCOUT
HOUT
VOUT
SYNCIN
626
627
628
629
630 ... 673
SYNCOUT
HOUT
VOUT
FIGURE 13. HDTV 1080I/25 LINE COMPOSITE VIDEO: INTERLACED (1250 LINES)
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ISL59885
CONDITIONS: VDD = 3.3V/5V, TA = +25°C
SYNCIN
SYNC OUT
HOUT
tdSYNCOUT
tdHOUT
tHOUT
FIGURE 14. HORIZONTAL INTERVAL (HDTV) (720p)
H TIMING FOR HDTV, NO FILTER (USING 720P INPUT SIGNAL)
PARAMETER
DESCRIPTION
CONDITIONS
TYP @ 3.3V
(Note 13)
TYP @ 5V
(Note 13)
UNIT
tdSYNCOUT
SYNCOUT Timing Relative to Input
(See Figure 14)
56
50
ns
tdHOUT
HOUT Timing Relative to Input
(See Figure 14)
48
36
ns
tHOUT
Horizontal Output Width
(See Figure 14)
1.90
1.90
µs
NOTES:
13. Delay variation is less than 2.5ns over-temperature range.
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ISL59885
CONDITIONS: VDD = 3.3V/5V, TA = +25°C
SYNCIN
tdSYNCOUT
SYNC OUT
HOUT
tdHOUT
tHOUT
FIGURE 15. HORIZONTAL INTERVAL (HDTV) (720p)
H TIMING FOR HDTV, WITH FILTER (USING 720P INPUT)
PARAMETER
DESCRIPTION
CONDITIONS
TYP @ 3.3V
(Note 14)
TYP @ 5V
(Note 14)
UNIT
tdSYNCOUT
SYNCOUT Timing Relative to Input
(See Figure 15)
120
110
ns
tdHOUT
HOUT Timing Relative to Input
(See Figure 15)
112
100
ns
tHOUT
Horizontal Output Width
(See Figure 15)
200
200
ns
NOTES:
14. Delay variation is less than 2.5ns over-temperature range.
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ISL59885
Applications Information
CSET
Video In
An external CSET capacitor is connected from CSET pin 6 to
ground. The CSET capacitor should be a X7R grade or better
because the Y5U general use capacitors may be too leaky and
cause faulty operation. The CSET capacitor should be very close
to the CSET pin to reduce possible board leakage. A setting of
56nF is recommended (see “CSET Bias Block Diagram” on
page 13). The CSET capacitor rectifies a 5µs pulse current and
creates a voltage on CSET. The CSET voltage is converted to bias
current for HSYNC and VSYNC timing.
See the “Simplified Block Diagram” on page 13.
An AC-coupled video signal is input to Video In pin 2 via C1,
nominally 0.1µF. Clamp charge current prevents the signal on
pin 2 from going any more negative than Sync Tip Ref, about
1.5V. This charge current is nominally about 1mA. A clamp
discharge current of about 10µA is always attempting to
discharge C1 to Sync Tip Ref; thus, charge is lost between sync
pulses that must be replaced during sync pulses. Droop voltage
can be calculated from It = CV, where V is the droop voltage, I is
the discharge current, t is the time between sync pulses (sync
period-sync tip width), and C is C1.
An NTSC video signal has a horizontal frequency of 15.73kHz
and a sync tip width of 4.7µs. This gives a period of 63.6µs and a
time of t = 58.9µs. The droop voltage will then be V = 5.9mV. This
is less than 2% of a nominal sync tip amplitude of 286mV. The
charge represented by this droop is replaced in a time given by
t = CV/I, where I = clamp charge current = 5.3mA. Here,
t = 590ns, about 12% of the sync pulse width of 4.7µs. It is
important that C1 be large enough that droop voltage does not
approach the switching threshold of the internal comparator.
Chroma Filter
A chroma filter is suggested to increase the S/N ratio of the
incoming video signal. Use of the optional chroma filter is shown
in Figure 16. It can be implemented very simply and
inexpensively with a series resistor of 100Ω and a capacitor of
570pF, which gives a single pole roll-off frequency of about
2.79MHz during NTSC or PAL. This sufficiently attenuates the
3.58MHz (NTSC) or 4.43MHz (PAL) color burst signal, yet passes
the approximately 15kHz sync signals without appreciable
attenuation. During HDTV, the transistor turns off and a 100pF
capacitor is left to filter any noise present at the input. A chroma
filter will increase the propagation delay from the composite
input to the outputs.
Composite Sync
ISL59885
CHROMA FILTER
The composite sync output is simply a reproduction of the input
signal with the active video removed. The sync tip of the
composite video signal is clamped to 1.5V at pin 2 and then
slices at 70mV above the sync tip reference. The output signal is
buffered out to pin 1. When there is loss of sync, the composite
sync output is held low.
VIDEO IN
0.1µF
100Ω
CF
100pF
Vertical Sync
A low-going vertical sync pulse is output during the start of the
vertical cycle of the incoming video signal. The vertical cycle
starts with a pre-equalizing phase of pulses with a duty cycle of
about 93%, followed by a vertical serration phase that has a duty
cycle of about 15%. Vertical sync is clocked out of the ISL59885
on the first rising edge during the vertical serration phase. In the
absence of vertical serration pulses, a vertical sync pulse is
forced out after the vertical sync default delay time, which is
approximately 60µs after the last falling edge of the vertical
equalizing phase.
RF
CF2
470pF
1 CSYNC
VDD 8
2 CVIN
HOUT 7
3 VSYNC
CSET 6
4 GND
HD 5
10kΩ
MMBT3904
FIGURE 16. OPTIONAL CHROMA FILTER
HD-Detect
High definition video is flagged by HD going low when the input
horizontal frequency is greater than 25kHz.
Horizontal Sync
The horizontal block senses the leading edges of the composite
sync signal and generates horizontal pulses of nominal width
5.2µs. Any half line pulses present in the input signal during
vertical blanking are removed with an internal 2H line eliminator
function that inhibits retriggering of horizontal output pulses until
70% of the line time is reached. Then, the horizontal output
operation is enabled again. Any signals present on the I/P signal
after the real H sync are ignored; thus, the horizontal output is
not affected by MacroVision copy protection. When there is a loss
of incoming composite sync, the horizontal sync output is held
high.
12
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October 31, 2011
ISL59885
Simplified Block Diagram
CLAMP
SYNC TIP REF
1.5V
C1
RF
620Ω
CF
510pF
VDD
8
VDD
C2
5V
0.1µF
COMPOSITE
VIDEO IN
2
SLICE
1.57V
0.1µF
COMP.
+
1 COMPOSITE
SYNC
HD
DETECTOR
5 HD
GND 4
CSET
C3
56nF
6
REF
GEN
SYNC
TIP
70mV
SLICE
V SYNC
3 VERTICAL
SYNC OUT
H SYNC
7 HORIZONTAL
SYNC OUT
2H
ELIMINATOR
CSET Bias Block Diagram
VDD
CSYNC
PULSE
5µs
VDD
CSET
+
-
56nF
IBIAS - TIMING
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without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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13
FN7442.8
October 31, 2011
ISL59885
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
5/25/2011
FN7442.8
CHANGE
• On page 1, removed “Demo Board” section and included ISL59885ISZ-EVAL evaluation board in Ordering
Information on page 2.
• On page 2, Pin Descriptions table: changed HD pin function from “Low when input horizontal frequency is
greater than 20kHz." to "Low when input horizontal frequency is greater than 25kHz."
• On page 2, Ordering Information table: removed ISL59885IS; obsolete. Changed Package Drawing Number
for ISL59885ISZ from MDP0027 (obsolete) to M8.15E. Added ISL59885ISZ-EVAL evaluation board.
• On page 3, Thermal Information: added ΘJA value of 120°C.
• On page 4, modified Figure 6, “PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE” to reflect ΘJA
value of 120°C instead of 110°C. Removed Figure 7, which showed ΘJA of 160°C measured on low
effective thermal conductivity board, as it is not relevant.
• On page 12, under HD-Detect: text changed from "High definition video is flagged by HD going low when the
input horizontal frequency is greater than 20kHz." to "High definition video is flagged by HD going low when
the input horizontal frequency is greater than 25kHz."
5/12/2009
FN7442.7
• Pg 2, DC Electrical Specifications: Changed MIN spec for IDD, Quiescent from 1.5mA to 1mA
• Added Hsync Blanking Window spec to Dynamic Characteristics Table
• Pg 5, Figure 8: Timing Diagram. Revised Note 4 re: Horizontal Sync Output.
• Pg 11, Horizontal Sync: updated text in this section.
• Pg 12: renamed CSET Bias Circuit to CSET Bias Block
8/15/2007
FN7442.6
• Pg 1, revised first paragraph.
• Updated Ordering Information table (removed all custom parts).
• Updated Package Outline Drawing to most recent revision.
8/9/2006
FN7442.5
• Added ISL59885ISZR5260 and ISL598851SZ-T7R5260 to Ordering Information.
• Updated Features on pg 1 and Dynamic Characteristics table.
1/23/2006
FN7442.4
• Changed VCC to VDD.
• Changed Vs to VDD.
9/8/2005
FN7442.3
• Pg 1, Ordering Information: added “ISL59885ISR5218” “ISL59885IS-T7R5218” “ISL59885IS-T13R5218”
“ISL59885ISZR5218” “ISL59885ISZ-T7R5218” and “ISL59885ISZ-T13R5218”.
• Pg 2, Pin Descriptions, CSET, removed “and resistor” in the sentence “(An external capacitor and resistor to
ground).
7/7/2005
FN7442.2
• Replaced microvision scope photo.
• Corrected Csync output waveform.
• Removed Rset resistor.
5/20/2005
FN7442.1
• Updated Ordering information with latest parts.
5/11/2005
FN7442.0
• Initial Release
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14
FN7442.8
October 31, 2011
ISL59885
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
15
FN7442.8
October 31, 2011
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