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ESheet
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Data
June 11, 2008
O
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ct ou RSIL or
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8-INT
1-88
Quad Channel, Single Supply, Video
Reconstruction Filter with On-Board
Charge Pump
• 3.3V Nominal Supply, Operates Down to 3.0V
Ordering Information
ISL59834IRZ
PART
MARKING
TEMP.
RANGE
(°C)
FN6268.1
Features
The ISL59834 is a quad channel, single supply, video
reconstruction filter with integrated charge pump. It is
designed to operate on a single supply (3.0V to 3.6V) and
generate its own negative supply (-1.5V) using a regulated
charge pump. Input signals to the ISL59834 can be AC- or
DC-coupled. When AC-coupled, the backporch clamp sets
the blank level to ground at the output. Channels 1 and 3
have a sync detector whose output is available at
SYNC_OUTA and SYNC_OUTB, respectively. SYNC_INA
and SYNC_INB are inputs that provide timing for Channel 2
and Channel 4, respectively. Channel 2 and Channel 4 have
keyed clamps, which set the outputs to ground when
SYNC_INA or SYNC_INB are driven to the logic high state.
Each of the four outputs are capable of driving two DC or
AC-coupled standard video loads. The ISL59834 features a
4th order Butterworth reconstruction filter that provides a
9MHz nominal -3dB frequency and 40dB of attenuation at
27MHz. Nominal operational current is 63mA. When
powered down, the device draws 5µA maximum supply
current. The ISL59834 is available in a 44 Ld 7x7 QFN
package.
PART
NUMBER
(NOTE)
ISL59834
• DC-Coupled Outputs
• Inputs can be AC- or DC-Coupled
• Eliminates the Need for Large Output Coupling Capacitor
• Integrated Sync Tip Clamp sets the Backporch to Ground
at the Output for Channels 1 and 3
• Integrated Keyed Clamp puts Channel 2 and Channel 4
Outputs to Ground During Sync
• Each Output Drives 2 Standard Video Loads
• Response Flat to 5MHz with 40dB Attenuation at 27MHz
• Pb-Free (RoHS compliant)
Applications
• Set-Top Box Receiver
• Television
• DVD Player
• Digital Camera
• Cell Phone
Block Diagram
PACKAGE
(Pb-Free)
59 834IRZ -40 to +85 44 Ld QFN
PKG.
DWG. #
ISL59834
CHANNEL 1
L44.7x7A
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
VIDEO IN
(Y)
CLAMP +
SYNC
DETECTOR
LPF
9MHz
x2
VIDEO OUT
(Y)
CHARGE PUMP
CHANNEL 2
VIDEO IN
(C)
KEYED
CLAMP
LPF
9MHz
x2
VIDEO OUT
(C)
CHARGE PUMP
CHANNEL 3
VIDEO IN
(Y)
CLAMP +
SYNC
DETECTOR
LPF
9MHz
x2
VIDEO OUT
(Y)
CHARGE PUMP
CHANNEL 4
VIDEO IN
(C)
KEYED
CLAMP
LPF
9MHz
x2
VIDEO OUT
(C)
CHARGE PUMP
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL59834
Pinout
IN1
NC
ENABLEA
VS
NC
CLKA
NC
SYNC_OUTA
SYNC_INA
NC
OUT1
ISL59834
(44 LD QFN)
TOP VIEW
44
43
42
41
40
39
38
37
36
35
34
30 CAPA+
VCPA
5
29 CAPA-
VS
6
28 CLKB
ENABLEB
7
27 SYNC_OUTB
IN3
8
26 SYNC_INB
GND
9
25 OUT3
IN4
10
24 OUT4
GND
11
23 VEEBIN
2
12
13
14
15
16
17
18
19
20
21
22
VEEBOUT
4
NC
GNDCPA
CAPB+
31 VEEAOUT
CAPB-
3
NC
GND
NC
32 VEEAIN
NC
2
VCPB
IN2
GNDCPB
33 OUT2
NC
1
NC
GND
FN6268.1
June 11, 2008
ISL59834
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V
VIN to GND. . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VS + 0.3V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . ±50mA
Maximum Current into Any Pin . . . . . . . . . . . . . . . . . . . . . . . ±50mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .3500V
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .350V
Thermal Resistance (Typical, Note 1)
JA (°C/W)
44 Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
NOTE:
1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
Electrical Specifications
SYMBOL
VCP = VS = 3.3V, CF1 = CF2 = 0.1µF, CS1 = CS2 = 0.22µF, CFIL1 = CFIL2 = 0.4µF, CIN1 = CIN2 = CIN3 = CIN4 =
0.1µF, RL1 = RL2 = 150, Typical TA = +27°C.
PARAMETER
CONDITIONS
MIN
(Note 2)
TYP
MAX
(Note 2)
UNIT
3.0
3.3
3.6
V
-1.75
-1.5
-1.25
V
28
32
mA
DC CHARACTERISTICS
VS, VCP
Supply Range
Guaranteed by PSRR
VEEOUT
Charge Pump Output
Measured at VEEIN
IS
Supply Current
No load
ICP
Charge Pump Supply Current
No load
35
40
mA
IPD
Power-down Current
ENABLE = 0.4V
0.6
5
µA
IIN
Input Pull-down Current
Channels 1 and 3, VIN = 0.5V
0.4
4
10
µA
IB
Input Bias Current
Channels 2 and 4, VIN = 0.5V, SYNC_IN = 0V
-10
-3
10
µA
AV
DC Gain
1.94
2
2.05
V/V
Max DC Input Range
DC-coupled input, guaranteed by DC gain test
VCLAMPOUT1
Output Sync Tip Clamp Level
(Channels 1 and 3)
VIN  0, AC-coupled input
-650
-590
-525
mV
VCLAMPOUT2
Keyed Clamp Level
(Channels 2 and 4)
Output level when SYNC_IN  2.0V
-60
-25
0
mV
VCLAMPIN1
Input Clamp Level
(Channels 1 and 3)
Input floating
0
30
70
mV
VCLAMPIN2
Input Keyed Clamp Level
(Channels 2 and 4)
Input floating, input level when SYNC_IN 2.0V
275
300
375
mV
Output Level Shift
(Channels 1 and 3)
VIN0, output shifted relative to input, DC-coupled
input
-685
-620
-550
mV
Output Level Shift
(Channels 2 and 4)
VIN0, output shifted relative to input, DC-coupled
input
-380
-330
-280
mV
Clamp Restore Current
Force VIN = -0.3V, Channels 1 and 3
-5
-2.5
mA
135
180
VIN_MAX
VOS
ICLAMP
Force VIN = 1V, Channel 2 and 4
1.4
Force VIN = -0.3V, Channels 2 and 4
-200
VSLICE
Sync Detect Threshold
Channels 1 and 3
100
PSRRDC
Power Supply Rejection
VS = +3.0 to +3.6
50
3
V
77
µA
-160
µA
200
mV
dB
FN6268.1
June 11, 2008
ISL59834
Electrical Specifications
SYMBOL
VCP = VS = 3.3V, CF1 = CF2 = 0.1µF, CS1 = CS2 = 0.22µF, CFIL1 = CFIL2 = 0.4µF, CIN1 = CIN2 = CIN3 = CIN4 =
0.1µF, RL1 = RL2 = 150, Typical TA = +27°C. (Continued)
PARAMETER
CONDITIONS
MIN
(Note 2)
TYP
MAX
(Note 2)
UNIT
0
0.8
1.25
dB
-35
dB
AC CHARACTERISTICS
APB
Passband Flatness
f = 5MHz relative to 100kHz
ASB
Stopband Attenuation
f  27MHz relative to 100kHz
-50
dG
Differential Gain
11-step modulated staircase
0.45
%
dP
Differential Phase
11-step modulated staircase
-0.15
°
Signal-to-Noise Ratio
Peak signal (1.4VP-P) to RMS noise, f = 10kHz to
10MHz
60
dB
GDMATCH
DC Group Delay Match
Channel-to-channel group delay matching at
100kHz
0.1
ns
GD
Group Delay Deviation
Deviation from 100kHz to 3.58MHz
8
ns
PSRR
Power Supply Rejection
VIN = 100mVP-P sine wave, f = 100kHz to 5MHz
25
dB
XTALK
Channel-to-Channel Crosstalk
f = 100kHz to 5MHz, inter-channel
-55
dB
VNOISE
Input Voltage Noise
1.44
mVRMS
SNR
LOGIC (ENABLEA, ENABLEB)
VIL
Logic Low Input Voltage
VIH
Logic High Input Voltage
2.0
Logic Input Current
-1
II
0.8
V
V
1
µA
CHARGE PUMP
fCP
Charge Pump Clock Frequency
9.5
MHz
NOTE:
2. Parameters with MIN and/or MAX limits are 100% tested at +27°C, unless otherwise specified. Temperature limits are established by
characterization and are not production tested.
4
FN6268.1
June 11, 2008
ISL59834
Pin Descriptions
NUMBER
NAME
1, 3, 9, 11
GND
2
IN2
4
GNDCPA
5
VCPA
6, 41
VS
7
ENABLEB
8
IN3
Video Input 3. Luma Channel.
10
IN4
Video Input 4. Chroma Channel.
12, 13, 16, 17, 18,
21, 35, 38, 40, 43
NC
No Connect.
14
GNDCPB
15
VCPB
19
CAPB-
Charge-Pump B Flying Capacitor Negative Terminal. Connect a 0.1µF capacitor from CAPB+ to
CAPB-.
20
CAPB+
Charge-Pump B Flying Capacitor Positive Terminal. Connect a 0.1µF capacitor from CAPB+ to CAPB.
22
VEEBOUT
23
VEEBIN
24
OUT4
Video Output 4
25
OUT3
Video Output 3
26
SYNC_INB
27
SYNC_OUTB
28
CLKB
Channel 3 and Channel 4 Charge Pump Clock Output. Can also be driven by external clock. CLKA
must be tied to CLKB.
29
CAPA-
Charge-Pump A Flying Capacitor Negative Terminal. Connect a 0.1µF capacitor from CAPA+ to
CAPA-.
30
CAPA+
Charge-Pump A Flying Capacitor Positive Terminal. Connect a 0.1µF capacitor from CAPB+ to
CAPB-.
31
VEEAOUT
32
VEEAIN
33
OUT2
Video Output 2
34
OUT1
Video Output 1
36
SYNC_INA
37
SYNC_OUTA
39
CLKA
42
ENABLEA
44
IN1
Video Input 1. Luma Channel.
-
EP
Exposed Pad. Connect to VEEAIN or VEEBIN.
5
FUNCTION
Ground
Video Input 2. Chroma Channel.
Charge Pump A Ground
Charge Pump A Power Supply. Bypass with a 0.1µF capacitor to GNDCPA.
Positive Power Supply. Bypass to GND with a 0.1µF capacitor.
Channel 3 and Channel 4 Enable. Connect to VS to enable channels. ENABLEA must be tied to
ENABLEB.
Charge Pump B Ground.
Charge Pump B Power Supply. Bypass with a 0.1µF capacitor to GNDCPB.
Charge Pump Negative Output. Bypass with a 0.22µF capacitor to GCP2.
Negative Supply for Channels 3 and 4. Connect an RC filter between VEEBIN and VEEBOUT. See
Typical Application Diagram. VEEAIN must be tied to VEEBIN.
Sync Input. Sync logic input for Channel 4.
Sync Output. Sync logic output from Channel 3.
Charge Pump Negative Output. Bypass with a 0.22µF capacitor to GNDCPA.
Negative Supply for Channels 1 and 2. Connect an RC filter between VEEAIN and VEEAOUT. See
Typical Application Diagram. VEEAIN must be tied to VEEBIN.
Sync Input. Sync logic input for Channel 2.
Sync Output. Sync logic output from Channel 1.
Channel 1 and Channel 2 Charge Pump Clock Output. Can also be driven by external clock. CLKA
must be tied to CLKB.
Channel 1 and Channel 2 enable. Connect to VS to enable channels. ENABLEA must be tied to
ENABLEB.
FN6268.1
June 11, 2008
ISL59834
Functional Diagram
VS
ENABLEA
ENABLEB
SYNC DETECTOR
SYNC_OUTA
LPF
LEVEL
SHIFT
(-310mV)
IN1
9MHz
OUT1
X2
VEEAIN
+
-593mV
LPF
LEVEL
SHIFT
(-165mV)
IN2
9MHz
X2
OUT2
VEEAIN
KEYED
+
SYNC_OUTB
0V
SYNC_INA
SYNC DETECTOR
LPF
LEVEL
SHIFT
(-310mV)
IN3
9MHz
X2
OUT3
VEEBIN
+
-593mV
LPF
LEVEL
SHIFT
(-165mV)
IN4
9MHz
OUT4
X2
VEEBIN
KEYED
+
VEEAIN
0V
SYNC_INB
VEEBIN
ISL59834
CHARGE
PUMP B
CHARGE
PUMP A
GND
VEEAOUT
6
GNDCPA CAPA+ CAPA- CLKA
VCPA
VEEBOUT
GNDCPB CAPB+ CAPB- CLKB
VCPB
FN6268.1
June 11, 2008
ISL59834
Component (YPbPr) Application Diagram
+3.3V
0.1µF
ENABLEA
Y
CURRENT
DAC
ENABLEB
4.7µF
VS
SYNC_OUTA
SYNC_INA
0.1µF
IN1
SYNC_OUTB
150
SYNC_INB
75
PB
CURRENT
DAC
OUT1
0.1µF
75
IN2
150
75
OUT2
PR
CURRENT
DAC
75
0.1µF
IN4
75
150
MPEG
DECODER
OUT3
ISL59834
75
0.1µF
COMPOSITE
SOURCE
75
IN3
OUT4
75
75
CLKA
CLKB
RFIL1
0.22µF
CFIL1
CS1
VEEAIN
VEEBIN
VEEAOUT
VEEBOUT
10
10
0.47µF
0.47µF
+3.3V
CCP1B
0.1µF
CS2
0.22µF
CFIL2
+3.3V
VCPA
1.0µF
CCP1A
RFIL2
VCPB
0.1µF
GNDCPA
GND
CAPA+
CAPA-
CAPB+ CAPB-
CF1
CF2
0.1µF
0.1µF
GNDCPB
CCP2A
1.0µF
CCP2B
s
7
FN6268.1
June 11, 2008
ISL59834
S-Video Application Diagram
+3.3V
0.1F
ENABLEA
ENABLEB
4.7F
VS
SYNC_OUTA
SYNC_INA
0.1F
IN1
Y1
SYNC_OUTB
75
SYNC_INB
75
OUT1
0.1F
C1
75
IN2
75
75
OUT2
75
0.1F
IN3
Y2
75
75
OUT3
ISL59834
75
0.1F
75
IN4
C2
OUT4
75
75
CLKA
CLKB
RFIL1
0.22F
CFIL1
CS1
VEEAIN
VEEBIN
VEEAOUT
VEEBOUT


F
F
+3.3V
CCP1B
CS2
0.22F
CFIL2
+3.3V
VCPA
F
CCP1A
RFIL2
VCPB
F
F
GNDCPA
8
GND
CAPA+
CAPA-
CAPB+ CAPB-
CF1
CF2
F
F
GNDCPB
CCP2A
F
CCP2B
FN6268.1
June 11, 2008
ISL59834
VCP = VS = 3.3V, CF1 = CF2 = 0.1µF, CS1 = CS2 = 0.22µF, CFIL1 = CFIL2 = 0.4µF, CIN1 = CIN2 =
CIN3 = CIN4 = 0.1µF, RL1 = RL2 = 150.
10
2
0
1
-10
-20
CHANNEL 2, 4
RL = 150
CHANNEL 2, 4
RL = 75
-30
-40
CHANNEL 1, 3
RL = 150
-50
-60
-70
0.1
MAGNITUDE (dB)
MAGNITUDE (dB)
Typical Performance Curves
0
CHANNEL 1, 3
RL = 150
-1
CHANNEL 2, 4
RL = 150
-2
-3
-5
100M
0.1
50
-1.40
CHANNEL 1, 3
LUMA
CHARGE PUMP VOLTAGE (V)
DELAY (ns)
30
20
10
0
-10
CHANNEL 2, 4
CHROMA
-20
-30
-40
0.1
1M
10M
FREQUENCY (Hz)
-1.44
-1.45
-1.46
VCP = 3.3V
VS = 2.7V TO 3.6V
-1.47
-10
MAGNITUDE (dB)
MAGNITUDE (dB)
-1.43
2.8
2.9
VCP = VS 2.7V TO 3.6V
3.0 3.1
3.2
3.3
SUPPLY VOLTAGE (V)
3.4
3.5
3.6
0
ENABLE = LOW
ANY INPUT TO ANY OUTPUT
-30
-40
-50
-60
-70
-30
-40
-50
-60
-70
-90
-80
1M
10M
FREQUENCY (Hz)
100M
FIGURE 5. INPUT-TO-OUTPUT ISOLATION vs FREQUENCY
9
INPUT OF CHANNEL 1/2 TO OUTPUT OF CHANNEL 3/4
-20
-80
-100
0.1
VS = 3.3V
VCP = 2.7 TO 3.6V
-1.42
FIGURE 4. CHARGE PUMP VOLTAGE vs SUPPLY VOLTAGE
0
-20
10M
ALL MEASUREMENTS
AT VEEIN
-1.41
-1.48
2.7
100M
FIGURE 3. GROUP DELAY vs FREQUENCY
-10
1M
FREQUENCY (Hz)
FIGURE 2. GAIN FLATNESS vs FREQUENCY
FIGURE 1. BANDWIDTH vs FREQUENCY
40
CHANNEL 1, 3
RL = 75
-4
CHANNEL 1, 3
RL = 75
1M
10M
FREQUENCY (Hz)
CHANNEL 2, 4
RL = 75
-90
0.1
1M
10M
FREQUENCY (Hz)
100M
FIGURE 6. INTER-CHANNEL CROSSTALK
FN6268.1
June 11, 2008
ISL59834
Typical Performance Curves
VCP = VS = 3.3V, CF1 = CF2 = 0.1µF, CS1 = CS2 = 0.22µF, CFIL1 = CFIL2 = 0.4µF, CIN1 = CIN2 =
CIN3 = CIN4 = 0.1µF, RL1 = RL2 = 150. (Continued)
70
0
-20
-30
-40
-50
-60
1M
10M
FREQUENCY (Hz)
1500
60
58
56
54
3.0
3.1
3.2
3.3
3.4
SUPPLY VOLTAGE (V)
3.5
3.6
30
NO LOAD
INPUT FLOATING
25
1200
IMPEDANCE )
DISABLED SUPPLY CURRENT (nA)
62
FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE
1100
1000
900
800
700
20
15
10
5
600
500
3.0
3.1
3.2
3.3
3.4
SUPPLY VOTLAGE (V)
3.5
0
0.1
3.6
10M
FREQUENCY (Hz)
100M
0.05
0
WAVEFORM = MODULATED RAMP
0 IRE TO 100 IRE
0.03
-10
0.01
VAC = 100mVP-P
VS = +3.3V + VAC
-0.01
DG (%)
-20
1M
FIGURE 10. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 9. DISABLED SUPPLY CURRENT vs SUPPLY
VOLTAGE
MAGNITUDE (dB)
64
50
100M
FIGURE 7. LUMA-TO-CHROMA CROSSTALK
1300
66
52
-70
0.1
1400
NO LOAD
INPUT FLOATING
68
SUPPLY CURRENT (mA)
MAGNITUDE (dB)
INPUT OF CHANNEL 1, 3 TO OUTPUT OF
-10 CHANNEL 2, 4 AND VICE-VERSA
-30
-40
-0.05
-0.07
-0.09
-0.11
-50
-60
0.001
-0.03
-0.13
0.01
0.1
1M
FREQUENCY (Hz)
FIGURE 11. POWER SUPPLY REJECTION RATIO vs
FREQUENCY
10
10M
-0.15
0
1
2
3
4
5
6
7
8
9
10
11
STEP
FIGURE 12. DIFFERENTIAL GAIN
FN6268.1
June 11, 2008
ISL59834
Typical Performance Curves
VCP = VS = 3.3V, CF1 = CF2 = 0.1µF, CS1 = CS2 = 0.22µF, CFIL1 = CFIL2 = 0.4µF, CIN1 = CIN2 =
CIN3 = CIN4 = 0.1µF, RL1 = RL2 = 150. (Continued)
0.6
TIME SCALE = 10ns/DIV
DISABLE = 1V/DIV
OUTPUT = 1V/DIV
WAVEFORM = MODULATED RAMP
0.5 0 IRE to 100 IRE
0.4
DP (°)
0.3
DISABLE SIGNAL
0.2
0.1
OUTPUT SIGNAL
0
-0.1
-0.2
0
1
2
3
4
5
6
STEP
7
8
9
10
11
FIGURE 14. DISABLE TIME
FIGURE 13. DIFFERENTIAL PHASE
TIME SCALE = 5µs/DIV
ENABLE = 1V/DIV
OUTPUT = 1V/DIV
ENABLE SIGNAL
TIME SCALE = 500ns/DIV
IN = 200mV/DIV
OUT = 500mV/DIV
INPUT
TIME = 35µs
OUTPUT
OUTPUT SIGNAL
FIGURE 15. ENABLE TIME
TIMEBASE = 100ns/DIV
IN = 200mV/DIV
OUT = 500mV/DIV
FIGURE 16. 12.5T RESPONSE (CHANNELS 1 and 3)
TIME SCALE = 10µs/DIV
IN = 500mV/DIV
OUT = 1V/DIV
INPUT
INPUT
OUTPUT
OUTPUT
FIGURE 17. 2T RESPONSE (CHANNELS 1 and 3)
11
FIGURE 18. NTSC COLORBAR (CHANNELS 1 and 3)
FN6268.1
June 11, 2008
ISL59834
Typical Performance Curves
VCP = VS = 3.3V, CF1 = CF2 = 0.1µF, CS1 = CS2 = 0.22µF, CFIL1 = CFIL2 = 0.4µF, CIN1 = CIN2 =
CIN3 = CIN4 = 0.1µF, RL1 = RL2 = 150. (Continued)
TIME SCALE = 10µs/DIV
LUMA OUT = 500mV/DIV
CHROMA OUT = 500mV/DIV
LUMA OUTPUT
CHANNELS 1, 3
VIDEO SIGNAL (CHANNEL 1 or 3)
TIME SCALE = 5µs/DIV
OUT = 500mV/DIV
SYNC_OUT = 500mV/DIV
CHROMA OUTPUT
CHANNELS 2, 4
SYNC_OUT
FIGURE 19. S-VIDEO SCOPE SHOT
INPUT = NTSC VIDEO + 2Hz SQUARE WAVE
(BEFORE COUPLING CAPACITOR)
TIMEBASE = 1ms/DIV
INPUT: 500mV/DIV
OUTPUT: 500mV/DIV
CHANNEL 1 OR
CHANNEL 3 OUTPUT
FIGURE 21. LUMA CLAMP RESPONSE TO POSITIVE
TRANSIENT (CHANNEL 1 AND 3)
INPUT = NTSC S-VIDEO (CHROMA) + 2Hz SQUARE WAVE
(BEFORE COUPLING CAPACITOR)
FIGURE 20. SYNC_OUT SIGNAL
INPUT = NTSC VIDEO + 2Hz SQUARE WAVE
(BEFORE COUPLING CAPACITOR)
CHANNEL 1 OR
CHANNEL 3 OUTPUT
TIMEBASE = 200µs/DIV
INPUT: 500mV/DIV
OUTPUT: 500mV/DIV
FIGURE 22. LUMA CLAMP RESPONSE TO NEGATIVE
TRANSIENT (CHANNEL 1 AND 3)
INPUT = NTSC S-VIDEO (CHROMA) + 2Hz SQUARE WAVE
(BEFORE COUPLING CAPACITOR)
TIMEBASE = 2ms/DIV
INPUT: 500mV/DIV
OUTPUT: 500mV/DIV
TIMEBASE = 2ms/DIV
INPUT: 500mV/DIV
OUTPUT: 500mV/DIV
CHANNEL 2 OR CHANNEL 4 OUTPUT
CHANNEL 2 OR CHANNEL 4 OUTPUT
FIGURE 23. CHROMA CLAMP RESPONSE TO POSITIVE
TRANSIENT (CHANNEL 2 AND 4)
12
FIGURE 24. CHROMA CLAMP RESPONSE TO NEGATIVE
TRANSIENT (CHANNEL 2 AND 4)
FN6268.1
June 11, 2008
ISL59834
Typical Performance Curves
VCP = VS = 3.3V, CF1 = CF2 = 0.1µF, CS1 = CS2 = 0.22µF, CFIL1 = CFIL2 = 0.4µF, CIN1 = CIN2 =
CIN3 = CIN4 = 0.1µF, RL1 = RL2 = 150. (Continued)
100
TIME SCALE = 50ns/DIV
VERTICAL SCALE = 20mV/DIV
RMS NOISE = 2.87mV
OUTPUT REFERRED
10
µV/Hz
CHARGE PUMP NOISE,
CONTRIBUTES ONLY A SMALL
PERCENTAGE OF THE
OVERALL NOISE
1
0.1
0M
1M
2M
3M
4M 5M 6M
FREQUENCY (Hz)
7M
8M
9M
10M
FIGURE 26. CHARGE PUMP FEEDTHROUGH AT AMPLIFIER
OUTPUT
FIGURE 25. NOISE SPECTRUM
4.5
0
POWER DISSIPATION (W)
THD (dBc)
VS = VCP = +3.3V
-10 RL = 150
VOUT = 0 TO 2VP, SINE WAVE
-20
-30
-40
fIN = 500kHz
-50
fIN = 5MHz
-60
-70
0.5
0.8
1.1
1.4
1.7
2.0
4.0
3.5
3.0
2.5
44 LD QFN PACKAGE
7mmx7mm
JA = +32°C/W
2.0
1.5
1.0
0.5
0
OUTPUT VOLTAGE (V)
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
AMBIENT TEMPERATURE (°C)
FIGURE 28. PACKAGE POWER DISSIPATION
FIGURE 27. THD (dBc) vs OUTPUT VOLTAGE (VP-P)
Description of Operation and Application Information
Theory of Operation
Output Amplifier
The ISL59834 is a single supply video driver with a
reconstruction filter and an on-board charge pump. It is
designed to drive SDTV displays with component (YPbPr),
S-video (Y-C), or composite video (CV) signals. The input
signals can be AC or DC-coupled. When AC-coupled, a sync
tip clamp sets the blank level to ground at the output of
Channel 1 and Channel 3. Keyed clamps force the average
levels of Channel 2 and Channel 4 to ground. The keyed
clamps force the outputs to ground when SYNC_INA or
SYNC_INB are driven to the logic high state. The ISL59834
outputs are capable of driving two AC or DC-coupled
standard video loads and have a 4th order Butterworth
reconstruction filter with nominal -3dB frequency set to
9MHz, providing 40dB of attenuation at 27MHz. The
ISL59834 is designed to operate with a single supply voltage
range ranging from 3.0V to 3.6V. This eliminates the need for
a split supply with the incorporation of two charge pumps
capable of generating a bottom rail as much as 1.5V below
ground; providing a 4.8V range on a single 3.3V supply. This
performance is ideal for NTSC video with negative-going
sync pulses.
The ISL59834 output amplifiers provide a gain of +6dB. The
output amplifiers are able to drive a 2.8VP-P video signal into
a 150 or 75load to ground.
13
The outputs are highly-stable, low distortion, low power, high
frequency amplifiers capable of driving moderate (~10pF)
capacitive loads.
Input/Output Range
The ISL59834 has a dynamic input range of 0 to 1.4VP-P
This allows the device to handle high amplitude video signal
inputs. As the input signal moves outside the specified
range, the output signal will exhibit increasingly higher levels
of harmonic distortion.
Charge Pump
The ISL59834 contains two charge pumps; charge pump A
supplies Channel 1 and 2, while charge pump B supplies
Channel 3 and 4. The ISL59834 charge pumps provide a
bottom rail up to 1.5V below ground while operating on a
3.0V to 3.6V power supply. The charge pumps are internally
regulated and are driven by internal 9.5MHz clocks. The
FN6268.1
June 11, 2008
ISL59834
clock pins for both charge pumps (CLKA and CLKB) must be
shorted together.
AC-Coupled Inputs
To reduce the noise on the power supply generated by the
charge pump, connect a lowpass RC-network between
VEEOUT and VEEIN. See the “Typical Application Circuits”
for further information.
The ISL59834 features a sync tip clamp that forces the black
level of the output video signal to ground. This ensures that
the sync-tip voltage level will be approximately -300mV at
the back-termination resistor of a standard video load. The
clamp is activated whenever the input voltage falls below 0V.
The correction voltage required to do this is stored across
the input AC-coupling capacitor. Refer to Typical Application
Circuit for a detailed diagram.
VEEOUT Pins
VEEAOUT and VEEBOUT are the output pins for the charge
pumps. Keep in mind that these outputs are fully regulated
supplies that must be properly bypassed. Bypass these pins
with a 0.47µF ceramic capacitor placed as close to the pin
and connected to the ground plane of the board.
VEEIN Pins
VEEAIN and VEEBIN are the subtrate connections for the
ISL59834, these two pins must be shorted together. To
reduce the noise on the power supply generated by the
charge pump, connect a lowpass RC-network between
VEEOUT and VEEIN. See the “Typical Application Circuits”
for further information.
Video Performance
DIFFERENTIAL GAIN/PHASE
For good video performance, an amplifier is required to
maintain the same output impedance and the same
frequency and phase response as DC levels are changed at
the output. Special circuitry has been incorporated into the
ISL59834 to reduce the output impedance variation with the
current output. This results in outstanding differential gain
and differential phase specifications of 0.45% and 0.15°,
while driving 150 at a gain of +2V/V.
SYNC TIP CLAMP (CHANNEL 1 AND 3)
KEYED CLAMP (CHANNEL 2 AND 4)
Channel 2 and Channel 4 have a keyed clamp, which forces
the output to ground when SYNC_INA (Channel 2) or
SYNC_INB (Channel 4) are driven to the logic high state.
The SYNC_IN pins may be connected to either SYNC_OUT
pins or they may be driven by external sources.
SYNC DETECTOR AND CLAMP TIMING
Channel 1 and Channel 3 also have sync detectors whose
outputs are available at SYNC_OUTA and SYNC_OUTB
pins respectively.
The slice level for the sync detectors is between 100mV to
200mV. This means that if the signal level is below 100mV at
Channel 1 or 3, then SYNC_OUTA or SYNC_OUTB are
high. If the signal level is above 200mV, then SYNC_OUTA
or SYNC_OUTB are low. Figure 29 shows the operation of
the sync detector.
NTSC LUMINANCE
CHANNEL 1 OR 3
INPUT
+1.00V
NTSC
The ISL59834, generating a negative rail internally, is ideally
suited for NTSC video with its accompanying negative-going
sync signals.
+300mV
100mV < VSLICE < 200mV
+0mV
S-VIDEO
For a typical S-video application with two S-video signals,
connect the luma signals to Channel 1 and 3, and connect
the chrominance signals to Channel 2 and 4. For clamp
timing, connect SYNC_OUTA to SYNC_INA and
SYNC_OUTB to SYNC_INB. See the “S-Video Typical
Application Circuit” on page 8.
YPbPr
For a typical component video application, connect Y to
Channel 1, Pb to Channel 2 and Pr to Channel 4. Channel 3
can be optionally used a composite signal. For the clamp
timing, connect SYNC_OUTA to both SYNC_INA and
SYNC_INB and leave SYNC_OUTB floating. See the
“YPbPr Typical Application Circuit” on page 7.
14
SYNC_OUTA OR
SYNC_OUTB
+3.3V
+0mV
FIGURE 29. SYNC DETECTOR SLICE LEVEL
DC-Coupled Inputs (Channel 1 and 3)
When DC-coupling the inputs, ensure that the lowest signal
level is greater than +50mV to prevent the clamp from
turning on and distorting the output. When DC-coupled, the
ISL59834 shifts the signal by -620mV.
Amplifier Disable
The ISL59834 can be disabled and its output placed in a
high impedance state. ENABLEA shuts off Channel 1 and 2
while ENABLEB shuts off Channel 3 and 4. Both ENABLE
pins must be shorted together. The turn-off time is around
10ns and the turn-on time is around 35µs. The turn-on time
FN6268.1
June 11, 2008
ISL59834
is longer because extra time is needed for the charge pump
to settle before the amplifiers are enabled. When disabled,
the device supply current is reduced to 5µA. Power-down is
controlled by standard TTL or CMOS signal levels at the
ENABLE pins. The applied logic signal is relative to the GND
pin. Applying a signal that is less than 0.8V above GND will
disable the device. The device will be enabled when the
ENABLE signals are 2V above GND.
Output Drive Capability
The maximum output current for the ISL59834 is ±50mA.
Maximum reliability is maintained if the output current never
exceeds ±50mA, after which the electro-migration limit of the
process will be exceeded and the part will be damaged. This
limit is set by the design of the internal metal
interconnections.
Driving Capacitive Loads and Cables
The ISL59834 (internally-compensated to drive 75 cables)
will drive 10pF loads in parallel with 150 or 75 with less
than 1.3dB of peaking.
Power Dissipation
With the high output drive capability of the ISL59834, it is
possible to exceed the +150°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for an application to determine if load conditions
or package types need to be modified to assure operation of
the amplifier in a safe operating area.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
T JMAX – T AMAX
PD MAX = -------------------------------------------- JA
(EQ. 1)
Where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
JA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
for sourcing:
V OUT i
PDMAX = V S  I SMAX +  V S – V OUT i   --------------------R
i
(EQ. 2)
LOAD
Where:
VS = Supply voltage
ISMAX = Maximum quiescent supply current
VOUT = Maximum output voltage of the application
RLOAD = Load resistance tied to ground
ILOAD = Load current
i = Number of output channels
By setting Equation 1 equal to Equation 2 and 3, we can
solve for the output current and RLOAD values needed to
avoid exceeding the maximum junction temperature.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Strip
line design techniques are recommended for the input and
output signal traces to help control the characteristic
impedance. Furthermore, the characteristic impedance of
the traces should be 75. Trace lengths should be as short
as possible between the output pin and the series 75
resistor. The power supply pin must be well bypassed to
reduce the risk of oscillation. For normal single supply
operation, a single 4.7µF tantalum capacitor in parallel with a
0.1µF ceramic capacitor from VS and VCP to GND will
suffice.
The AC performance of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• Use low inductance components, such as chip resistors
and chip capacitors whenever possible.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
sharp corners; use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces longer than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. To maintain frequency performance
with longer traces, use striplines.
• Match channel-to-channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
• Route all signal I/O lines over continuous ground planes
(i.e. no split planes or PCB gaps under these lines).
• Place termination resistors in their optimum location as
close to the device as possible.
for sinking:
PD MAX = V S  I SMAX +  V OUT i – V S   I LOAD i
15
(EQ. 3)
FN6268.1
June 11, 2008
ISL59834
• Use good quality connectors and cables, matching cable
types and keeping cable lengths to a minimum when
testing.
• Place flying and output capacitors as close to the device
as possible for the charge pump.
Decouple well, using a minimum of 2 power supply
decoupling capacitors, placed as close to the device as
possible. Avoid vias between the capacitor and the device
because vias add unwanted inductance. Larger capacitors
may be farther away. When vias are required in a layout,
they should be routed as far away from the device as
possible.
16
FN6268.1
June 11, 2008
ISL59834
Quad Flat No-Lead Plastic Package (QFN)
L44.7x7A
A
B
44 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220)
N
(N-1)
(N-2)
D
MILLIMETERS
SYMBOL
1
2
3
PIN #1
I.D. MARK
E
(2X)
0.075 C
TOP VIEW
(2X)
(N/2)
0.075 C
MIN
SEATING
PLANE
0.08 C
N LEADS AND
EXPOSED PAD
NOTES
A
0.80
0.85
0.90
-
0.00
0.02
0.05
-
b
0.20
0.25
0.30
-
c
0.203 REF
-
D
7.00 BASIC
-
D2
5.10 REF
8
E
7.00 BASIC
-
E2
5.10 REF
8
L
0.10 C
e
MAX
A1
e
C
NOMINAL
0.50 BASIC
0.50
0.55
0.60
-
N
44 REF
4
ND
11 REF
6
NE
11 REF
5
Rev. 1 1/07
SEE DETAIL “X”
NOTES:
SIDE VIEW
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
0.01 M C A B
4. N is the total number of terminals on the device.
(N-2)
(N-1)
N
b
L
N LEADS
PIN #1 I.D.
3
1
2
3
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
(E2)
7. Inward end of terminal may be square or circular in shape with
radius (b/2) as shown.
(N/2)
NE 5
(D2)
8. If two values are listed, multiple exposed pad options are
available. Refer to device-specific datasheet.
9. One of 10 packages in MDP0046
7
BOTTOM VIEW
C
A
2
(c)
A1
(L)
N LEADS
DETAIL “X”
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
FN6268.1
June 11, 2008
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