DATASHEET

HA456
®
Data Sheet
September 26, 2008
120MHz, Low Power, 8x8 Video
Crosspoint Switch
Features
• Fully Buffered Inputs and Outputs (AV = +1)
The HA456 is the first 8x8 video crosspoint switch suitable
for high performance video systems. Its high level of
integration significantly reduces component count, board
space, and cost. The crosspoint switch contains a digitally
controlled matrix of 64 fully buffered switches that connect 8
video input signals to any, or all, matrix outputs. Each matrix
output connects to an internal, high-speed (200V/µs), unity
gain buffer capable of driving 400Ω and 5pF to ±2V.
For applications requiring gain or increased drive capability,
the HA456 outputs can be connected directly to two
HFA1412 quad, gain of two video buffers, which are capable
of driving 75Ω loads.
This crosspoint’s true high impedance three-state output
capability, makes it feasible to parallel multiple HA456s and
form larger switch matrices.
HA456CMZ HA456CMZ
(Note)
• Serial or Parallel Digital Interface
• Expandable for Larger Switch Matrices
• Wide Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 120MHz
• High Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 200V/µs
• Differential Gain and Phase . . . . . . . . . . . . . .0.05%, 0.05°
• Low Crosstalk at 10MHz . . . . . . . . . . . . . . . . . . . . . -55dB
• Pb-Free Available (RoHS Compliant)
Applications
• Professional Video Switching and Routing
Pinout
PACKAGE
PKG.
DWG. #
0 to +70 44 Ld PLCC
N44.65
0 to +70 44 Ld PLCC
(Pb-free)
N44.65
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
HA456
(44 LD PLCC)
TOP VIEW
6
A0
IN1
NC
IN2
DGND
NC
IN3
DGND
IN4
EDGE/LEVEL
IN5
5 4
3
2 1 44 43 42 41 40
7
8
39
38
9
37
10
11
36
12
35
34
13
33
14
15
32
31
16
30
17
29
OUT2
VOUT3
AGND
OUT4
NC
AGND
OUT5
AGND
OUT6
V+
V+
IN6
18 19 20 21 22 23 24 25 26 27 28
1
SER/PAR
IN7
VNC
WR
LATCH
CE
CE
OUT7
HA456CM
TEMP.
RANGE
(°C)
• Switches Standard and High Resolution Video Signals
IN0
A1
A2
D0/SER IN
D1/SER OUT
NC
V+
OUT0
D2
OUT1
D3
HA456CM
PART
MARKING
• Routes Any Input Channel to Any Output Channel
• Security and Video Editing Systems
Ordering Information
PART
NUMBER
FN4153.7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2006, 2007, 2008. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
HA456
HA456 Functional Block Diagram
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
OUTPUT
BUFFERS
(AV = 1)
OUT0
EN0
HA456
8x8
SWITCH
MATRIX
OUT7
EN7
EN0:7
SLAVE REGISTER
SER/PAR
MASTER REGISTER
D0/SER IN
A0
2
A1
A2
D2
LATCH
EDGE/LEVEL
WR
CE
CE
D1/SER OUT
D3
FN4153.7
September 26, 2008
HA456
Pin Descriptions
NAME
NC
FUNCTION
No connect. Not internally connected.
D1/SER OUT
Parallel Data Bit input D1 for Parallel Programming Mode. Serial Data Output (MSB of shift register) for cascading multiple
HA456s in serial programming mode. Simply connect Serial Data Out of one HA456 to Serial Data In of another HA456 to daisy
chain multiple devices.
D0/SER IN
Parallel Data Bit Input D0 for Parallel Programming Mode. Serial Data Input (input to shift register) for serial programming mode.
A2, A1, A0
Output Channel Address Bits. These inputs select the output being programmed in parallel programming mode.
IN0-IN7
Analog Video Input Lines.
DGND
Digital Ground. Connect both DGND pins to AGND.
EDGE/LEVEL
V+
SER/PAR
VWR
LATCH
A user strapped input that defines whether synchronous channel switching is edge or level controlled. With this pin is strapped
high, the slave register loads from the master register (thus changing the switch matrix state) on the rising edge of the LATCH
signal. If it is strapped low (level mode), the slave register is transparent while LATCH is low, passing data directly from the
master register to the switch state decoders. Strapping EDGE/LEVEL and LATCH low causes the channel switch to execute on
the WR rising edge (not recommended for serial mode operation).
Positive Supply Voltage. Connect all V+ pins together and decouple each pin to AGND (see Figure 2).
A user strapped input that defines whether the serial (SER/PAR = 1) or parallel (SER/PAR = 0) digital programming interface is
being utilized.
Negative Supply Voltage. Connect both V- pins together and decouple each pin to AGND (see Figure 2).
WRITE Input. In serial mode, data shifts into the shift register (Master Register) LSB from SER IN on the WR rising edge. In
parallel mode, the Master Register loads with D3:0 (if D3:0 = 0000 through 1000), or the appropriate action is taken
(if D3:0 =1011 through 1111), on the WR rising edge (see Table 1).
Synchronous Channel Switch Control Input. If EDGE/LEVEL = 1, data is loaded from the Master Register to the Slave Register
on the rising edge of LATCH. If EDGE/LEVEL = 0, data is loaded from the Master to the Slave Register while LATCH = 0. In
parallel mode, commands 1011 through 1110 execute asynchronously, on the WR rising edge, regardless of the state of LATCH
or EDGE/LEVEL. Parallel mode command 1111 executes a software “Latch” (see Table 1).
CE
Chip Enable. When CE = 0 and CE = 1, the WR line is enabled.
CE
Chip Enable. When CE = 0 and CE = 1, the WR line is enabled.
OUT7-OUT0
AGND
Analog Video Outputs.
Analog Ground.
D3
Parallel Data Bit Input D3 when SER/PAR = 0. D3 is unused with serial programming.
D2
Parallel Data Bit Input D2 when SER/PAR = 0. D2 is unused with serial programming.
3
FN4153.7
September 26, 2008
HA456
Absolute Maximum Ratings
Thermal Information
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
Positive Supply Voltage (V+) Referred to AGND . . . . . . . . . . . . . 6V
Negative Supply Voltage (V-) Referred to AGND. . . . . . . . . . . . -6V
DGND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND ±1V
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VSUPPLY
Digital Input Voltage . . . . . . . . . . . . . . (V+ + 0.3V) to (DGND - 0.3V)
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . . 1.5kV
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . ±4.5V to ±5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
VSUPPLY = ±5V, AGND = DGND = 0V, RL = 400Ω (Note 2), Unless Otherwise Specified.
Electrical Specifications
TEST
LEVEL
(Note 3)
TEMP
(°C)
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
A
25
0.990
0.996
1.00
V/V
A
Full
0.988
0.995
1.00
A
25
-
0.001
0.004
A
Full
-
0.001
0.005
All Outputs Enabled, RL = Open,
VIN = 0V,
Total for All V+ (3) or V- (2) Pins
A
25
-
68
80
A
Full
-
71
83
All Outputs Disabled, RL = Open,
Total for All V+ (3) or V- (2) Pins
A
25
-
47
65
A
Full
-
47
67
A
Full
±2
±2.5
-
V
PARAMETER
TEST CONDITIONS
Voltage Gain
VIN = -1.5V to +1.5V, Worst Case
Switch Configuration
Channel-to-Channel Gain Mismatch
Supply Current
Disabled Supply Current
Input Voltage Range
V/V
mA
mA
Analog Input Current
VIN = 0V
A
Full
-
1.6
12
µA
Input Noise (RS = 75Ω)
DC to 40MHz
B
25
-
0.15
-
mVRMS
≥10kHz
B
25
-
22
-
nV/√Hz
DC
C
25
-
4
-
MΩ
B
25
-
3.2
-
pF
A
25
-18
-6.5
5
mV
A
Full
-20
-7.5
6
A
25
-
2
11
A
Full
-
4
13
Analog Input Resistance
Analog Input Capacitance (Input Connected to
One Output or All Outputs, Note 6)
Output Offset Voltage
VIN = 0V, Worst Case Switch
Configuration
Channel-to-Channel Offset Voltage
Mismatch
Offset Voltage Drift
VIN = ±2.5V
Output Voltage Swing
mV
B
Full
-
20
-
µV/°C
A
25
±2.2
±2.48
-
V
A
Full
±2.1
±2.47
-
V
Output Resistance
Enabled, DC
B
25
-
0.25
-
Ω
Output Leakage Current
(Including D1/SER OUT)
All Outputs Disabled,
VOUT = 2.5V
A
25
-
0.2
5
µA
A
Full
-
1
10
µA
Output Resistance
Output Disabled
A
25
0.6
15
-
MΩ
4
FN4153.7
September 26, 2008
HA456
VSUPPLY = ±5V, AGND = DGND = 0V, RL = 400Ω (Note 2), Unless Otherwise Specified. (Continued)
Electrical Specifications
PARAMETER
TEST CONDITIONS
TEST
LEVEL
(Note 3)
TEMP
(°C)
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
B
25
-
3.5
-
pF
Output Capacitance
(Output Disabled)
Power Supply Rejection Ratio
DC, VS = ±4.5V to ±5.5V, VIN = 0V
A
Full
45
53
-
dB
Digital Input Current (Note 5)
VIN = 0V or 5V
A
Full
-
-
1
µA
Digital Input Low Voltage
A
Full
-
-
0.8
V
Digital Input High Voltage
A
25
2.0
-
-
V
A
Full
2.2
-
-
V
SER OUT Logic Low Voltage
Serial Mode, IOL = 1.6mA
A
Full
-
-
0.4
V
SER OUT Logic High Voltage
Serial Mode, IOH = -0.4mA
A
Full
3.0
-
-
V
CL = 5pF, VIN = 200mVP-P
B
25
-
120
-
MHz
CL = 5pF, VIN = 1VP-P
B
25
-
70
-
MHz
CL = 5pF, VIN = 2VP-P
B
25
-
50
-
MHz
VOUT = 4VP-P
B
25
-
200
-
V/µs
AC CHARACTERISTICS (Note 4)
-3dB Bandwidth (Note 6)
Slew Rate (Note 6)
All Hostile Crosstalk (Note 6)
10MHz, VIN = 1VP-P, RL =1kΩ
B
25
-
-55
-
dB
All Hostile Off-Isolation (Note 6)
10MHz, VIN = 1VP-P
B
25
-
70
-
dB
Differential Phase
NTSC or PAL, RL = 1kΩ
B
25
-
0.05
-
°
NTSC or PAL, RL ≥ 10kΩ
B
25
-
0.05
-
°
NTSC or PAL, RL = 1kΩ
B
25
-
0.05
-
%
NTSC or PAL, RL ≥10kΩ
B
25
-
0.02
-
%
Write Pulse Width High (tWH)
A
Full
20
-
-
ns
Write Pulse Width Low (tWL)
A
Full
20
-
-
ns
Chip-Enable Setup Time to Write (tCS)
A
Full
5
-
-
ns
Chip-Enable Hold Time From Write (tCH)
A
Full
5
-
-
ns
Parallel Mode
A
Full
20
-
-
ns
Serial Mode
A
Full
20
-
-
ns
Data and Address Hold Time from Write (tDH)
A
Full
25
-
-
ns
Latch Pulse Width (tL)
A
Full
40
-
-
ns
Latch Delay From Write (tD)
A
Full
40
-
-
ns
Differential Gain
TIMING CHARACTERISTICS (See Figure 3 for More Information)
Data and Address Setup Time to Write (tDS)
LATCH Edge to Output Disabled (tOFF)
Serial Mode
B
Full
-
30
-
ns
LATCH Edge to Output Enabled (tON)
Serial Mode
B
Full
-
185
-
ns
Output Break-Before-Make Delay (tON - tOFF)
Serial Mode
B
Full
-
155
-
ns
NOTES:
2. For the lowest crosstalk, and the best composite video performance, use RL ≥ 1kΩ.
3. Test Level: A. Production Tested; B. Typical or Established Limit Based on Characterization; C. Design Typical for Information Only.
4. See AC Test Circuits (Figure 6 through Figure 9).
5. Excludes D1/SER OUT which is a bidirectional terminal and thus falls under the higher Output Leakage limit.
6. See “Typical Performance Curves” beginning on page 11 for more information.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
5
FN4153.7
September 26, 2008
HA456
Application Information
HA456 Architecture
The HA456 video crosspoint switch consists of 64 switches in
an 8x8 grid (see Figure 1). Each input is fully buffered and
presents a constant input capacitance whether the input
connects to one output or all 8 outputs. This yields consistent
input termination impedances regardless of the switch
configuration. The 8 matrix outputs are followed by 8 unity gain,
wideband, tristatable buffers optimized for driving 400Ω and
5pF loads. The output disable function is useful for multiplexing
two or more HA456s to create a larger input matrix (e.g., two
multiplexed HA456s yield a 16x8 crosspoint).
The HA456 outputs can be disabled individually or
collectively under software control. When disabled, an output
enters a high-impedance state. In multichip parallel
applications, the disable function prevents inactive outputs
from loading lines driven by other devices. Disabling an
unused output also reduces power consumption.
The HA456 outputs connect easily to two HFA1412 quad,
gain-of-two buffers when 75Ω loads must be driven.
Power-On RESET
The HA456 has an internal power-on reset (POR) circuit that
disables all outputs at power-up, and presets the switch
matrix so that all outputs connect to IN0. In parallel mode,
the desired switch state may be programmed before the
outputs are enabled. In serial mode, all outputs are
connected to GND each time they are enabled, so switch
state programming must occur after the output is enabled.
Digital Interface
The desired switch state can be loaded using a 7-bit parallel
interface mode or 32-bit serial interface mode (see Tables 1
through 3). All actions associated with the WR line occur on
its rising edge. The same is true for the LATCH line if
EDGE/LEVEL = 1. Otherwise, the Slave Register updates
asynchronously (while LATCH=0, if EDGE/LEVEL = 0). WR
is logically AND’ed with CE and CE to allow active high or
active low chip enable.
7-Bit Parallel Mode
In the parallel programming mode (SER/PAR = 0), the 7 control
bits (A2:0 and D3:0) typically specify an output channel (A2:0)
and the corresponding action to be taken (D3:0). Command
codes are available to enable or disable all outputs, or
individual outputs, as shown in Table 1. Each output has 4-bit
Master and Slave Registers associated with it that hold the
output’s currently selected input address (defined by D3:0). The
input address (if applicable) is loaded into the Master Register
on the rising edge of WR. If the HA456 is in level mode, and if
LATCH = 0 (asynchronous switching), then the input address
flows through the transparent Slave Register and the output
immediately switches to the new input. For synchronous
switching on the rising edge of LATCH, strap the HA456 for
edge mode, program all the desired switch connections, and
then drive an inverted pulse on the LATCH input. Note:
Operations defined by commands 1011 - 1111 occur
asynchronously on the WR rising edge, without regard for the
state of LATCH or EDGE/LEVEL.
32-Bit Serial Mode
In the serial programming mode, all master registers are loaded
with data, making it unnecessary to specify an output address
(A2:0). The input data format is D3-D0, starting with OUT0 and
ending with OUT7 for 32 total bits (i.e., first bit shifted in is D3
for OUT0, and 32nd bit shifted in is D0 for OUT7). Only codes
0000 through 1010 are valid serial mode commands. Code
1010 disables an individual output, while code 1001 enables it.
After data is shifted into the 32-bit Master Register, it transfers
to the Slave Register on the rising edge of the LATCH line
(Edge mode), or when LATCH = 0 (Level mode, see Figure 5).
HA456
AV = +2
WR
LATCH
INPUT
SELECT AND
COMMAND
CODES OR
SERIAL I/O
VIDEO
OUT
75Ω
INPUT
BUFFERS
VIDEO
INPUTS
OUTPUT
SELECT
75Ω
8X8
SWITCH
MATRIX
HFA1412 OR
HFA1405
A2
A1
A0
D3
D2
D1/SER OUT
D0/SER IN
AV = +2
FIGURE 1. TYPICAL CABLE DRIVING APPLICATION
6
FN4153.7
September 26, 2008
HA456
TABLE 1. PARALLEL INTERFACE COMMANDS
A2:0
D3:0
Selects
Output
Being
Programmed
Address
Inputs are
Irrelevant for
These
Functions
ACTION
0000 to 0111
Connect the input defined by D3:0 to the output selected by A2:0. Doesn’t enable a disabled output.
1000
Connect the output selected by A2:0 to GND. Doesn’t enable a disabled output.
1011
Asynchronously disable the single output selected by A2:0, and leave the Master Register unchanged.
1100
Asynchronously enable the single output selected by A2:0, and leave the Master Register unchanged.
1101
Asynchronously disable all outputs, and leave the Master Register unchanged.
1110
Asynchronously enable all outputs, and leave the Master Register unchanged.
1111
Send a Software “Latch” pulse to the Slave Register to load it from the Master Register, iff, the LATCH input = 1.
If the LATCH input = 0, then this command is a NOP. The Master Register is unchanged by this command.
1001 or 1010
Do not use these codes in the parallel programming mode. These codes are for serial programming only.
TABLE 2. SERIAL INTERFACE COMMANDS
D3:0
0000 to 0111
ACTION
Connect the output to the input channel defined by D3:0. Doesn’t enable a disabled output.
1000
Connect the output to GND. Doesn’t enable a disabled output.
1001
Enable the output and connect it to GND. The default power-up state is all outputs disabled, so use this code to enable
outputs after power is applied, but before programming the switch configuration.
1010
Disable the output. The output is no longer associated with any input channel; the desired input must be redefined after
re enabling the output.
1011 to 1111
Do not use these codes in the serial programming mode.
TABLE 3. DEFINITION OF DATA AND ADDRESS BIT FUNCTIONS
SER/PAR
D3
D2
D1
D0
A2:0
COMMENT
H
X
X
Serial Data
Output
Serial Data Input
X
32-Bit Serial Mode
L
H
Parallel Data
Input
Parallel Data
Input
Parallel Data
Input
Output
Address
Parallel Mode; D2:0 define the
command to be executed
L
L
Parallel Data
Input
Parallel Data
Input
Parallel Data
Input
Output
Address
Parallel Mode; D2:0 define the Input
Channel
Figure 2 shows a typical application of the HA456 with
HFA1412 quad, gain-of-two buffers at the outputs to drive
75Ω loads. This application shows the HA456 digital-switch
control interface set up in the 7-bit parallel mode. The HA456
uses 7 data lines and 3 control lines (WR, CE and LATCH).
The input/output information is presented to the chip at A2:0
and D3:0 by a parallel printer port. The data is stored in the
Master Registers on the rising edge of WR. When the
LATCH line goes high, the switch configuration loads into the
Slave Registers, and all 8 outputs reconfigure at the same
time. Each 7-bit word updates only one output at a time.
7
If several outputs are to be updated, the data is individually
loaded into the Master Registers. Then, a single LATCH
pulse can reconfigure all channels simultaneously.
An IBM compatible PC loads the programming data into the
HA456 via its parallel port (LPT1) using a simple BASIC
program.
FN4153.7
September 26, 2008
HA456
HFA1412
(AV = +2)
HA456
6
8
10
13
15
17
19
21
VIDEO
INPUTS
OUT0
IN0
IN1
IN2
IN3
IN4
IN5
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
CE
IN6
IN7
EDGE/LEVEL
1
2
3
4
5
19
24
V+
3
2
42
40
7
5
4
AGND
D0/SER IN
D1/SER OUT DGND
D2
VD3
A0
A1
SER/PAR
A2
CE
25
LATCH
6
7
8
30
14
16
33
36
18
WR
43
RS
3 IN 1
41
34
37
35
32
30
28
27
16
RS
5
IN 2
10
IN 3
12
IN 4
75Ω
OUT1 1
VOUT
7
OUT2
8
OUT3
14
OUT4
75Ω
RS
18, 29, 44
V+
4
-IN0:3
V11
2, 6 9, 13
-5V
+5V
31, 33, 36
11, 14
22, 38
-5V
20
26
NC
NOTE: All decoupling capacitors 0.1µF Ceramic (1 per supply pin). For lowest crosstalk, connect unused pins to GND use RS to tune the overall
output response.
FIGURE 2. TYPICAL HIGH PERFORMANCE, PARALLEL MODE APPLICATION CIRCUIT (SEE FIGURE 18)
Waveforms
VALID DATA
A2:0, D3:0
VALID DATA
tDS
tDH
tCS
CE
tCH
tWL
tWH
WR
tD
tL
LATCH
(EDGE MODE)
FIGURE 3. DIGITAL TIMING REQUIREMENTS
8
FN4153.7
September 26, 2008
HA456
Waveforms
(Continued)
DATA (N)
DATA (N + 1)
DATA (N + 2)
WR
LATCH
DATA (N)
MASTER REGISTER CONTENTS
SLAVE REGISTER CONTENTS
(EDGE/LEVEL = 0)
DATA (N + 1)
DATA (N + 1)
DATA (N)
SLAVE REGISTER CONTENTS
(EDGE/LEVEL = 1)
DATA (N + 2)
DATA (N + 2)
DATA (N + 1)
DATA (N)
DATA (N + 2)
FIGURE 4. PARALLEL PROGRAMMING MODE OPERATION (SER/PAR = 0)
NEW DATA FOR
OUT0
D3
SER IN
D2
D1
NEW DATA FOR
OUT1 TO OUT6
D0
D3
D2
NEW DATA FOR
OUT7
D3
D2
D1
1st
WRITE
WR
D0
32nd
WRITE
LATCH
t=0
SLAVE REGISTER CONTENTS
(EDGE/LEVEL = 0)
OLD DATA
SLAVE REGISTER CONTENTS
(EDGE/LEVEL = 1)
OLD DATA
NEW DATA
NEW DATA
FIGURE 5. SERIAL PROGRAMMING MODE OPERATION (SER/PAR = 1)
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FN4153.7
September 26, 2008
HA456
AC Test Circuits
IN0
OUT0
VOUT
IN1
OUT1
VOUT
IN2
OUT2
VOUT
OUT3
IN3
OUT3
VOUT
IN4
OUT4
IN4
OUT4
VOUT
IN5
IN0
OUT0
IN1
OUT1
IN2
OUT2
IN3
VOUT
OUT5
IN5
OUT5
VOUT
IN6
OUT6
IN6
OUT6
VOUT
IN7
OUT7
IN7
OUT7
VOUT
VIN = 1VP-P , AT 10MHz
VIN = 1VP-P , SWEEP FREQUENCY
FIGURE 6. -3dB BANDWIDTH (NOTES 8 thru 11)
7 X 75Ω
FIGURE 7. ALL HOSTILE OFF-ISOLATION (NOTES 11 thru 13)
IN0
OUT0
VOUT
IN0
OUT0
IN1
OUT1
VOUT
IN1
OUT1
IN2
OUT2
VOUT
IN2
OUT2
IN3
OUT3
VOUT
IN3
OUT3
IN4
OUT4
VOUT
IN4
OUT4
IN5
OUT5
VOUT
IN5
OUT5
IN6
OUT6
VOUT
IN6
OUT6
IN7
OUT7
IN7
OUT7
75Ω
VIN = 1VP-P , AT 10MHz
VIN = 1VP-P , AT 10MHz
FIGURE 8. SINGLE CHANNEL CROSSTALK (NOTES 11, 14
thru 17)
VOUT
FIGURE 9. ALL HOSTILE CROSSTALK (NOTES 11, 16, 18
thru 20)
NOTES:
8. Program the desired input to output combination (e.g., IN7 to OUT1).
9. Enable the selected output(s).
10. Drive the selected input with VIN, and measure the -3dB frequency at the selected output (VOUT).
11. Load all outputs with the desired RL.
12. Disable all outputs.
13. Drive all inputs with VIN and measure VOUT at any output; isolation (in dB) = -20log10 (VOUT/VIN).
14. Drive VIN on one input which connects to one output (e.g., IN7 to OUT7).
15. Terminate all other inputs to GND.
16. Enable all outputs.
17. Measure VOUT at any undriven output; crosstalk (in dB) = 20log10 (VOUT/VIN).
18. Terminate one input to GND, and connect that input to a single output (e.g., IN0 to OUT0).
19. Drive the other seven inputs with VIN, and connect these active inputs to the remaining seven outputs.
20. Measure VOUT at the quiescent output; crosstalk (in dB) = 20log10 (VOUT/VIN).
10
FN4153.7
September 26, 2008
HA456
VSUPPLY = ±5V, TA = +25°C, RL = 400Ω, Unless Otherwise Specified.
1.4
4
1.2
3
1.0
2
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Typical Performance Curves
0.8
0.6
0.4
0.2
0
1
0
-1
-2
-3
-0.2
-4
TIME (20ns/DIV)
FIGURE 10. SMALL SIGNAL PULSE RESPONSE
GAIN (dB)
3
0
TIME (20ns/DIV)
FIGURE 11. LARGE SIGNAL PULSE RESPONSE
VOUT = 0.2VP-P
GAIN
-3
VOUT = 1VP-P
1.0
VOUT = 2VP-P
PHASE
45
90
VOUT = 1VP-P
135
VOUT = 0.2VP-P
PHASE (°)
0
GAIN (dB)
-6
0.5
0
-0.5
VOUT = 1VP-P
-1.0
-1.5
VOUT = 0.2VP-P
-2.0
180
VOUT = 2VP-P
1M
10M
10M
200M
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 12. FREQUENCY RESPONSE
20
VIN = 1VP-P
-20
30
-30
40
RL = 150Ω
-40
-50
RL = 1kΩ
-60
-70
-80
100M
200M
VIN = 1VP-P
RL = 1kΩ
50
60
70
80
RL = 150Ω
90
100
-90
-100
200M
FIGURE 13. GAIN FLATNESS
OFF-ISOLATION (dB)
CROSSTALK (dB)
-10
10M
1M
10M
FREQUENCY (Hz)
FIGURE 14. ALL HOSTILE CROSSTALK
11
100M
200M
110
1M
10M
FREQUENCY (Hz)
FIGURE 15. ALL HOSTILE OFF-ISOLATION
FN4153.7
September 26, 2008
HA456
VSUPPLY = ±5V, TA = +25°C, RL = 400Ω, Unless Otherwise Specified. (Continued)
120
225
110
200
175
150
1 INPUT TO ALL OUTPUTS
100
90
80
1 INPUT TO 1 OUTPUT
70
60
125
PHASE
0
100
10
75
50
0.5
20
1.0
1.5
2.0
2.5
3.0
3.5 4.0
VOUT (VP-P)
4.5
5.0
5.5
6.0
0.03M
FIGURE 16. SLEW RATE vs VOUT
0.1M
1M
FREQUENCY (Hz)
PHASE (°)
MAGNITUDE (dBΩ)
250
30
100M
10M
FIGURE 17. INPUT IMPEDANCE vs FREQUENCY
RL =150Ω
RS = 0Ω
VOUT = 0.5VP-P
3
GAIN (dB)
SLEW RATE (V/µs)
Typical Performance Curves
0
-3
VOUT = 1VP-P
-6
1M
10M
FREQUENCY (Hz)
100M
200M
FIGURE 18. FREQUENCY RESPONSE OF HA456-HFA1412 COMBINATION (PER FIGURE 2)
12
FN4153.7
September 26, 2008
HA456
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
PIN (1) IDENTIFIER
0.042 (1.07)
0.056 (1.42)
0.004 (0.10)
C
0.025 (0.64)
R
0.045 (1.14)
0.050 (1.27) TP
C
L
D2/E2
E1 E
C
L
D2/E2
VIEW “A”
0.020 (0.51)
MIN
A1
A
D1
D
N44.65 (JEDEC MS-018AC ISSUE A)
44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.165
0.180
4.20
4.57
-
A1
0.090
0.120
2.29
3.04
-
D
0.685
0.695
17.40
17.65
-
D1
0.650
0.656
16.51
16.66
3
D2
0.291
0.319
7.40
8.10
4, 5
E
0.685
0.695
17.40
17.65
-
E1
0.650
0.656
16.51
16.66
3
E2
0.291
0.319
7.40
8.10
4, 5
N
44
44
SEATING
-C- PLANE
0.020 (0.51) MAX
3 PLCS
0.026 (0.66)
0.032 (0.81)
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
0.045 (1.14)
MIN
6
Rev. 2 11/97
VIEW “A” TYP.
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
4. To be measured at seating plane -C- contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN4153.7
September 26, 2008
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