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TERSIL
1-888-IN
ISL59450
®
Multiformat Video Crosspoint with
Integrated Sync Separator
February 14, 2008
FN7510.0
Features
• 6 Composite, 4 S-Video and 4 Component Video Sources
The ISL59450 is a video crosspoint switch supporting
multiple video input formats (CVBS, S-Video, YPbPr, and
RGB signals). Embedded anti-aliasing filters with
programmable corner frequencies eliminate glitch noise from
video DACs. The large number of inputs, wide range of
formats, integrated anti-aliasing filters, and dual
sync-separators make the ISL59450 an ideal choice for
video switching in nearly all display systems.
• 2 Component Inputs can be Configured for VGA with
Separate H and V Sync Inputs
• Multi-format Video Filtering
• Compatible with Macrovision® Encoded Signals
• Programmable Gain of x1 or x2
• Outputs have High Impedance Disable Mode
The ISL59450 is available in a 128 Ld MQFP package and is
specified for operation over the full -40°C to +85°C
temperature range.
• Two Universal Sync Separators support SD, HD, and
Computer Signals
Ordering Information
Applications
PART NUMBER
(Note)
ISL59450IQZ
PART
MARKING
ISL59450IQZ
PACKAGE
(Pb-free)
PKG.
DWG. #
128 Ld MQFP
MDP0055
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
• Pb-free (RoHS compliant)
• AV Receivers
• LCD-TVs
• AV Switch Boxes
• Projectors
• HDTV Systems
• Multiple Video Input Systems
Simplified Block Diagram
CVBSIN0
CVBSIN1
CVBSIN2
CVBSIN3
CVBSIN4
CVBSIN5
LPF
x1
x2
CVBSOUTA
LPF
x1
x2
CVBSOUTB
LPF
x1
x2
2
LPF
x1
x2
2
LPF
x1
x2
3
LPF
x1
x2
3
DC Restore
SvideoIN0
SvideoIN1
SvideoIN2
SvideoIN3
2
2
YPbPrIN0
YPbPrIN1
YPbPrIN2
YPbPrIN3
3
3
2
DC Restore
2
3
SvideoOUTA
SvideoOUTB
YPbPrOUTA
DC Restore
3
YPbPrOUTB
SOGs from Video Inputs
HSYNCINA
VSYNCINA
Sync Processor A
HSYNCOUTA
VSYNCOUTA
HSYNCINB
VSYNCINB
Sync Processor B
HSYNCOUTB
VSYNCOUTB
SCL
SDA
I2C System Control
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2008. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL59450
Absolute Maximum Ratings
Thermal Information
Voltage on VA
(referenced to GND = GNDA = GNDD) . . . . . . . . . . . . . . . . . 6.0V
Voltage on VD
(referenced to GND = GNDA = GNDD) . . . . . . . . . . . . . . . . . 4.0V
Voltage on any Analog Input Pin . . . . . . . . . . . . . -0.3V to VA + 0.3V
Voltage on any Digital Input Pin . . . . . . . . . . . . . . -0.3V to VD + 0.3V
Current into any Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
ESD Classification
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125V
Thermal Resistance
θJA (°C/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.84
Maximum Biased Junction Temperature . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature (Commercial) . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . VA = 5.0V, VD = 3.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
AC Electrical Specifications
PARAMETER
VA = 5.0V, VD = 3.3V, VIN = 0.7VP-P, TA = +25°C, RL = 150Ω, VTIPINx = 0.5V, VSLICEINx = 0.6V,
VLUMAx1INx = VLUMAx2INx = 0.8; VCHROMAx1INx = VCHROMAx2INx = 1.15V, all frequency response
measurements relative to f = 100kHz, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
f = 6MHz, GAIN 1
-1.6
-1.1
-0.4
dB
f = 6MHz, GAIN 2
-1.6
-1.1
-0.4
dB
f = 10MHz, GAIN 1
-4.2
-2.7
-1.5
dB
f = 10MHz, GAIN 2
-4.2
-2.7
-1.5
dB
f = 27MHz, GAIN 1
-30
-19
-11
dB
f = 27MHz, GAIN 2
-30
-19
-11
dB
YPbPr/RGB (Component) Video Inputs
YPbPr-10MHz
Passband Flatness, 10MHz Filter
Cutoff Flatness, 10MHz Filter
Stopband Rejection, 10MHz Filter
YPbPr-20MHz
Passband Flatness, 20MHz Filter
Cutoff Bandwidth, 20MHz Filter
Stopband Rejection, 20MHz Filter
YPbPr-36MHz
Passband Flatness, 36MHz Filter
Cutoff Bandwidth, 36MHz Filter
Stopband Rejection, 36MHz Filter
2
f = 54MHz, GAIN 1
-51
dB
f = 54MHZ, GAIN 2
-51
dB
f =12MHz, GAIN 1
-1.5
-0.9
-0.4
dB
f =12MHz, GAIN 2
-1.5
-0.9
-0.4
dB
f = 20MHz, GAIN 1
-3.6
-2.3
-1.3
dB
f = 20MHz, GAIN 2
-3.6
-2.3
-1.3
dB
f = 54MHz, GAIN 1
-30
-15
-9
dB
f = 54MHz, GAIN 2
-30
-15
-9
dB
f = 20MHz, GAIN 1
-1.6
-1
-0.4
dB
f = 20MHz, GAIN 2
-1.6
-1
-0.4
dB
f = 36MHz, GAIN 1
-4.7
-2.7
-1.5
dB
f = 36MHz, GAIN 2
-4.7
-2.7
-1.5
dB
f = 108MHz, GAIN 1
-22
dB
f = 108MHz, GAIN 2
-22
dB
FN7510.0
February 14, 2008
ISL59450
AC Electrical Specifications
PARAMETER
YPbPr-Bypass
VA = 5.0V, VD = 3.3V, VIN = 0.7VP-P, TA = +25°C, RL = 150Ω, VTIPINx = 0.5V, VSLICEINx = 0.6V,
VLUMAx1INx = VLUMAx2INx = 0.8; VCHROMAx1INx = VCHROMAx2INx = 1.15V, all frequency response
measurements relative to f = 100kHz, unless otherwise specified. (Continued)
DESCRIPTION
Passband Flatness, Filter Bypassed
Cutoff Bandwidth, Filter Bypassed
Positive Slew Rate, Filter Bypassed
CONDITIONS
MIN
TYP
MAX
UNIT
f = 220MHz, GAIN 1
±1
dB
f = 220MHz, GAIN 2
±1
dB
GAIN 1
275
MHz
GAIN 2
275
MHz
VOUT = 2VP-P, GAIN 1
350
450
V/µs
VOUT = 2VP-P, GAIN 2
450
590
V/µs
VOUT = 2VP-P, GAIN 1
350
440
V/µs
VOUT = 2VP-P, GAIN 2
720
950
V/µs
f =7MHz, GAIN 1
-2.3
-1.5
-0.8
dB
f =7MHz, GAIN 2
-2.3
-1.5
-0.8
dB
f = 11MHz, GAIN 1
-5.5
-3.4
-2
dB
f = 11MHz, GAIN 2
-5.5
-3.4
-2
dB
f = 27MHz, GAIN 1
-32
-21
-11
dB
f = 27MHz, GAIN 2
-32
-21
-11
dB
Passband Flatness, Filter Bypassed
f = 27MHz, GAIN 2
-2.3
-1
-0.8
dB
Cutoff Rejection, Filter Bypassed
f = 54MHz, GAIN 2
-12
-3.6
-2.5
dB
f = 5MHz, GAIN 1
-2.7
-1.7
-1
dB
f = 5MHz, GAIN 2
-2.7
-1.7
-1
dB
f = 7MHz, GAIN 1
-5
-3.2
-1.8
dB
f = 7MHz, GAIN 2
-5
-3.2
-1.8
dB
f = 27MHz, GAIN 1
-50
-39
-26
dB
f = 27MHz, GAIN 2
-50
-39
-26
dB
Passband Flatness, Filter Bypassed
f = 27MHz, GAIN 2
-1.9
-1.1
-0.7
dB
Cutoff Rejection, Filter Bypassed
f = 54MHz, GAIN 2
-7.2
-3.8
-2.7
dB
Differential Gain
f = 3.58MHz, GAIN 1
0.5
%
f = 3.58MHz, GAIN 2
0.3
%
f = 3.58MHz, GAIN 1
0.45
°
f = 3.58MHz, GAIN 2
0.65
°
85
dB
Negative Slew Rate, Filter Bypassed
S-Video VIDEO INPUTS
SV-10MHz
Passband Flatness, 10MHz Filter
Cutoff Rejection, 10MHz Filter
Stopband Rejection, 10MHz
SV-Bypass
CVBS (Composite) VIDEO INPUTS
CVBS-7MHz
Passband Flatness, 7MHz Filter
Cutoff Rejection, 7MHz Filter
Stopband Rejection, 7MHz Filter
CVBS-Bypass
dG
dP
Differential Phase
ALL VIDEO INPUTS
INTER-XTALK
Inter-Channel Crosstalk
3
Any input of Channel A to any output
Channel B and vice-versa, GAIN 1 and 2,
f = 10MHz
FN7510.0
February 14, 2008
ISL59450
DC Electrical Specifications VA = 5.0V, VD = 3.3V, TA = +25°C, RL = 150Ω, VTIPINx = 0.5V, VSLICEINx = 0.6V,
VLUMAx1INx = VLUMAx2INx = 0.8; VCHROMAx1INx = VCHROMAx2INx = 1.15V, unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
VA
Analog Supply Range
4.5
5.5
V
VD
Digital Supply Range
2.7
3.6
V
IA
Analog Supply Current
350
mA
ID
IDISABLED
PSRR
All output groups enabled
290
1 Composite output enabled
25
mA
1 S-video output group enabled
48
mA
1 Component output group enabled
75
mA
Digital Supply Current
Both sync separators enabled
3.5
6
mA
Standby Supply Current
Disabled Analog Current, IA
0.7
3
mA
Disabled Digital Current, ID
0.7
2.5
mA
GAIN 1 or 2, any output
50
dB
GAIN 1 or 2
45
dB
Power Supply Rejection
PSRRCLAMP_ON Rejection with Clamp Enabled
Gain
VOS-CLAMP
Low Frequency Gain
GAIN 1
0.95
1
1.05
V/V
GAIN 2
1.9
2.0
2.1
V/V
Clamp Offset (Delta between external
VREF = any reference input, GAIN 1
reference voltage and output during clamp)
VREF 30mV
VREF +
30mV
mV
VREF = any reference input, GAIN 2
VREF 30mV
VREF +
30mV
mV
VOS
VIN - VOUT
(Useful if DC-Coupling)
Clamp disabled, AV = 1
IPULLDOWN
Input Pulldown Current
VIN = 2V, clamp enabled (sinking)
Clamp Pullup Current
CV and S-Video, normal offset mode,
clamp enabled (sourcing)
100
130
170
µA
Component/RGB, normal offset mode,
clamp enabled (sourcing)
220
270
320
µA
CV and S-Video, low offset mode, clamp
enabled (sourcing)
220
270
320
µA
Component/RGB, low offset mode, clamp
enabled (sourcing)
400
500
650
µA
VIN = 3V, AV2 = 2.0V, Sourcing, RL = 10Ω
to GND
60
102
140
mA
VIN = 0V, Sinking, RL = 10Ω to +3V
20
30
40
mA
2.5
V
ICLAMP
ISC
VOUT-LIN
Short Circuit Current
Output Linear Voltage Range
0.45
V
1
µA
0.5
LOGIC INPUTS (SDA, SCL, Address, Reset, PowerDown, HSYNCINx, VSYNCINx, SDETx)
VIH
Input High Voltage (HIGH)
All logic pins, except Reset
Reset (Pin must be >3.5V to ensure part is
not resetting)
VIL
Input Low Voltage (LOW)
IIH
Input High Current (VIN = 5V, Logic Inputs,
Sinking)
IIL
Input Low Current (VIN = 0V, Logic Inputs,
Sourcing)
4
2
V
3.5
V
0.8
V
No pull-up or pull-down
-1
0
1
µA
Pins with 300kΩ internal pull-downs:
Address, Reset, Power-down
8
17
34
µA
No pull-up or pull-down
-1
0
1
µA
Pins with 300kΩ internal pull-up: SDETx
10
15
25
µA
FN7510.0
February 14, 2008
ISL59450
Serial Interface (I2C) Specifications
SYMBOL
VOL
PARAMETER
CONDITIONS
MIN
(Note 1)
TYP
0
MAX
(Note 1)
UNIT
0.4
V
SDA Output Buffer LOW Voltage
IOL = 4mA
ILI
Input Leakage Current on SCL
VIN = 5.5V
0.1
1
µA
ILO
I/O Leakage Current on SDA
VIN = 5.5V
0.1
1
µA
400
kHz
TIMING CHARACTERISTICS
fSCL
SCL Frequency
tLOW
Clock LOW Time
Measured at the 30% of VD crossing.
1.3
tHIGH
Clock HIGH Time
Measured at the 70% of VD crossing.
0
tSU:STA
START Condition Set-up Time
SCL rising edge to SDA falling edge. Both
crossing 70% of VD.
0.6
µs
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VD
to SCL falling edge crossing 70% of VD.
0.6
µs
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing 70% of VD
to SDA entering the 30% to 70% of VD
window.
0
tSU:STO
STOP Condition Set-up Time
From SCL rising edge crossing 70% of VD,
to SDA rising edge crossing 30% of VD
0.6
µs
tR
SDA and SCL Rise Time
From 30% to 70% of VD
20 +
0.1 x Cb
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VD
20 +
0.1 x Cb
ns
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
Cb
Cpin
SDA and SCL Pin Capacitance
µs
0.9
0.9
µs
µs
400
pF
10
pF
NOTE:
1. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
I2C Timing
Diagram
tF
tHIGH
tLOW
tR
SCL
tSU:STA
tHD:STA
SDA
(INPUT TIMING)
tHD:DAT
tSU:STO
SDA
(OUTPUT TIMING)
5
FN7510.0
February 14, 2008
ISL59450
Functional Diagram
VA = 5.0V
CVIN0
CVIN1
CVIN2
CVIN3
CVIN4
CVIN5
VA = 5.0V
Composite
Channel A
CVIN0
CVIN1
CVIN2
CVIN3
CVIN4
CVIN5
CVOUTA
GND
Composite
Channel B
CVOUTB
GND
SYNCCV
SYNCCV
VA = 5.0V
VA = 5.0V
SYIN0
SCIN0
SYIN0
SCIN0
SYIN1
SCIN1
SYIN2
SCIN2
SYNCY-C
VA = 5.0V
YIN0
PrIN0
PbIN0
GND
SYNCY-C
VA = 5.0V
YIN0
PrIN0
PbIN0
YIN1
PrIN1
PbIN1
YOUTA
PrOUTA
PbOUTA
Component
Channel A
YIN2
PrIN2
PbIN2
SYIN3
SCIN3
Component
Channel B
YIN2
PrIN2
PbIN2
YIN3
PrIN3
PbIN3
KEYED CLAMP TIMING
(SLAVE MODE)
GND
SYOUTB
SCOUTB
S-Video
Channel B
SYIN2
SCIN2
KEYED CLAMP TIMING
(SLAVE MODE)
SYIN3
SCIN3
YIN1
PrIN1
PbIN1
SYIN1
SCIN1
SYOUTA
SCOUTA
S-Video
Channel A
YOUTB
PrOUTB
PbOUTB
YIN3
PrIN3
PbIN3
VD = 3.3V
CLAMPOUTA
HSYNCINA
VSYNCINA
FIELDOUTA
SYNC Separator A
HSYNCOUTA
CLAMPOUTB
HSYNCINB
VSYNCINB
SYNC Separator B
FIELDOUTB
HSYNCOUTB
VSYNCOUTA
GNDD
SYNCCOMP.
VD = 3.3V
GND
SYNCCOMP.
GND
VSYNCOUTB
GNDD
DIGITAL CONTROL
SIGNALS
VD = 3.3V
SDA
SCL
I2C Interface
RESET
ADDRESS
GNDD
6
FN7510.0
February 14, 2008
ISL59450
Component Block Diagram
Component
Control Register
Bits 7, 4
SLICER
VSLICE
-
VLUMAx1
1,0
VLUMAx2
1,1
+
Component
Control
Register
Bit 7
Clamp
(from Sync Sep.)
YIN0
00
YIN1
01
YIN2
10
YIN3
11
0
1
1µA
VCHROMAx1
0,0
VCHROMAx2
0,1
VLUMAx1
1,0
VLUMAx2
1,1
PrIN0
00
PrIN1
01
Clamp from Sync
Separator
+
1
Component
Control
Register
Bit 7
-
+
LPF
10
x1
x2
PrOUT
VOS
1µA
11
Component
Control Register
Bits 3:2
Component Control
Register
Bits 1:0
Component Control
Register
Bits 6, 4
VCHROMAx1
0,0
VCHROMAx2
0,1
VLUMAx1
1,0
VLUMAx2
1,1
PbIN0
00
PbIN1
01
PbIN2
10
PbIN3
YOUT
Component
Control Register
Bits 3:2
Component Control
Register
Bits 6, 4
PrIN3
x1
x2
VOS
Component
Control Register
Bits 1:0
PrIN2
+ LPF
Clamp from Sync
Separator
+
1
0
0,X
0
VTIP
Component
Control
Register
Bit 7
+
-
LPF
x1
x2
PbOUT
VOS
1µA
11
Component Control
Register
Bits 1:0
7
Sync Timing
(to Sync Separator)
+
Component
Control Register
Bits 3:2
FN7510.0
February 14, 2008
ISL59450
S-Video Block Diagram
S-Video Control
Register
Bits 7, 4
SLICER
VSLICE
Sync Timing
(to Sync Separator)
+
0,X
VLUMAx1
1,0
VLUMAx2
1,1
+
S-Video
Control
Register
Bit 7
Clamp
(from Sync Sep.)
SYIN0
00
SYIN1
01
SYIN2
10
SYIN3
11
0
1
+ VOS
1µA
S-Video Control
Register
Bit 4
VCHROMAx1
0
VCHROMAx2
1
SCIN0
00
SCIN1
01
SCIN2
10
SYOUT
S-Video Control
Register
Bit 3
S-Video Control
Register
Bits 1:0
Clamp from Sync
Separator
S-Video
Control
Register
Bit 7
+
1
-
+
LPF
x1
x2
SCOUT
VOS
1µA
SCIN3
x1
x2
LPF
0
VTIP
11
S-Video Control
Register
Bit 3
S-Video Control
Register
Bits 1:0
Composite Block Diagram
Composite
Control Register
Bits 7, 4
SLICER
VSLICE
+
-
VTIP
0,X
VLUMAx1
1,0
VLUMAx2
1,1
+
Composite
Control
Register
Bit 7
Clamp
(from Sync Sep.)
CVIN0
CVIN1
CVIN2
CVIN3
CVIN4
CVIN5
000
001
010
011
100
101
Composite Control
Register
Bits 2:0
8
Sync Timing
(to Sync Separator)
1
0
+
-
LPF
VOS
1µA
x1
x2
CVOUT
Composite Control
Register
Bit 3
FN7510.0
February 14, 2008
ISL59450
Sync Separator Block Diagram
Keyed Clamp
Timing Signal
(To All
Channels)
Sync Separator
control bits 1:0
ClampOut
Sync
Separator
Enable (bit 5)
SYNC from
Composite SLICER
10
SYNC from
S-Video SLICER
01
SYNC from
Component SLICER
00
Sync
Separator
control bit 2
Sync
Separator
1
0
Sync
Separator
control bits 3:0
HSYNCIN
Sync Separator
control bit 7
H
V
1011
1
11
0
HSYNCIN
All
other
settings
FieldOut
HSYNCOUT
H
VSYNCIN
V
VSYNCOUT
0
1
9
FN7510.0
February 14, 2008
ISL59450
Typical Application Circuit
+5V
0.1µF
+3.3V
µC
75Ω + 0.1µF
1µF
75Ω
COMPOSITE 1
75Ω + 0.1µF
CVIN0
COMPOSITE 2
75Ω + 0.1µF
CVIN1
COMPOSITE 3
75Ω + 0.1µF
CVIN2
COMPOSITE 4
75Ω + 0.1µF
CVIN3
COMPOSITE 5
75Ω + 0.1µF
CVIN4
COMPOSITE 6
75Ω + 0.1µF
CVIN5
S-Video Luma 1
75Ω + 0.1µF
SYIN0
S-Video Chroma 1
75Ω + 0.1µF
SCIN0
S-Video Luma 2
75Ω + 0.1µF
SYIN1
S-Video Chroma 2
75Ω + 0.1µF
SCIN1
SDA
SCL Powerdown
Address
Reset
0.01µF
0.01µF
1µF
VA V D
CVOUTA
75Ω
75Ω
CVOUTB
75Ω
S-Video Luma 3
75Ω + 0.1µF
SYIN2
S-Video Chroma 3
75Ω + 0.1µF
SCIN2
S-Video Luma 4
75Ω + 0.1µF
SYIN3
75Ω + 0.1µF
SCIN3
S-Video Chroma 4
SYOUTA
SCOUTA
S-Video
Out
75Ω
75Ω
SYOUTB
S-Video
Out
75Ω
SCOUTB
YOUTA
PrOUTA
75Ω
75Ω
HD Out
75Ω
PbOUTA
HSYNCOUTA
VSYNCOUTA
Component Luma 1
Component Pb 1
75Ω+ 0.1µF
YIN0
75Ω + 0.1µF
PbIN0
Component Pr 1
75Ω + 0.1µF
PrIN0
ISL59450
YOUTB
75Ω
75Ω
PrOUTB
75Ω
VGA
Out
PbOUTB
Component Luma 2
Component Pb 2
75Ω + 0.1µF
YIN1
75Ω + 0.1µF
PbIN1
HSYNC OUTB
Component Pr 2
75Ω + 0.1µF
PrIN1
VSYNC OUTB
Green 1 (SoG)
Blue 1
75Ω + 0.1µF
YIN2
75Ω + 0.1µF
PbIN2
Red 1
75Ω + 0.1µF
PrIN2
VLUMAX1INA
HSYNC INA
VLUMAX1INB
VSYNC INA
VLUMAX2INB
VTIPINA
VTIPINB
0.5V
VLUMAX2INA
Green 2
Blue 2
75Ω + 0.1µF
YIN3
75O + 0.1µF
Pb IN3
Red 2
75Ω + 0.1µF
PrIN3
HSYNC 2
VSYNC 2
0.1µF
VSLICE INA
VSLICE INB
0.6V
0.1µF
HSYNC INB
VSYNC INB
VCHROMAX1INA
VCHROMAX2INA
1V
VCHROMAX1INB
CSETA
56nF
10
CSETB
56nF
GND
VCHROMAX2INB
0.1µF
FN7510.0
February 14, 2008
ISL59450
Pinout
CSETA
HSYNCINA
GNDD
GNDD
GNDD
DNC
ClampOUTA
108
107
106
105
104
103
GNDD
111
VSYNCINA
GNDD
112
109
GNDD
110
VD
113
VLUMAx1INA
119
114
VLUMAx2INA
120
GNDD
VCHROMAx1INA
121
115
VCHROMAx2INA
122
GNDD
GNDA
123
116
GNDA
124
117
VA
125
VSLICEINA
GNDA
126
VTIPINA
CVIN0
127
118
CVIN1
128
ISL59450
(128 LD MQFP)
TOP VIEW
C V IN 2
1
102
Field O U T A
SD E T 0
2
101
VSY N C O U T A
H SY N C O U T A
SY IN 0
3
100
SC IN 0
4
99
VD
SD E T 1
5
98
GNDA
SY IN 1
6
97
GNDA
SC IN 1
7
96
C V O U TA
GNDA
8
95
GNDA
Y IN 0
9
94
SY O U T A
Pb IN 0
10
93
SC O U T A
Pr IN 0
11
92
Address
GNDA
12
91
Y OU TA
Y IN 1
13
90
P ow erD ow n
GNDA
14
89
Pb O U T A
Pb IN 1
15
88
Pr O U T A
Pr IN 1
16
87
VA
GNDA
17
86
GNDD
VA
18
85
SD A
GNDA
19
84
GNDD
VA
20
83
VD
GNDA
21
82
SC L
Y IN 2
22
81
GNDA
GNDA
23
80
VA
Pb IN 2
24
79
Pr O U T B
Pr IN 2
25
78
Pb O U T B
GNDA
26
77
R eset
Y IN 3
27
76
Y OU TB
GNDA
28
75
GNDD
Pb IN 3
29
74
SC O U T B
Pr IN 3
30
73
SY O U T B
SD E T 2
31
72
GNDA
SY IN 2
32
71
C V O U TB
SC IN 2
33
70
GNDA
SD E T 3
34
69
GNDA
11
ClampOUTB 64
DNC 63
GNDD
62
GNDD 61
GNDD 60
VSYNCINB
HSYNCINB 59
58
CSETB 57
GNDD 56
GNDD 55
GNDD
54
VD 53
GNDD 52
GNDD 51
VTIPINB
50
VSLICEINB 49
Field O U T B
VLUMAx1INB 48
65
VLUMAx2INB 47
38
VCHROMAx1INB 46
VSY N C O U T B
C V IN 3
VCHROMAx2INB 45
66
GNDA 44
37
VA 42
H SY N C O U T B
GNDA
GNDA 43
VD
67
GNDA 41
68
36
CVIN5 40
35
CVIN4 39
SY IN 3
SC IN 3
FN7510.0
February 14, 2008
ISL59450
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
COMPOSITE (CV) VIDEO INPUTS (6x1)
127
CVIN0
Composite Video Input 0
128
CVIN1
Composite Video Input 1
1
CVIN2
Composite Video Input 2
38
CVIN3
Composite Video Input 3
39
CVIN4
Composite Video Input 4
40
CVIN5
Composite Video Input 5
COMPOSITE (CV) VIDEO OUTPUTS
96
CVOUTA
Composite Video Output A with High-Z disable mode
71
CVOUTB
Composite Video Output B with High-Z disable mode
S-VIDEO (SV) INPUTS (4x2)
3
SYIN0
S-Video Luma Input 0
4
SCIN0
S-Video Chroma Input 0
6
SYIN1
S-Video Luma Input 1
7
SCIN1
S-Video Chroma Input 1
32
SYIN2
S-Video Luma Input 2
33
SCIN2
S-Video Chroma Input 2
35
SYIN3
S-Video Luma Input 3
36
SCIN3
S-Video Chroma Input 3
S-VIDEO (SV) OUTPUTS
94
SYOUTA
S-Video Luma Output A with High-Z disable mode
93
SCOUTA
S-Video Chroma Output A with High-Z disable mode
73
SYOUTB
S-Video Luma Output B with High-Z disable mode
74
SCOUTB
S-Video Chroma Output B with High-Z disable mode
S-VIDEO CONNECTION DETECTION PINS
2
SDET0
Digital Input with internal pull-up to VA. Detects S-Video connector 0. Tie to NC switch on S-Video connector,
with other end of switch tied to ground. 0V = no cable attached, VA = S-Video cable attached. 300k pull-up
to analog supply.
5
SDET1
Digital Input with internal pull-up to VA. Detects S-Video connector 1. Tie to NC switch on S-Video connector,
with other end of switch tied to ground. 0V = no cable attached, VA = S-Video cable attached. 300k pull-up
to analog supply.
31
SDET2
Digital Input with internal pull-up to VA. Detects S-Video connector 2. Tie to NC switch on S-Video connector,
with other end of switch tied to ground. 0V = no cable attached, VA = S-Video cable attached. 300k pull-up
to analog supply.
34
SDET3
Digital Input with internal pull-up to VA. Detects S-Video connector 3. Tie to NC switch on S-Video connector,
with other end of switch tied to ground. 0V = no cable attached, VA = S-Video cable attached. 300k pull-up
to analog supply.
COMPONENT (YPbPr) VIDEO INPUTS (4x3)
9
YIN0
Luma component (or Green RGB) video input 0
10
PbIN0
Chroma Pb component (or Blue RGB) video input 0
11
PrIN0
Chroma Pr component (or Red RGB) video input 0
13
YIN1
Luma component (or Green RGB) video input 1
15
PbIN1
Chroma Pb component (or Blue RGB) video input 1
12
FN7510.0
February 14, 2008
ISL59450
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
DESCRIPTION
16
PrIN1
Chroma Pr component (or Red RGB) video input 1
22
YIN2
Luma component (or Green RGB) video input 2
24
PbIN2
Chroma Pb component (or Blue RGB) video input 2
25
PrIN2
Chroma Pr component (or Red RGB) video input 2
27
YIN3
Luma component (or Green RGB) video input 3
29
PbIN3
Chroma Pb component (or Blue RGB) video input 3
30
PrIN3
Chroma Pr component (or Red RGB) video input 3
COMPONENT VIDEO OUTPUTS
91
YOUTA
Component Video Luma Output A with High-Z disable mode
89
PbOUTA
Chroma Pb component (or Blue Component) Video Output A with High-Z disable
88
PrOUTA
Chroma Pr component (or Red Component) Video Output A with High-Z disable
76
YOUTB
Component Video Luma Output B with High-Z disable mode
78
PbOUTB
Chroma Pb component (or Blue Component) Video Output B with High-Z disable
79
PrOUTB
Chroma Pr component (or Red Component) Video Output B with High-Z disable
A SYNC SEPARATOR INPUTS AND OUTPUTS
108
HSYNCINA
Horizontal External Sync Source for Sync Separator A. This signal may be pure HSYNC or CSYNC.
109
VSYNCINA
Vertical External Sync Source for Sync Separator A
110
CSETA
Sync Separator filter capacitor. Connect a 0.056µF capacitor between this pin and analog ground.
100
HSYNCOUTA
Horizontal Sync Output for Sync Separator A
101
VSYNCOUTA
Vertical Sync Output for Sync Separator A
102
FieldOUTA
Field Flag for Sync Separator A. Low = odd field, high = even field.
103
ClampOUTA
External Clamp Timing Pulse for Sync Separator A (for timed back porch clamping)
B SYNC SEPARATOR INPUTS AND OUTPUTS
59
HSYNCINB
Horizontal External Sync Source for Sync Separator B. This signal may be pure HSYNC or CSYNC.
58
VSYNCINB
Vertical External Sync Source for Sync Separator B
57
CSETB
Sync Separator filter capacitor. Connect a 0.056µF capacitor between this pin and analog ground.
67
HSYNCOUTB
Horizontal Sync Output from Sync Separator B
66
VSYNCOUTB
Vertical Sync Output from Sync Separator B
65
FieldOUTB
Field Flag for Sync Separator B. Low = odd field, high = even field.
64
ClampOUTB
External Clamp Timing Pulse for Sync Separator B (for timed back porch clamping)
EXTERNAL DC REFERENCE LEVELS
122
VCHROMAx2INA
Analog Input. Chroma Reference Level for DC-Restore when AV = 2, for Channel A. This DC voltage sets
the midpoint voltage of the C signal (S-Video) and the Pb, Pr signals (Component video) for Channel A when
the gain is set to x2. When using the YPbPr inputs in YPbPr mode, this DC voltage sets the clamp voltage
of the Pr/R and Pb/B signals for Channel A. This input is typically tied together with VCHROMAx2INB and
driven with the same voltage.
121
VCHROMAx1INA
Analog Input. Chroma Reference Level for DC-Restore when AV = 1, for Channel A. This voltage sets the
midpoint voltage of the C signal (S-Video) and the Pb, Pr signals (Component video) for Channel A when
the gain is set to x1. When using the YPbPr inputs in YPbPr mode, this DC voltage sets the clamp voltage
of the Pr/R and Pb/B signals for Channel A. This input is typically tied together with VCHROMAx1INB and
driven with the same voltage.
13
FN7510.0
February 14, 2008
ISL59450
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
DESCRIPTION
120
VLUMAx2INA
Analog Input. Luma Reference Level for DC-Restore when AV = 2, for Channel A. When using the YPbPr
inputs in RGB mode, this DC voltage sets the clamp voltage of the Pr/R and Pb/B signals for Channel A
when the gain is set to x2. When using the YPbPr inputs in YPbPr mode, this DC voltage sets the clamp
voltage of the Pr/R and Pb/B signals for Channel A.This input is typically tied together with VLUMAx2INB
and driven with the same voltage. The Y/G signal is clamped to the VTIPINA voltage in master mode and
VLUMAx2INA in slave mode.
119
VLUMAx1INA
Analog Input. Luma Reference Level for DC-Restore when AV = 1, for Channel A. When using the YPbPr
inputs in RGB mode, this DC voltage sets the clamp voltage of the R and B signals for Channel A when
the gain is set to x1. This input is typically tied together with VLUMAx1INB and driven with the same voltage.
The Y/G signal is clamped to the VTIPINA voltage in master mode and VLUMAx1INA in slave mode.
118
VSLICEINA
Analog Input. Slicer comparator threshold for extracting composite sync from video, for Channel A. This DC
voltage is typically set to 0.07V above VTIPINA, creating a sync tip slicing level of 70mV. This input is
typically tied together with VSLICEINB and driven with the same voltage.
117
VTIPINA
Analog Input. Sync Tip Reference Level for DC-Restore, for Channel A. This DC voltage sets the level of
the sync tip of Channel A’s output signal. This input is typically tied together with VTIPINB and driven with
the same voltage. In RGB mode (with no Sync-on-Green), this sets the black level of the G channel.
45
VCHROMAx2INB
Analog Input. Chroma Reference Level for DC-Restore when AV = 2, for Channel A. This DC voltage sets
the midpoint voltage of the C signal (S-Video) and the Pb, Pr signals (Component video) for Channel A when
the gain is set to x2. When using the YPbPr inputs in YPbPr mode, this DC voltage sets the clamp voltage
of the Pr/R and Pb/B signals for Channel B. This input is typically tied together with VCHROMAx2INA and
driven with the same voltage.
46
VCHROMAx1INB
Analog Input. Chroma Reference Level for DC-Restore when AV = 1, for Channel A. This voltage sets the
midpoint voltage of the C signal (S-Video) and the Pb, Pr signals (Component video) for Channel A when
the gain is set to x1. When using the YPbPr inputs in YPbPr mode, this DC voltage sets the clamp voltage
of the Pr/R and Pb/B signals for Channel B. This input is typically tied together with VCHROMAx1INA and
driven with the same voltage.
47
VLUMAx2INB
Analog Input. Luma Reference Level for DC-Restore when AV = 2, for Channel B. When using the YPbPr
inputs in RGB mode, this DC voltage sets the clamp voltage of the R and B signals for Channel B when
the gain is set to x2. This input is typically tied together with VLUMAx2INA and driven with the same voltage.
The Y/G signal is clamped to the VTIPINB voltage in master mode and VLUMAx2INB in slave mode.
48
VLUMAx1INB
Analog Input. Luma Reference Level for DC-Restore when AV = 1, for Channel B. When using the YPbPr
inputs in RGB mode, this DC voltage sets the clamp voltage of the R and B signals for Channel B when
the gain is set to x1. This input is typically tied together with VLUMAx1INA and driven with the same voltage.
The Y/G signal is clamped to the VTIPINB voltage in master mode and VLUMAx1INB in slave mode.
49
VSLICEINB
Analog Input. Slicer comparator threshold for extracting composite sync from video, for Channel B. This DC
voltage is typically set to 0.07V above VTIPINB, creating a sync tip slicing level of 70mV. This input is
typically tied together with VSLICEINA and driven with the same voltage.
50
VTIPINB
Analog Input. Sync Tip Reference Level for DC-Restore, for Channel B. This DC voltage sets the level of
the sync tip of Channel B’s output signal. This input is typically tied together with VTIPINA and driven with
the same voltage. In RGB mode (with no Sync-on-Green), this sets the black level of the G channel.
I2C CONTROL AND I/O
85
SDA
I2C Bus Data I/O
82
SCL
I2C Bus Clock
92
Address
Digital Input with internal pull-down. Sets I2C address: 0x84 if tied low, 0x8C if tied high. (300k pull-down)
IC RESET, ENABLE AND MISC.
77
Reset
5V Digital Input, with 3.5V logic threshold and a 300k pull-down. Tie to +5V for normal operation. Taking
Reset to 0V and back to 5V initializes all data registers to 0x00.
90
PowerDown
Digital Input with 300k pull-down. When this pin is taken high, all analog circuitry is disabled to minimize
power consumption. In PowerDown mode, the outputs are tri-stated while the I2C interface remains active
and all register data is retained.
POWER SUPPLIES
18, 20, 42, 125 VA
+5V Analog supply
14
FN7510.0
February 14, 2008
ISL59450
Pin Descriptions (Continued)
PIN NUMBER
80, 87
PIN NAME
VA
DESCRIPTION
+5V Analog supply for output drivers
POWER SUPPLIES DIGITAL (3V)
83
Digital Plus Supply for I2C
VD
53, 68, 99, 114 VD
Digital Supply for Sync Separators
POWER SUPPLIES ANALOG GROUND (0V)
8, 12, 14, 17, GNDA
19, 21, 23, 26,
28, 37, 41, 43,
44, 69, 70, 72,
81, 95, 97, 98,
123, 124, 126
Analog Ground
POWER SUPPLIES DIGITAL GROUND (0V)
51, 52, 54, 55, GNDD
56, 60, 61, 62,
75, 84, 86,
105, 106, 107,
111, 112, 113,
115, 116
Digital Ground
UNUSED PINS
63, 104
DNC
Not Implemented. Do Not Connect these pins to anything (leave floating).
Typical Performance Curves
SUPPLY CURRENT (mA)
279
278
4.0
NO INPUT
NO LOAD
ALL OUTPUTS ENABLED
DIGITAL SUPPLY CURRENT (mA)
280
VA = +5V, VD = +3.3V, RL = 150Ω to GND, TA = +25°C, unless otherwise specified.
277
276
275
274
273
272
4.5
4.6
4.7
4.8
4.9
5.0
5.1
VOLTAGE (V)
5.2
5.3
5.4
5.5
FIGURE 1. ANALOG SUPPLY CURRENT vs SUPPLY
VOLTAGE
FILTER BYPASSED
MAGNITUDE (dB)
MAGNITUDE (dB)
-5
-10
-15
-20
FILTER ENABLED
-25
-30
-35
VIN = 700mVP-P
-40
0.1M
1M
10M
FREQUENCY (Hz)
100M
1G
FIGURE 3. COMPOSITE FREQUENCY RESPONSE (GAIN 1)
15
3.0
2.5
2.0
1.5
1.0
2.7
NO INPUT
NO LOAD
BOTH SYNC SEPARATOR ENABLED
2.8
2.9
3.0
3.1
3.2
VOLTAGE (V)
3.3
3.4
3.5
3.6
FIGURE 2. DIGITAL SUPPLY CURRENT vs SUPPLY VOLTAGES
5
0
3.5
3
FILTER BYPASSED
1
-1
-3
-5
-7
FILTER ENABLED
-9
-11
-13
-15
-17
-19 V = 700mV
IN
P-P
-21
0.1M
1M
10M
100M
FREQUENCY (Hz)
FIGURE 4. COMPOSITE FREQUENCY RESPONSE (GAIN 2)
FN7510.0
February 14, 2008
ISL59450
0
-2
-4
-6
-8
-10
-12
-14
-16
VA = +5V, VD = +3.3V, RL = 150Ω to GND, TA = +25°C, unless otherwise specified. (Continued)
FILTER BYPASSED
MAGNITUDE (dB)
MAGNITUDE (dB)
Typical Performance Curves
FILTER ENABLED
-18
-20 VIN = 700mVP-P
-22
0.1M
1M
10M
FREQUENCY (Hz)
100M
5
0
-5
COMPONENT
-10
10MHz
-15
-20
COMPONENT
20MHz
-25
-30
COMPONENT
-35
36MHz
-40
-45
-50 VIN = 700mVP-P
-55
0.1M
1M
10M
FREQUENCY (Hz)
COMPONENT
BYPASS
100M
1G
5
0
-5
COMPONENT
-10
10MHz
-15
COMPONENT
-20
20MHz
-25
-30
COMPONENT
-35
36MHz
-40
-45
-50 VIN = 700mVP-P
-55
0.1M
1M
10M
FREQUENCY (Hz)
COMPONENT
BYPASS
100M
1G
FIGURE 7. COMPONENT BANDWIDTH vs FREQUENCY
RESPONSE (GAIN = 1)
FIGURE 8. COMPONENT BANDWIDTH vs FREQUENCY
RESPONSE (GAIN = 2)
0.2
0.7
0.1
0.6
GAIN 2
0.5
0
0.4
-0.2
DP (°)
-0.1
DG (%)
100M
FIGURE 6. S-VIDEO FREQUENCY RESPONSE (GAIN 2)
MAGNITUDE (dB)
MAGNITUDE (dB)
FIGURE 5. S-VIDEO FREQUENCY RESPONSE (GAIN 1)
0
-2
-4
-6
FILTER BYPASSED
-8
-10
-12
-14
-16
FILTER ENABLED
-18
-20 V = 700mV
IN
P-P
-22
0.1M
1M
10M
FREQUENCY (Hz)
GAIN 1
-0.3
VAC = 40mVP-P
f = 3.58MHz
COMPOSITE OUTPUT
FILTER ENABLED
-0.4
-0.5
-0.6
0.1
0.3
0.5
0.7
0.9
1.1
1.3
OUTPUT DC VOLTAGE (V)
FIGURE 9. DIFFERENTIAL GAIN
16
1.5
1.7
1.9
GAIN 2
0.3
GAIN 1
0.2
0.1
VAC = 40mVP-P
f = 3.58MHz
COMPOSITE OUTPUT
FILTER ENABLED
0
-0.1
-0.2
0.1
0.3
0.5
0.7
0.9
1.1
1.3
OUTPUT DC LEVEL (V)
1.5
1.7
1.9
FIGURE 10. DIFFERENTIAL PHASE
FN7510.0
February 14, 2008
ISL59450
Typical Performance Curves
VA = +5V, VD = +3.3V, RL = 150Ω to GND, TA = +25°C, unless otherwise specified. (Continued)
COMPOSITE INPUT
TIMEBASE = 100ns/DIV
INPUT: 200mV/DIV
OUTPUT: 500mV/DIV
COMPOSITE INPUT
COMPOSITE OUTPUT
GAIN 2
FILTER ENABLED
VTIP = 0.5V
COMPOSITE OUTPUT
GAIN 2
FILTER ENABLED
VTIP = 0.5V
TIMEBASE = 10µs/div
INPUT: 500mV/div
OUTPUT: 1V/div
FIGURE 11. COLORBAR RESPONSE
FIGURE 12. 2T RESPONSE
TIMEBASE = 500ns/DIV
INPUT: 200mV/DIV
OUTPUT: 500mV/DIV
COMPONENT OUTPUT
COMPOSITE INPUT
GAIN 2
FILTER ENABLED
VTIP = 0.5V
COMPOSITE OUTPUT
fIN = 10MHz
TIMEBASE = 10ns/DIV
VERTICLE SCALE: 500mV/DIV
FIGURE 13. 12.5T RESPONSE
FIGURE 14. COMPONENT LARGE SIGNAL PULSE
RESPONSE GAIN 1
70
60
COMPONENT OUTPUT
DELAY (ns)
50
GAIN 1 AND
GAIN 2
40
30
20
fIN = 10MHz
TIMEBASE = 10ns/DIV
VERTICLE SCALE: 500mV/DIV
FIGURE 15. COMPONENT LARGE SIGNAL PULSE
RESPONSE GAIN 2
17
10
VIN = 700mVP-P
0
0.1M
1M
10M
FREQUENCY (Hz)
100M
FIGURE 16. COMPOSITE GROUP DELAY
FN7510.0
February 14, 2008
ISL59450
Typical Performance Curves
VA = +5V, VD = +3.3V, RL = 150Ω to GND, TA = +25°C, unless otherwise specified. (Continued)
60
45
40
35
DELAY (ns)
DELAY (ns)
50
GAIN 1 AND
GAIN 2
40
30
20
20
GAIN 1
10
VIN = 700mVP-P
0
0.1M
1M
10M
FREQUENCY (Hz)
5 V = 700mV
IN
P-P
0
0.1M
100M
FIGURE 17. S-VIDEO GROUP DELAY
1M
10M
FREQUENCY (Hz)
100M
FIGURE 18. COMPONENT 10MHz FILTER GROUP DELAY
25
18
GAIN 1
16
20
14
15
DELAY (ns)
DELAY (ns)
25
15
10
GAIN 2
10
12
8
6
4
VIN = 700mVP-P
0
0.1M
2
1M
10M
FREQUENCY (Hz)
GAIN 1 AND
GAIN 2
10
5
VIN = 700mVP-P
0
0.1M
100M
FIGURE 19. COMPONENT 20MHz FILTER GROUP DELAY
1M
10M
FREQUENCY (Hz)
100M
FIGURE 20. COMPONENT 36MHz FILTER GROUP DELAY
-50
5.0
4.5
GAIN 1
-55
3.5
CROSSTALK (dB)
4.0
DELAY (ns)
GAIN 2
30
GAIN 2
3.0
2.5
2.0
1.5
1.0
-65
-70
ANY INPUT OF CHANNEL A TO ANY
OUTPUT CHANNEL B AND VICE-VERSA
GAIN 1 AND GAIN 2
-75
-80
-85
0.5
VIN = 700mVP-P
0
0.1M
1M
-60
10M
FREQUENCY (Hz)
100M
FIGURE 21. COMPONENT BYPASS GROUP DELAY
18
1G
-90
0.1M
1M
10M
FREQUENCY (Hz)
100M
FIGURE 22. INTER-CHANNEL CROSSTALK
FN7510.0
February 14, 2008
ISL59450
Typical Performance Curves
0
-50
COMPOSITE INPUT TO
COMPONENT OUTPUT
FILTER ENABLED
COMPOSITE INPUT TO
S-VIDEO OUTPUT
FILTER ENABLED
-10
CROSSTALK (dB)
CROSSTALK (dB)
-20
-40
0
COMPOSITE INPUT TO
S-VIDEO OUTPUT
FILTER DISABLED
-10
-30
VA = +5V, VD = +3.3V, RL = 150Ω to GND, TA = +25°C, unless otherwise specified. (Continued)
COMPOSITE INPUT TO
-60 COMPONENT OUTPUT
FILTER DISABLED
-70
1M
10M
FREQUENCY (Hz)
S-VIDEO INPUT TO
COMPONENT OUTPUT
FILTER DISABLED
-40
-50
-60
-70
S-VIDEO INPUT TO
COMPONENT OUTPUT
FILTER ENABLED
-90
0.1M
100M
FIGURE 23. INTRA-CHANNEL CROSSTALK: COMPOSITE TO
COMPONENT/S-VIDEO
-30
CROSSTALK (dB)
BYPASS MODE
-40
36MHz FILTER
ENGAGED
-50
20MHz FILTER
ENGAGED
-60
10MHz FILTER
ENGAGED
-80
-90
0.1M
100M
-20
-30
-70
1M
10M
FREQUENCY (Hz)
FIGURE 24. INTRA-CHANNEL CROSSTALK: S-VIDEO TO
COMPONENT/COMPOSITE
-20
CROSSTALK (dB)
-30
S-VIDEO INPUT TO
COMPOSITE OUTPUT
FILTER DISABLED
-80
-80
-90
0.1M
S-VIDEO INPUT TO
COMPOSITE OUTPUT
FILTER ENABLED
-20
BYPASS MODE
-40
36MHz FILTER
ENGAGED
-50
-60
-70
10MHz FILTER
ENGAGED
20MHz FILTER
ENGAGED
-80
-90
1M
10M
FREQUENCY (Hz)
100M
FIGURE 25. INTRA-CHANNEL CROSSTALK: COMPONENT
INPUT TO COMPOSITE OUTPUT
INPUT = VIDEO + 2Hz SQUARE WAVE
(BEFORE COUPLING CAPACITOR)
TIMEBASE = 500µs/DIV
INPUT: 500mV/DIV
OUTPUT: 1V/DIV
COMPOSITE OR S-VIDEO OUTPUT
-100
0.1M
1M
10M
FREQUENCY (Hz)
100M
FIGURE 26. INTRA-CHANNEL CROSSTALK: COMPONENT
INPUT TO S-VIDEO OUTPUT
INPUT = VIDEO + 2Hz SQUARE WAVE
(BEFORE COUPLING CAPACITOR)
TIMEBASE = 500µs/DIV
INPUT: 500mV/DIV
OUTPUT: 1V/DIV
COMPOSITE OR S-VIDEO OUTPUT
ANY FILTER SETTING
GAIN 2
LOW OFFSET BIT = 1
ANY FILTER SETTING
GAIN 2
LOW OFFSET BIT = 0
FIGURE 27. COMPOSITE/S-VIDEO: CLAMP RESPONSE TO
+250mV STEP ON INPUT (HIGH OFFSET MODE)
19
FIGURE 28. COMPOSITE/S-VIDEO: CLAMP RESPONSE TO
+250mV STEP ON INPUT (LOW OFFSET MODE)
FN7510.0
February 14, 2008
ISL59450
Typical Performance Curves
INPUT = VIDEO + 2Hz SQUARE WAVE
(BEFORE COUPLING CAPACITOR)
VA = +5V, VD = +3.3V, RL = 150Ω to GND, TA = +25°C, unless otherwise specified. (Continued)
INPUT = VIDEO + 2Hz SQUARE WAVE
(BEFORE COUPLING CAPACITOR)
TIMEBASE = 500µs/DIV
INPUT: 500mV/DIV
OUTPUT: 1V/DIV
TIMEBASE = 500µs/DIV
INPUT: 500mV/DIV
OUTPUT: 1V/DIV
YPrPb OUTPUT
YPrPb
ANY FILTER SETTING
GAIN 2
LOW OFFSET BIT = 1
ANY FILTER SETTING
GAIN 2
LOW OFFSET BIT = 0
FIGURE 29. COMPONENT: CLAMP RESPONSE TO +250mV
STEP ON INPUT (HIGH OFFSET MODE)
FIGURE 30. COMPONENT: CLAMP RESPONSE TO +250mV
STEP ON INPUT (LOW OFFSET MODE)
INPUT = VIDEO + 2Hz SQUARE WAVE
(BEFORE COUPLING CAPACITOR)
0
ANY OUTPUT
REJECTION (dB)
-10
ANY OUTPUT
VAC = 200mVP-P
-20
GAIN 2
-30
-40
-50
TIMEBASE = 10Ms/DIV
INPUT: 500mV/DIV
OUTPUT: 1V/DIV
ANY FILTER SETTING
GAIN 2
-60
GAIN 1
1k
FIGURE 31. PULL-DOWN CURRENT RESPONSE
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 32. PSRR vs FREQUENCY
POWER DISSIPATION (W)
4.0
3.5
3.0
2.5
2.0
128 LD MQFP
1.5
θJA = +27.84°C/W
1.0
0.5
0
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
AMBIENT TEMPERATURE (°C)
FIGURE 33. PACKAGE POWER DISSIPATION
20
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February 14, 2008
ISL59450
Functional Description
Signal Muxes
The ISL59450 accepts 6 composite, 4 S-video and 4
component video sources. Each signal type is routed into a
crosspoint mux with two outputs. The 6 composite signals
are routed into a 6:2 mux, the S-video inputs are routed into
a double 4:2 mux and the component video signals are
routed into a triple 4:2 mux. Each mux is controlled through
the I2C interface.
Each signal type has two dedicated outputs, A and B. Signal
types cannot be routed to different signal type outputs. For
example, an S-video signal (Y, C) cannot be routed to the
composite outputs.
For the luma (Y and CVBS) channels, the DC-restore
function is either a standard sync-tip clamp (Master Mode) or
slaved to a clamp signal generated from the sync separator
(Slave Mode).
For the chroma (C and Pr/Pb) channels, the DC-restore
function is a keyed clamp timed to the luma channel (Master
Mode) or timed to a clamp signal generated from the sync
separator (Slave Mode).
The clamping circuit restores the AC-coupled video signal to
a fixed DC level (VTIP, or VLUMA). The clamping circuit
provides line-by-line restoration of the video sync level to a
the selected DC reference voltage during the sync tip.
Clamp Modes
mode) driven off the sync separator. The clamps for the
chroma channels (C/Pr/Pb) are keyed clamps timed to either
the luma (master mode) or the sync separator (slave mode).
Clamp Disable
The clamp can be disabled for each channel by setting the
appropriate bit high in the Miscellaneous 2 register (0x16).
For the S-video and component channels, additional action
needs to be taken in order to completely disable the clamps.
For S-video, setting the bit in the Miscellaneous 2 register
disables the pull-down 1µA pull-down current for both the
luma and chroma channel along with the clamp pull-up
current for the luma channel. However, it does not disable
the clamp pull-up current for the chroma channel unless the
sync separator for that channel is set to 0x25.
For component, setting the bit in the Miscellaneous 2
register disables the pull-down 1µA pull-down current for all
three channels, along with the clamp pull-up current for the
luma channel. However, it does not disable the clamp pull-up
current for the Pr and Pb channels unless the sync separator
for that channel is set to 0x24.
Low Offset Mode
Setting bit 6 in the Composite and S-Video Channel registers
increases the maximum amount of pull-up clamp current
available from 130µA to 270µA, which slightly reduces the
offset between the reference and the output when the clamp
is enabled.
The ISL59450 has two clamp modes: master and slave. Each
output group can operate in either mode. In master mode, sync
timing is derived directly from the video signal and video levels
are clamped using this internal sync signal. In slave mode,
video sync is derived from the input groups corresponding sync
separator (A or B) or an external source connected to the
corresponding sync separator. In the slave mode, the sync
timing can come from HSYNCIN and VSYNCIN or it can be
derived from the sync timing on the active video on the
composite, S-video, or component channels (see “Sync
Separator Block Diagram” on page 9). In the slave mode,
clamping occurs during the sync tip of the selected video signal
or the HSYNC signal (external HSYNC input).
For the component channels, this setting can be enabled by
setting Bit 7 in the Miscellaneous 2 register for Channel A and
Bit 3 for Channel B. This mode increases the maximum amount
of pull-up clamp current available from 270µA to 500µA.
GAIN 1
GAIN 2
GAIN 1
GAIN 2
Filters
Composite
VTIP
VTIP
VLUMAx1
VLUMAx2
The ISL59450 has integrated anti-aliasing/smoothing filters
for SD and HD video signals. For the Composite Video
signals, the user can use a 7MHz low pass filter or bypass it
(40MHz bandwidth). S-video signals have an 10MHz filter
with bypass (43MHz). Component Video signals have a
user-selectable 36MHz, 20MHz, or 10MHz filter, or bypass
(275MHz). All filters selections are made via the I2C host
interface.
S-Video
Luma
VTIP
VTIP
VLUMAx1
VLUMAx2
Clamps
References
Table 1 shows the references used for clamping depending
on the mode and video input being used. VSLICE should
usually be set to 70mV to 100mV above the selected
reference level for luma.
TABLE 1. CHANNEL REFERENCE LEVELS
VIDEO
OUTPUT
S-Video
Chroma
MASTER MODE
SLAVE MODE
VCHROMAx1 VCHROMAx2 VCHROMAx1 VCHROMAx2
Component:
Luma/Green
(YPrPb Mode)
VTIP
VTIP
VLUMAx1
VLUMAx2
Component:
Luma/Green
(RGB Mode)
VTIP
VTIP
VLUMAx1
VLUMAx2
The clamps for all the luma and composite channels can be
sync tip clamps (master mode) or timed keyed clamps (slave
21
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February 14, 2008
ISL59450
TABLE 1. CHANNEL REFERENCE LEVELS (Continued)
VIDEO
OUTPUT
MASTER MODE
GAIN 1
GAIN 2
SLAVE MODE
GAIN 1
GAIN 2
VCHROMAx1 VCHROMAx2 VCHROMAx1 VCHROMAx2
Component:
Pr/Pb
(YPrPb Mode)
Component:
Pr/Pb
(RGB Mode)
VLUMAx1
VLUMAx2
VLUMAx1
VLUMAx2
Bypass each reference voltage with a 0.01µF capacitor to
ground to reduce noise injection.
TABLE 2. SUGGESTED REFERENCE LEVELS
low for longer than the vertical sync default delay time. The
horizontal output gives horizontal timing with pre/post
equalizing pulses.
The use of two sync separators allows the user to send
independent sync information for two signals to downstream
devices. An example would be two video decoders or two
ADCs that are used in a picture-in-picture application. Each
sync separator is dedicated to its respective channel, Sync
Separator A for Channel A and Sync Separator B for
Channel B. It is important to note that the syncs for each
channel cannot be MUXed onto the other channel. For
example, HSYNCINA and VSYNCINA cannot be MUXed to
HSYNCOUTB and VSYNCOUTB.
REFERENCE
VOLTAGE
(V)
VTIPINA
0.5
VTIPINB
0.5
VLUMAx1INA
0.5
VLUMAx2INA
0.5
VLUMAx1INB
0.5
VLUMAx2INB
0.5
VCHROMAx1INA
1
VCHROMAx2INA
1
VCHROMAx1INB
1
A low-going Vertical Sync pulse is output during the start of
the vertical cycle of the incoming video signal. The vertical
cycle starts with a pre-equalizing phase of pulses with a duty
cycle of about 93%, followed by a vertical serration phase
that has a duty cycle of about 15%. Vertical Sync is clocked
out of the ISL59450 on the first rising edge during the
vertical serration phase. In the absence of vertical serration
pulses, a vertical sync pulse will be forced out after the
vertical sync default delay time, approximately 60µs after the
last falling edge of the vertical equalizing phase.
VCHROMAx2INB
1
HORIZONTAL SYNC
VSLICEINA
0.6
VSLICEINB
0.6
Outputs/Levels
Each signal output has a selectable gain of 0dB (GAIN 1) or
6dB (GAIN 2).
The input to the sync separators can be any of the video
inputs, as shown in the “Sync Separator Block Diagram” on
page 9. The HSYNC and VSYNC inputs are dedicated to
their respective sync separator (i.e. Sync Separator A can
connect to HSYNCINA and VSYNCINA, but not HSYNCINB
and VSYNCINB).
Sync Separators
The ISL59450 contains two high performance video sync
separators that automatically lock to any SD and HD video
signal. They will also extract sync timing information from
non-standard video inputs and in the presence of
Macrovision pulses. Composite sync, vertical sync and
horizontal sync outputs are provided from each sync
separator. Timing is adjusted automatically for various video
standards. The composite sync output follows video in sync
pulses and a vertical sync pulse is output on the rising edge
of the first vertical serration following the vertical
pre-equalizing string. For non-standard vertical inputs, a
default vertical pulse is output when the vertical signal stays
22
See the “Sync Separator Timing Diagrams” beginning on
page 32 for typical horizontal and vertical sync output timing.
VERTICAL SYNC
The horizontal circuit senses the composite sync edges and
produces the true horizontal pulses of nominal width 5µs for
standard definition NTSC signals. The pulse width of the
HSYNC output changes as the line frequency of the input
signal changes. For example, an NTSC input generates an
HSYNCOUT with a pulse width of 5µs; while a 720p HD
video input generates an HSYNCOUT with a pulse width of
1.9µs. The leading edge is triggered from the leading edge
of the input HSYNC with the same propagation delay as
composite sync. The half line pulses present in the input
signal during vertical blanking are removed with an internal
2H line eliminator circuit. This is a circuit that inhibits
horizontal output pulses until 75% of the line time is reached,
then the horizontal output operation is enabled again. Any
signals present on the I/P signal after the true H sync will be
ignored, thus the horizontal output will not be effected by
MacroVision copy protection. When there is a loss of sync,
the Horizontal Sync output is held high.
CSET
Connect external capacitors from CSETA and CSETB to
ground. The CSET capacitor should be a X7R grade or better
as the Y5U general use capacitors may be too leaky and
cause faulty operation. The CSET capacitor should be very
close to the CSETA and CSETB pins to reduce possible
board leakage. 56nF is recommended. The CSET capacitor
rectifies a 5µs pulse current and creates a voltage on CSET.
FN7510.0
February 14, 2008
ISL59450
The CSET voltage is converted to bias current for HSYNC
and VSYNC timing.
Internal Control Registers
The ISL59450 is initialized and controlled by a set of internal
registers that define the operating parameters of the entire
device. Communication is established between the external
controller and the ISL59450 through a standard I2C host port
interface, as described earlier. The Register Listing table on
page 24 describes all of these registers. Detailed I2C
programming information for each register is described in
“ISL59450 Serial Communications” on page 33.
Note: Do not write to reserved registers. Reserved bits in
any register should be written with 0s, unless otherwise
noted.
INITIALIZATION
It is recommended that the registers are initialized to 0x00 by
toggling the Reset pin low after powering the device. Once
the registers are initialized, set bit 0 of Miscellaneous
Register 1 to one to engage the global enable and allow the
various channels to be powered up.
Logic Control Signals
Reset is a 5V digital Input, with 3.5V logic threshold and a
300k pull-down. Tie to +5V for normal operation. Taking
Reset to 0V and back to 5V initializes all data registers to
0x00.
Power-down is a digital input with 300k pull-down. When this
pin is taken high, all analog circuitry is disabled to minimize
power consumption. In Power-down mode, the outputs are
tri-stated while the I2C interface remains active and all
register data is retained.
Layout Issues
• Match channel-to-channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches for S-video and component traces.
• All signal I/O lines should be routed over continuous
ground planes (i.e. no split planes or PCB gaps under
these lines).
• Put the proper termination resistors as close to the device
as possible.
• When testing, use high quality connectors and cables,
matching cable types and keep cable lengths to a
minimum.
• Decouple well using a minimum of 2 power supply
decoupling capacitors (1000pF, 0.01µF), placed as close
to the devices as possible. Vias between the capacitor and
the device add unwanted inductance. Larger capacitors
can be farther away.
Power Dissipation
With the high output drive capability of the ISL59450, it is
possible to exceed the +125°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for an application to determine if load conditions
or package types need to be modified to assure operation of
the amplifier in a safe operating area.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
T JMAX – T AMAX
PD MAX = --------------------------------------------θ JA
Where:
Crosstalk Issues
TJMAX = Maximum junction temperature
Do not set any one input to both A and B channels if the
references and modes for A and B are different. For
example, do not send CVIN0 to both CVOUTA and CVOUTB
if the references for Channel A and Channel B are different
or if one channel is in slave mode while the other is in master
mode. This could cause clamping conflicts and compromise
performance.
TAMAX = Maximum ambient temperature
Use the lowest bandwidth setting suitable for each
application to minimize noise, aliasing, and crosstalk. See
“Typical Application Curves” on page 19 and page 19.
(EQ. 1)
θJA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
for sourcing use Equation 2:
V OUT
PD MAX = V S × I SMAX + ( V S – V OUT ) × ---------------RL
(EQ. 2)
for sinking use Equation 3:
PD MAX = V S × I SMAX + ( V OUT – V S ) × I LOAD
(EQ. 3)
Where:
VS = Supply voltage
ISMAX = Maximum quiescent supply current
VOUT = Maximum output voltage of the application
RLOAD = Load resistance tied to ground
ILOAD = Load current
23
FN7510.0
February 14, 2008
ISL59450
Register Listings
DATA
GREY = READ ONLY, WHITE = READ/WRITE
ISL59450 I2C CONTROL MAP
I2 C
ADDR.
FUNCTION
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0x00
Sync Separator A
Sync
Output
Polarity
Reserved
Set to 0
Enable
Reserved
Set to 0
Sync Input
Polarity
Sync Type
Input
Select b1
Input
Select b0
0x01
Sync Separator B
Sync
Output
Polarity
Reserved
Set to 0
Enable
Reserved
Set to 0
Sync Input
Polarity
Sync Type
Input
Select b1
Input
Select b0
0x02
Composite Output A
Slave
Mode A
Low Offset
Mode
Enable
Output
Amplifier
Gain
Filter
Disable
Input
Select b2
Input
Select b1
Input
Select b0
0x03
Composite Output B
Slave
Mode B
Low Offset
Mode
Enable
Output
Amplifier
Gain
Filter
Disable
Input
Select b2
Input
Select b1
Input
Select b0
0x04
S-Video Output Group A
Slave
Mode A
Low Offset
Mode
Enable
Output
Amplifier
Gain
Filter
Disable
Reserved
Set to 0
Input
Select b1
Input
Select b0
0x05
S-Video Output Group B
Slave
Mode B
Low Offset
Mode
Enable
Output
Amplifier
Gain
Filter
Disable
Reserved
Set to 0
Input
Select b1
Input
Select b0
0x06
Component Video
Output Group A
Slave
Mode A
RGB
Mode
Enable
Output
Amplifier
Gain
Filter b1
Filter b0
Input
Select b1
Input
Select b0
0x07
Component Video
Output Group B
Slave
Mode B
RGB
Mode
Enable
Output
Amplifier
Gain
Filter b1
Filter b0
Input
Select b1
Input
Select b0
0
0
0
0
0
0
0
0
0x08 0x13
Reserved Ignore the
contents of and do not
write to these registers.
0x14
Miscellaneous 1 S-Video
Connected. Field Invert
Enable allows Field output
signal to be inverted when
"Sync Output Polarity" bit
is set. Global Enable: 0:
Low power standby mode
with outputs in highimpedance state, 1:
Powers up all internal
reference
S-Video 3
Connected
S-Video 2
Connected
S-Video 1
Connected
S-Video 0
Connected
Reserved
Set to 0
Reserved
Set to 0
Field Invert
Enable
Global
Enable
0x15
Reserved Ignore the
contents of and do not
write to these registers.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x16
Miscellaneous 2
Disable
S-Video A
Clamp
Disable
Component
Disable
Component
B Low
Composite
B Clamp
Offset
A Clamp
Mode
Disable
S-Video B
Clamp
Disable
Composite
B Clamp
Disable
Component
Component
A Low
A Clamp
Offset
Mode
24
FN7510.0
February 14, 2008
ISL59450
Register Descriptions
ADDRESS
0x00
REGISTER
Sync Separator A
25
BIT(S)
1:0
FUNCTION NAME
DESCRIPTION
Input Select A
Chooses the sync source for Sync Separator A to
process. Use these bits in conjunction with the Sync
Type bit directly below.
00: Component SOG (Channel A)
01: S-Video SOG (Channel A)
10: Composite SOG (Channel A)
11: External H and V or CSYNC on H (Channel A)
2
Sync Type A
This bit must be set to the type of incoming sync. For all
SOG or CSYNC signals, this bit should be set.
0: HSYNC is on HSYNCA, VSYNC is on VSYNCA
1: SOG or CSYNC on HSYNCA
3
Sync Input Polarity A
This bit must be set depending on the polarity of the
incoming sync.
0: SOG and active low external HSYNC/CSYNC.
1: Active high external, HSYNC/CSYNC signal.
This forces the internal polarity of the HSYNC signal to
be correct for clamping. Please note setting this bit also
inverts the polarity of HsyncA and VsyncA outputs. See
“Typical Register Settings” on page 31 for correct
values.
4
Reserved
Set this bit to 0.
5
Enable A
0: Sync Separator A is disabled
1: Sync Separator A is enabled
6
Reserved
Set this bit to 0.
7
Sync Output Polarity A
Polarity of HsyncA and VsyncA outputs
0: Active Low
1: Active High
Note: If the Field Invert Enable bit (register 0x14b1) is
set, FieldA’s output will also be inverted when this bit is
set.
FN7510.0
February 14, 2008
ISL59450
Register Descriptions (Continued)
ADDRESS
0x01
0x02
REGISTER
Sync Separator B
Composite Channel A
26
BIT(S)
1:0
FUNCTION NAME
DESCRIPTION
Input Select B
Chooses the sync source for Sync Separator B to
process. Use these bits in conjunction with the Sync
Type bit directly below.
00: Component SOG (Channel B)
01: S-Video SOG (Channel B)
10: Composite SOG (Channel B)
11: External H and V or CSYNC on H (Channel B)
2
Sync Type B
This bit must be set to the type of incoming sync. For all
SOG or CSYNC signals, this bit should be set.
0: HSYNC is on HSYNCB, VSYNC is on VSYNCB
1: SOG or CSYNC on HSYNCB
3
Sync Input Polarity B
This bit must be set depending on the polarity of the
incoming sync.
0: SOG and active low external HSYNC/CSYNC.
1: Active high external, HSYNC/CSYNC signal.
This forces the internal polarity of the HSYNC signal to
be correct for clamping. Please note setting this bit also
inverts the polarity of HsyncB and VsyncB outputs. See
“Typical Register Settings” on page 31 for correct
values.
4
Reserved
Set this bit to 0.
5
Enable B
0: Sync Separator B is disabled
1: Sync Separator B is enabled
6
Reserved
Set this bit to 0.
7
Sync Output Polarity B
Polarity of HsyncB and VsyncB outputs
0: Active Low
1: Active High
Note: If the Field Invert Enable bit (register 0x14b1) is
set, FieldB’s output will also be inverted when this bit is
set.
2:0
Input Select A
0: CVBSIN0
1: CVBSIN1
2: CVBSIN2
3: CVBSIN3
4: CVBSIN4
5: CVBSIN5
3
Filter Disable A
0: 7MHz Smoothing Filter
1: Smoothing Filter bypassed (40MHz bandwidth)
4
Output Amplifier Gain A 0: x1
1: x2
5
Enable A
0: Disables (High-Z) Composite A output
1: Enables Composite output A
6
Low Offset Mode A
0: Normal Mode
1: Low Offset Mode
Slightly lowers the DC offset from input to output by
increasing the maximum amount of clamp restore
current from 130µA to 270µA.
7
Slave Mode A
0: Sync tip DC-restore on selected channel (master
mode)
1: DC-restore clamp timing slaved to Sync Separator A
(slave mode)
FN7510.0
February 14, 2008
ISL59450
Register Descriptions (Continued)
ADDRESS
0x03
0x04
REGISTER
Composite Channel B
S-Video Channel A
27
BIT(S)
FUNCTION NAME
DESCRIPTION
2:0
Input Select B
0: CVBSIN0
1: CVBSIN1
2: CVBSIN2
3: CVBSIN3
4: CVBSIN4
5: CVBSIN5
3
Filter Disable B
0: 7MHz Smoothing Filter
1: Smoothing Filter bypassed (40MHz bandwidth)
4
Output Amplifier Gain B 0: x1
1: x2
5
Enable B
0: Disables (High-Z) Composite B output
1: Enables Composite output B
6
Low Offset Mode B
0: Normal Mode
1: Low Offset Mode
Slightly lowers the DC offset from input to output by
increasing the maximum amount of clamp restore
current from 130µA to 270µA.
7
Slave Mode B
0: Sync tip DC-restore on selected channel (master
mode)
1: DC-restore clamp timing slaved to Sync Separator B
(slave mode)
1:0
Input Select A
0: SvideoIN0
1: SvideoIN1
2: SvideoIN2
3: SvideoIN3
2
Reserved
Set this bit to 0
3
Filter Disable A
0: 10MHz Smoothing Filter
1: Smoothing Filter bypassed (40MHz bandwidth)
4
Output Amplifier Gain A 0: x1
1: x2
5
Enable A
0: Disables (High-Z) S-Video A outputs
1: Enables S-Video A outputs
6
Low Offset Mode A
0: Normal Mode
1: Low Offset Mode
Slightly lowers the DC offset of the output by increasing
the maximum amount of clamp restore current from
130µA to 270µA.
7
Slave Mode A
0: Sync tip DC-restore on selected channel (master
mode)
1: DC-restore clamp timing slaved to Sync Separator A
(slave mode)
FN7510.0
February 14, 2008
ISL59450
Register Descriptions (Continued)
ADDRESS
0x05
0x06
REGISTER
S-Video Channel B
Component Channel A
28
BIT(S)
1:0
FUNCTION NAME
DESCRIPTION
Input Select B
0: SvideoIN0
1: SvideoIN1
2: SvideoIN2
3: SvideoIN3
2
Reserved
Set this bit to 0
3
Filter Disable B
0: 10MHz Smoothing Filter
1: Smoothing Filter bypassed (40MHz bandwidth)
4
Output Amplifier Gain B 0: x1
1: x2
5
Enable B
0: Disables (High-Z) S-Video B outputs
1: Enables S-Video B outputs
6
Low Offset Mode B
0: Normal Mode
1: Low Offset Mode
Slightly lowers the DC offset of the output by increasing
the maximum amount of clamp restore current from
130µA to 270µA.
7
Slave Mode B
0: Sync tip DC-restore on selected channel (master
mode)
1: DC-restore clamp timing slaved to Sync Separator B
(slave mode)
1:0
Input Select A
0: YPbPrIN0
1: YPbPrIN1
2: YPbPrIN2
3: YPbPrIN3
3:2
Filter Select A
0: 10MHz Smoothing FIlter
1: 20MHz Smoothing FIlter
2: 36MHz Smoothing Filter
3: Smoothing Filter Bypassed (250MHz bandwidth)
4
Output Amplifier Gain A 0: x1
1: x2
5
Enable A
0: Disables (High-Z) Component A outputs
1: Enables Component A outputs
6
RGB Mode A
0: YPbPr Mode
Y clamps to VTIPINA (master mode)
Y clamps to VLUMAx1/2INA (slave mode)
Pb/Pr clamps to VCHROMAx1/2INA
1: RGB Mode
Y clamps to VTIPINA (master mode)
Y clamps to VLUMAx1/2INA (slave mode)
Pb/Pr clamps to VLUMAx1/2INA
7
Slave Mode A
0: Sync tip DC-restore on selected channel (master
mode)
1: DC-restore clamp timing slaved to Sync Separator A
(slave mode)
FN7510.0
February 14, 2008
ISL59450
Register Descriptions (Continued)
ADDRESS
0x07
REGISTER
Component Channel B
BIT(S)
FUNCTION NAME
DESCRIPTION
1:0
Input Select B
0: YPbPrIN0
1: YPbPrIN1
2: YPbPrIN2
3: YPbPrIN3
3:2
Filter Select B
0: 10MHz Smoothing Filter
1: 20MHz Smoothing Filter
2: 36MHz Smoothing Filter
3: Smoothing Filter Bypassed (250MHz bandwidth)
4
Output Amplifier Gain B 0: x1
1: x2
5
Enable B
0: Disables (High-Z) Component B outputs
1: Enables Component B outputs
6
RGB Mode B
0: YPbPr Mode
Y clamps to VTIPINB (master mode)
Y clamps to VLUMAx1/2INB (slave mode)
Pb/Pr clamps to VCHROMAx1/2INB
1: RGB Mode
Y clamps to VTIPINB (master mode)
Y clamps to VLUMAx1/2INB (slave mode)
Pb/Pr clamps to VLUMAx1/2INB
7
Slave Mode B
0: Sync tip DC-restore on selected channel (master
mode)
1: DC-restore clamp timing slaved to Sync Separator B
(slave mode)
0x08-0x0B
Reserved (Read only)
7:0
Reserved
Reserved
0x0C-0x0D
Reserved
7:0
Reserved
Write 0x00 to these registers
0x0E-0x11
Reserved (Read only)
7:0
Reserved
Reserved
0x12-0x13
Reserved
7:0
Reserved
Write 0x00 to these registers
0
Global Enable
0: All outputs disabled
1: Outputs enabled per their individual Enable settings
1
Field Invert Enable
0: The Sync Output Polarity bit (Sync Separator) does
not affect Field polarity.
1: The Sync Output Polarity bit (Sync Separator) inverts
the Field output.
2
Reserved
Set this bit to 0
3
Reserved
Set this bit to 0
4
S-Video 0 Connected
0: Cable plugged in to S-Video Channel 0
1: Nothing plugged in to S-Video Channel 0
5
S-Video 1 Connected
0: Cable plugged in to S-Video Channel 1
1: Nothing plugged in to S-Video Channel 1
6
S-Video 2 Connected
0: Cable plugged in to S-Video Channel 2
1: Nothing plugged in to S-Video Channel 2
7
S-Video 3 Connected
0: Cable plugged in to S-Video Channel 3
1: Nothing plugged in to S-Video Channel 3
Reserved
Reserved
0x14
0x15
Miscellaneous 1
(Bits 4 thru 7 are read-only)
Reserved
7:0
29
FN7510.0
February 14, 2008
ISL59450
Register Descriptions (Continued)
ADDRESS
0x16
REGISTER
Miscellaneous 2
BIT(S)
FUNCTION NAME
DESCRIPTION
0
Disable Composite B
Clamp
This bit disables the DC-restore clamp for composite
Channel B.
0: Composite A clamp enabled
1: Composite A clamp disabled
1
Disable S-Video B
Clamp
This bit disables the DC-restore clamp for the luma (Y)
of S-Video Channel B.
Disables the 1µA pull-down currents for both Y and C.
Does not disable the clamp for chroma channel unless
in Slave mode and Sync Separator. B = 0x25.
0: S-Video A clamp enabled
1: S-Video A clamp disabled
2
Disable Component B
Clamp
This bit disables the DC-restore clamp for Y/G of
component Channel B.
Disables the 1µA pull-down currents for ALL three
channels.
Does not disable the pull-up clamp for Pr/R and Pb/B
unless in Slave mode AND Sync Separator. B = 0x24.
0: Y Component A clamp enabled
1: Y Component A clamp disabled
3
Component B Low
Offset Mode
0: Normal operation
1: DC-restore clamp has a lower offset.
Slightly lowers the DC offset of the component outputs
by increasing the maximum amount of clamp restore
current from 250µA to 500µA.
4
Disable Composite A
Clamp
This bit disables the DC-restore clamp for composite
Channel A
0: Composite A clamp enabled
1: Composite A clamp disabled
5
Disable S-Video A
Clamp
This bit disables the DC-restore clamp for the luma (Y)
of S-Video Channel A.
Disables the 1µA pull-down currents for both Y and C.
Does not disable the clamp for chroma channel unless
in Slave mode and Sync Separator. A = 0x25.
0: S-Video A clamp enabled
1: S-Video A clamp disabled
6
Disable Component A
Clamp
This bit disables the DC-restore clamp for Y/G of
component Channel A.
Disables the 1µA pull-down currents for ALL three
channels.
Does not disable the clamps for Pr/R and Pb/B unless
in Slave mode AND Sync Separator. A = 0x24.
0: Y Component A clamp enabled
1: Y Component A clamp disabled
7
30
Component A Low
Offset Mode
0: Normal operation
1: DC-restore clamp has a lower offset.
Slightly lowers the DC offset of the component outputs
by increasing the maximum amount of clamp restore
current from 250µA to 500µA.
FN7510.0
February 14, 2008
ISL59450
Typical Register Settings
REGISTER
SETTINGS
VIDEO TYPE
CHANNEL A
REGISTER
ADDRESS
CHANNEL B
REGISTER
ADDRESS
CHANNEL
REGISTER VALUE
SYNC SEPARATOR
REGISTER VALUE
For all settings, Miscellaneous 1 Register (0x14) = 0xX1 and Miscellaneous 2 (0x16) = 0x00.
Composite 0
Composite
0x02
0x03
0x30
0x00
Composite 1
Composite
0x02
0x03
0x31
0x00
Composite 2
Composite
0x02
0x03
0x32
0x00
Composite 3
Composite
0x02
0x03
0x33
0x00
Composite 4
Composite
0x02
0x03
0x34
0x00
Composite 5
Composite
0x02
0x03
0x35
0x00
S-Video 1
S-Video
0x04
0x05
0x30
0x00
S-Video 2
S-Video
0x04
0x05
0x31
0x00
S-Video 3
S-Video
0x04
0x05
0x32
0x00
S-Video 4
S-Video
0x04
0x05
0x33
0x00
Component 0
Component
0x06
0x07
0x3C
0x00
RGB + HV
0x06
0x07
0xFC
0x23 (active low sync in)
0xAB (active high sync in)
Component
0x06
0x07
0x3D
0x00
RGB + HV
0x06
0x07
0xFD
0x23 (active low sync in)
0xAB (active high sync in)
Component
0x06
0x07
0x3E
0x00
RGB + HV
0x06
0x07
0xFE
0x23 (active low sync in)
0xAB (active high sync in)
Component
0x06
0x07
0x3F
0x00
RGB+HV
0x06
0x07
0xFF
0x23 (active low sync in)
0xAB (active high sync in)
Component 1
Component 2
Component 3
31
FN7510.0
February 14, 2008
ISL59450
Sync Separator NTSC Vertical Timing
SIGNAL 1a. COMPOSITE VIDEO INPUT, FIELD ONE
1.5µs ±0.1µs
TIME
VERTICAL BLANKING INTERVAL = 20H
3H
H SYNC
INTERVAL
H
2
3H
3H
3
4
START OF
H
FIELD ONE
PREEQUALIZING
PULSE INTERVAL
H
1
5
+H
+63.5µs
1271µs
-H
-0µs
6
7
8
9
10
0.5H
VERTICAL SYNC
PULSE INTERVAL
POSTEQUALIZING
PULSE INTERVAL
9 LINE VERTICAL INTERVAL
19
20
21
H
REF SUBCARRIER PHASE,
COLOR FIELD ONE
SIGNAL 1b. VERTICAL SYNC OUTPUT
280µs
SIGNAL 1c. HORIZONTAL SYNC OUTPUT
NOTES:
2. The composite sync output reproduces all the video input sync pulses, with a propagation delay.
3. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge with a propagation delay.
4. Horizontal sync output produces the true “H” pulses of nominal width of 5µs. It has the same delay as the composite sync.
Sync Separator NTSC Horizontal Timing
CONDITIONS: VD = 3.3V, TA = +25°C
WHITE LEVEL
COLOR BURST
INPUT
DYNAMIC
RANGE
0.5V TO 2V
VIDEO
SYNC LEVEL
SYNC IN
VSLICE
50%
SYNC
TIP
HOUT
VBLANK
(BLANKING LEVEL
VOLTAGE)
SYNC
VSYNC
(SYNC TIP
VOLTAGE)
tdHOUT
tHOUT
32
FN7510.0
February 14, 2008
ISL59450
PARAMETER
DESCRIPTION
tdHOUT
HOUT Timing Relative to Input
tHOUT
Horizontal Output Width
CONDITIONS
TYP
UNIT
200
ns
5
µs
TYP
@ 3.3V
UNIT
90
ns
1.90
µs
Sync Separator HSYNC Timing for 720p
CONDITIONS: VD = 3.3V TA = +25°C
SYNCIN
HOUT
tdHOUT
tHOUT
PARAMETER
DESCRIPTION
tdHOUT
HOUT Timing Relative to Input
tHOUT
Horizontal Output Width
ISL59450 Serial Communications
I2C Overview
The ISL59450 uses a 2-wire I2C serial bus for
communication with its host. SCL is the Serial Clock line,
driven by the host, and SDA is the Serial Data line, which
can be driven by all devices on the bus. SDA is open drain to
allow multiple devices to share the same bus
simultaneously.
Communication is accomplished in three steps:
1. The Host selects the ISL59450 with which it wishes to
communicate.
2. The Host writes the initial ISL59450 Configuration
Register address it wishes to write to or read from.
3. The Host writes to or reads from the ISL59450’s
Configuration Register. The ISL59450’s internal address
pointer auto increments, so to read registers 0x00
through 0x16, for example, one would write 0x00 in step
two, then repeat step four 28 times, with each read
returning the next register value.
The ISL59450 has a 7-bit address on the serial bus. The upper
6-bits are permanently set to 100010x, with the x determined by
the state of the Address pin (Table 3). This allows two
33
CONDITIONS
ISL59450s to be independently controlled while sharing the
same bus. The Address pin has an internal pull-down resistor
to pull the terminal low to set a zero.
TABLE 3. I2C ADDRESS OPTIONS
B7
B6
B5
B4
B3
B2
B1
B0
HEX
A6
(MSB)
A5
A4
A3
A2
A0
A1 (Address) R/W
1
0
0
0
0
1
0
1/0 0x85/0x84
1
0
0
0
0
1
1
1/0 0x87/0x86
The bus is nominally inactive, with SDA and SCL high.
Communication begins when the host issues a START
command by taking SDA low while SCL is high (Figure 34).
The ISL59450 continuously monitors the SDA and SCL lines
for the start condition and will not respond to any command
until this condition has been met. The host then transmits the
7-bit serial address plus a R/W bit, indicating if the next
transaction will be a Read (R/W = 1) or a Write (R/W = 0). If
the address transmitted matches that of any device on the
bus, that device must respond with an ACKNOWLEDGE
(Figure 35).
FN7510.0
February 14, 2008
ISL59450
Once the serial address has been transmitted and
acknowledged, one or more bytes of information can be
written to or read from the slave. Communication with the
selected device in the selected direction (read or write) is
ended by a STOP command, where SDA rises while SCL is
high (Figure 34), or a second START command, which is
commonly used to reverse data direction without
relinquishing the bus.
Data on the serial bus must be valid for the entire time SCL
is high (Figure 36). To achieve this, data being written to the
ISL59450 is latched on a delayed version of the rising edge
of SCL. SCL is delayed and de-glitched inside the ISL59450
for three crystal clock periods (120ns for a 25MHz crystal) to
eliminate spurious clock pulses that could disrupt serial
communication.
When the contents of the ISL59450 are being read, the SDA
line is updated after the falling edge of SCL, delayed and
de-glitched in the same manner.
Configuration Register Write
Figure 37 shows two views of the steps necessary to write
one or more words to the Configuration Register.
Configuration Register Read
Figure 38 shows two views of the steps necessary to read
one or more words from the Configuration Register.
SCL
SDA
START
STOP
FIGURE 34. VALID START AND STOP CONDITIONS
SCL FROM
HOST
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 35. ACKNOWLEDGE RESPONSE FROM RECEIVER
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 36. VALID DATA CHANGES ON THE SDA BUS
34
FN7510.0
February 14, 2008
ISL59450
Signals the beginning of serial I/O
START Command
ISL59450 Serial Address
R/W
1
0
0
0
0
1
Addr
0
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
ISL59450 Device Select Address Write
The first 7 bits of the first byte select the ISL59450 on the 2-wire
bus at the address set by the Address pin. R/W = 0, indicating
the next transaction will be a write.
ISL59450 Register Address Write
This is the address of the ISL59450’s configuration register that
the following byte will be written to.
ISL59450 Register Data Write(s)
This is the data to be written to the ISL59450’s configuration register.
Note: The ISL59450’s Configuration Register’s address pointer auto
increments after each data write. Repeat this step to write multiple
sequential bytes of data to the Configuration Register.
(Repeat if desired)
Signals the ending of serial I/O
STOP Command
Signals from
the Host
SDA Bus
Signals from
the ISL59450
S
T Serial Bus
A
R Address
T
Register
Address
aaaaaaa0
AAAAAAAA
A
C
K
S
T
O
P
Data
Write*
* The data write step may be repeated to write to the
ISL59450’s Configuration Register sequentially, beginning at
the Register Address written in the previous step.
dddddddd
A
C
K
A
C
K
FIGURE 37. CONFIGURATION REGISTER WRITE
35
FN7510.0
February 14, 2008
ISL59450
Signals the beginning of serial I/O
START Command
ISL59450 Serial Bus
R/W
ISL59450 Device Select Address Write
1
1
0
0
0
0
A7
A6
A5
A4
A3
0
A1
A0
This sets the initial address of the ISL59450’s configuration
register for subsequent reading.
Ends the previous transaction and starts a new one
R/W
ISL59450 Serial Bus Address Read
A2
START Command
ISL59450 Serial Bus
1
1
0
0
0
0
D7
D6
D5
D4
D3
The first 7 bits of the first byte select the ISL59450 on the 2-wire
bus at the address set by the Address pin. R/W = 0, indicating
the next transaction will be a write.
ISL59450 Register Address Write
Address
Address
1
D1
D0
This is the 7-bit address of the ISL59450 on the 2-wire bus. The
address is 0x85 if pin 92 is low, 0x87 if pin 92 is high. R/W = 1,
indicating next transaction(s) will be a read.
ISL59450 Register Data Read(s)
D2
Note: The ISL59450’s Configuration Register’s address pointer
auto increments after each data read. Repeat this step to read
multiple sequential bytes of data from the Configuration Register.
Signals the ending of serial I/O
(Repeat if desired)
STOP Command
Signals from
the Host
SDA Bus
Signals from
the ISL59450
S
T Serial Bus
A
R Address
T
R
E
S
T Serial Bus
A Address
R
T
Register
Address
aaaaaaa0
AAAAAAAA
A
C
K
This is the data read from the ISL59450’s configuration register.
Data
Read*
aaaaaaa1
A
C
K
S
T
O
AP
C
K
* The data read step may be repeated to read
from the ISL59450’s Configuration Register
sequentially, beginning at the Register
Address written in the two previous steps.
A dddddddd
C
K
FIGURE 38. CONFIGURATION REGISTER READ
36
FN7510.0
February 14, 2008
ISL59450
Metric Plastic Quad Flatpack Packages (MQFP)
D
MDP0055
D1
128
14x20mm 128 LEAD MQFP (WITH AND WITHOUT HEAT
SPREADER) 3.2mm FOOTPRINT
PIN 1 ID
1
SYMBOL
20.000 ±0.100
(E1)
19.870 ±0.100
18.500 REF
E1 E
12.500 REF
C0.600x0.350
(4X)
13.870 ±0.100
A
1
A
14.000 ±0.100
(D1)
12° ALL
AROUND
Y
b
T1
T
DIMENSIONS
(MILLIMETERS)
REMARKS
A
Max 3.40
A1
0.250~0.500
Overall height
Standoff
A2
2.750 ±0.250
Package thickness
α
0°~7°
Foot angle
b
0.220 ±0.050
Lead width 1
b1
0.200 ±0.030
D
17.200 ±0.250
Lead base metal width 1
Lead tip to tip
D1
14.000 ±0.100
Package length
E
23.200 ±0.250
Lead tip to tip
E1
20.000 ±0.100
Package width
e
0.500 Base
Lead pitch
L
0.880 ±0.150
Foot length
L1
1.600 Ref.
Lead length
T
0.170 ±0.060
T1
0.152 ±0.040
ccc
0.100
Frame thickness 1
Frame base metal thickness 1
Foot coplanarity
ddd
0.100
Foot position
b1
Rev. 2 2/07
1 SECTION A-A
DROP IN HEAT SPREADER
4 STAND POINTS MAY BE EXPOSED
DO NOT TRY TO CONNECT ELECTRICALLY
2.
1 Matte finish on package body surface except ejection and
pin 1 marking (Ra 0.8~2.0um).
3. All molded body sharp corner RADII unless otherwise specified
(Max RO.200).
5. Top/Bottom misalignment (X, Y): Max. 0.127
6. Drawing does not include plastic or metal protrusion or cutting
burr.
0.200 MIN
0° MIN
7.
2 Compliant to JEDEC MS-022.
R0.13 MIN
ccc C
A2
1. General tolerance: Distance ±0.100, Angle +2.5°.
4. Package/Leadframe misalignment (X, Y): Max. 0.127
R0.25 TYP
ALL AROUND
A
NOTES:
0.13~0.30
α
SEATING
PLANE
A1
C
GAUGE
PLANE
0.25 BASE
L
e
L1
b
T
ddd M C
DETAIL Y
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
37
FN7510.0
February 14, 2008
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