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8
8
-8
1
YC (S-video) to Composite Video Driver
with LPF
The ISL59114 is a YC (S-video) reconstruction filter with a
-3dB roll-off frequency of 9MHz and summer amplifier to
create the composite video signal. Operating from a single
supply ranging from +2.5V to +3.6V and drawing only 4.5mA
quiescent current, the ISL59114 is ideally suited for low
power, battery-operated applications. Additionally, an enable
pin shuts the part down in under 14ns.
ISL59114
September 21, 2006
Features
• 3rd order 9MHz reconstruction filter
• 40V/µs slew rate
• Low supply current = 4.5mA
• Maximum Power-down current <0.5µA
• Supplies from 2.5V to 3.6V
• Rail-to-rail output
The ISL59114 is designed to meet the bandwidth and very
low power requirements of battery-operated communication,
instrumentation, and modern industrial applications such as
video on demand, cable set-top boxes, MP3 players, and
HDTV. The ISL59114 is offered in a space-saving µTQFN
Pb-free package guaranteed to a 0.6mm maximum height
constraint and specified for operation from -40°C to +85°C
temperature range.
• µTQFN package
Pinout
• Video on demand
ISL59114
(10 LD ΜTQFN)
TOP VIEW
FN6184.2
• Pb-free plus anneal available (RoHS compliant)
Applications
• Video amplifiers
• Portable and handheld products
• Communications devices
• Cable set-top boxes
• Satellite set-top boxes
• MP3 players
GND
10
• HDTV
• Personal video recorder
YIN
1
9
YOUT
ENCLAMP
2
8
CVBSOUT
CIN
3
7
COUT
Block Diagram
+
65mV
YIN
ENCY
6
4
ENCVBS
9MHz
500mV
- +
x2
YOUT
x2
COUT
x2
CVBSOUT
1uA
65mV
CIN
5
9MHz
- +
ENCY
VDD
+
ENCLAMP
+
65mV
- +
ENCVBS
Ordering Information
PART NUMBER (Note)
ISL59114IRUZ-T7
PART MARKING
FJ
TAPE AND REEL
TEMP. RANGE (°C)
7”
-40 to +85
PACKAGE (Pb-Free)
10 Ld µTQFN
PKG. DWG. #
L10.2.1x1.6A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL59114
Absolute Maximum Ratings (TA = +25°C)
ESD Classification
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage from VDD to GND . . . . . . . . . . . . . . . . . . . . . . . 4.2V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . VDD +0.3V to GND -0.3V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VDD = 3.3V, TA = +25°C, RL = 150 to GND, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
3.6
V
INPUT CHARACTERISTICS
VDD
Supply Voltage Range
2.5
IDD_CY
Quiescent Supply Current - CY Amps
Enabled
VIN = 500mV, ENCY = VDD, ENCVBS = GND,
no load
3.1
4.0
mA
IDD
Quiescent Supply Current
VIN = 500mV, ENCY = ENCVBS = VDD,
no load
4.5
6.0
mA
IDD_OFF
Shutdown Supply Current
ENCY = ENCVBS = 0V
0.1
0.5
µA
VY_CLAMP
Y Input Clamp Voltage
IY = -100µA
-30
-15
10
mV
IY_DOWN
Y input Clamp Discharge Current
VY = 0.5V
0.6
1
1.6
µA
IY_UP
Y Input Clamp Charge Current
VY = -0.1V
-3.4
-3.0
mA
RY
Y Input Resistance
0.5V < VY < 1V
10
VC_CLAMP
C Input Clamp Voltage
VY = 0.05V, IC = 0A
500
550
700
mV
RC
C Input Resistance
VY = 0.05V, 0.25V < VC < 0.75V
2.0
2.5
3.0
k
IC
C Input Bias Current
VY = 0.3V
-200
-2
200
nA
VY_SYNC
Y Input Sync Detect Voltage
100
150
200
mV
VOLS
Output Level Shift Voltage
VIN = 0V, no load
60
130
200
mV
AV_CY
Voltage Gain, C-Y channel
RL = 150
1.95
1.99
2.04
V/V
AV_CVBS
Voltage Gain, CVBS channel
RL = 150
1.93
1.98
2.04
V/V
AV_CY
C-to-Y Channel Gain Mismatch
-1.75
±0.5
1.75
%
AV_CVBS
C/Y-to-CVBS Channel Gain Mismatch
-3
±0.7
3
%
PSRR_CY
DC Power Supply Rejection
VDD = 2.5V to 3.6V
40
60
dB
PSRR_CVBS
DC Power Supply Rejection
VDD = 2.5V to 3.6V
25
35
dB
VOH
Output Voltage High Swing
VIN = 2V, RL = 150 to GND
2.85
3.2
V
ISC
Output Short-Circuit Current
VIN = 2V, to GND through 10
100
145
mA
IENABLE
ENCY, ENCVBS Input Current
0V < VEN < 3.3V
-0.2
0.001
VIL
Disable Threshold
VIH
Enable Threshold
ROUT
Shutdown Output Impedance
+0.2
µA
0.8
V
2.0
EN = 0V, DC
EN = 0V, f = 4.5MHz
2
M
V
5.0
7.5
3.4
k
k
FN6184.2
September 21, 2006
ISL59114
Electrical Specifications
PARAMETER
VDD = 3.3V, TA = +25°C, RL = 150 to GND, unless otherwise specified. (Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW0.1dB
BW3dB
±0.1dB Bandwidth
-3dB Bandwidth
Normalized Stopband Gain
RSOURCE = 75, RL = 150, CL = 5pF
5.6
MHz
RSOURCE = 500, RL = 150, CL = 5pF
3.9
MHz
RSOURCE = 75, RL = 150, CL = 5pF
8.8
MHz
RSOURCE = 500, RL = 150, CL = 5pF
7.8
MHz
f = 27MHz, RSOURCE = 75
-28.5
dB
f = 27MHz, RSOURCE = 500
-30.6
dB
dG
Differential Gain
NTSC and PAL
0.10
%
dP
Differential Phase
NTSC and PAL
0.5
°
D/DT
Group Delay Variation
f = 100kHz, 5MHz
5.4
ns
SNR
Signal to Noise Ratio
100% white signal
65
dB
TON
Enable Time
VIN = 500mV, VOUT to 1%
200
ns
TOFF
Disable Time
VIN = 500mV, VOUT to 1%
14
ns
+SR
Positive Slew Rate
20% to 80%, VIN = 1V step
30
40
50
V/µs
-SR
Negative Slew Rate
80% to 20%, VIN = 1V step
-30
-40
-50
V/µs
tF
Fall Time
2.5VSTEP, 80% - 20%
25
ns
tR
Rise Time
2.5VSTEP, 20% - 80%
22
ns
Connection Diagram
+
Y (luminance)
65mV
YIN
9MHz
0.1uF
500mV
C (chrominance)
S-video cable
x2
YOUT
75
1uA
CIN
0.1uF
ENCLAMP
uC or
tie to 3.3V
- +
ENCY
ENCVBS
65mV
9MHz
- +
x2
COUT
75
+
+
65mV
- +
x2
CVBSOUT
75
YOUT
75
COUT
75
CVBSOUT
75
Note:
ENCLAMP is high for AC coupled inputs (as shown)
ENCLAMP is low for DC coupled inputs
3
FN6184.2
September 21, 2006
ISL59114
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1
YIN
2
ENCLAMP
3
CIN
4
ENCY
5
VDD
6
ENCVBS
7
COUT
8
CVBSOUT
9
YOUT
Luminance output
10
GND
Ground
Luminance input
Enable clamp. Tie high for AC coupled inputs. Tie low for DC coupled inputs.
Chrominance input
Enable chrominance and luminance outputs
Positive power supply
Enable composite video output
Chrominance output
Composite video output
Typical Performance Curves
5
0
-5
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
5
-0.1dB BW @ 5.6MHz
-10
-15
-20
-25
-30
-35
VDD = +3.3V
RL = 150
100k
1M
10M
FREQUENCY RESPONSE (Hz)
-20
-25
-30
VDD = +3.3V
RL = 150
3.0
-1
-2
CL = 100pF
-3
35M
1M
10M
FREQUENCY RESPONSE (Hz)
100k
3.5
0
-4
VDD = +3.3V
RL = 150
FIN = 100kHz
2.5
2.0
1.5
1.0
CL = 10pF
-5
-6
100k
-15
4.0
VOUT (VP-P)
NORMALIZED GAIN (dB)
1
-28dB BW @ 27MHz
-10
FIGURE 2. GAIN vs FREQUENCY -3dB POINT
CL = 470pF
VDD = +3.3V
RL = 150
-3dB BW @ 8.8MHz
-5
-35
25M
FIGURE 1. GAIN vs FREQUENCY -0.1dB
2
0
1M
10M
FREQUENCY RESPONSE (Hz)
0.5
25M
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS CLOAD
4
0.0
0.0
0.5
1.0
1.5
2.0
2.5
VIN (VP-P)
3.0
3.5
4.0
FIGURE 4. MAXIMUM OUTPUT MAGNITUDE vs INPUT
MAGNITUDE
FN6184.2
September 21, 2006
ISL59114
Typical Performance Curves (Continued)
0
270
180
VDD = +3.3V
RL = 150
VDD = +3.3V
-10
GAIN (dB)
PHASE (°)
-20
90
0
-90
-30
-40
-50
-60
-180
-270
100k
-70
1M
10M
FREQUENCY (Hz)
-80
100k
100M
1M
10M
FREQUENCY (Hz)
100M
FIGURE 6. PSRR vs FREQUENCY
FIGURE 5. PHASE vs FREQUENCY
-30
VDD = +3.3V
-40
YIN TO COUT
GAIN (dB)
-50
-60
-70
-80
CIN TO YOUT
-90
-100
100k
SUPPLY CURRENT (mA)
7
6
NO LOAD
NO INPUT
5
4
3
2
1
0
0.0
5
50M
FIGURE 8. ISOLATION vs FREQUENCY
FIGURE 7. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 9. MAXIMUM OUTPUT vs LOAD RESISTANCE
1M
10M
FREQUENCY (Hz)
0.5
1.0
1.5
2.0
2.5
3.0
SUPPLY VOLTAGE (V)
3.5
4.0
FIGURE 10. SUPPLY CURRENT vs SUPPLY VOLTAGE
FN6184.2
September 21, 2006
ISL59114
3.5
3.6
3.0
3.0
2.5
AMPLITUDE (V)
AMPLITUDE (V)
Typical Performance Curves (Continued)
VDD = +3.3V
RL = 150
VOUT = 2.5VP-P
2.0
1.5
TRISE = 26.4ns
1.0
0.5
0
2.4
1.8
POSITIVE SLEW
RATE = 41.1V/µs
1.2
NEGATIVE SLEW
RATE = -40.8V/µs
0.6
TFALL = 26.9ns
0.0
-120 -60
VDD = +3.3V
RL = 150
VOUT = 1VP-P
0.0
-60
60 120 180 240 300 360 420 480 540
TIME (ns)
3.0
VDD = +3.3V
RL = 150
2.0
1.0
0.5
0.0
30
60
90 120
TIME (ns)
150
180
210
OUTPUT SIGNAL
-10
0
10
TIME (ns)
20
30
40
FIGURE 14. DISABLE TIME
-30
THD
VDD = +3.3V
RL = 150
VOUT = 2VP-P
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
480
0.5
-0.5
-20
-20
-40
-50
-60
3rd HD
-70
-80
420
1.0
FIGURE 13. ENABLE TIME
-30
360
1.5
0.0
0
300
2.0
OUTPUT SIGNAL
-30
180 240
TIME (ns)
DISABLE SIGNAL
ENABLE SIGNAL
1.5
-0.5
-60
120
VDD = +3.3V
RL = 150
2.5
AMPLITUDE (V)
AMPLITUDE (V)
2.5
60
FIGURE 12. SLEW RATE
FIGURE 11. LARGE SIGNAL STEP RESPONSE
3.0
0
2nd HD
1M
10M
FREQUENCY (Hz)
FIGURE 15. HARMONIC DISTORTION vs FREQUENCY
6
-40
THD
-50
-60
3rd HD
-70
2nd HD
-80
0.5
1.0
1.5
2.0
2.5
OUTPUT VOLTAGE (VP-P)
3.0
FIGURE 16. HARMONIC DISTORTION vs OUTPUT VOLTAGE
FN6184.2
September 21, 2006
ISL59114
Typical Performance Curves (Continued)
16
-3dB BANDWIDTH (MHz)
VDD = +3.3V
RL = 150
VDD = +3.3V
RL = 150
14
12
10
8
6
4
2
80
140
200
260
320
380
440
500
INPUT RESISTANCE ()
FIGURE 18. -3dB BANDWIDTH vs INPUT RESISTANCE
FIGURE 17. GROUP DELAY vs FREQUENCY
44
VIN = 1VP-P
RL = 150
SLEW RATE (V/µs)
43
POSITIVE SLEW RATE
42
41
40
39
NEGATIVE SLEW RATE
38
37
2.0
2.5
3.0
3.5
SUPPLY VOLTAGE (V)
4.0
FIGURE 19. SLEW RATE vs SUPPLY VOLTAGE
NOISE FLOOR  nV/ Hz 
100
10
2
4
10kHz
6
8
1
100kHz
2
4
FREQUENCY (Hz)
6
8
1
1MHz
2
4
4.2MHz
FIGURE 20. UNWEIGHTED NOISE FLOOR
7
FN6184.2
September 21, 2006
ISL59114
Typical Performance Curves (Continued)
JEDEC JESD51-3 AND SEMI G42-88
(SINGLE LAYER) TEST BOARD
3
0.7
0.6 515mW
0.5

POWER DISSIPATION (W)
POWER DISSIPATION (W)
0.8
µT
QF
N1
19
4° 0
C/
W
JA
=
0.4
0.3
0.2
0.1
0
0
25
75 85 100
50
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD QFN EXPOSED DIEPAD SOLDERED TO
PCB PER JESD51-5
2.5
2
1.5
1
775mW
J
0.5
0
0
25
µT Q
A =12
F N1
0
9°C
/W
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Application Information
The Sallen Key Low Pass Filter
The ISL59114 is a single-supply rail-to-rail triple (two in,
three out) video amplifier with internal sync tip clamps, a
typical -3dB bandwidth of 9MHz and slew rate of about
40V/µs. The Y and C channels are internally mixed to create
a third CVBS (composite) video output. This part is ideally
suited for applications requiring high composite and s-video
performance with very low power consumption. As the
performance characteristics and features illustrate, the
ISL59114 is optimized for portable video applications.
The Sallen Key is a classic low pass configuration. This
provides a very stable low pass function, and in the case of
the ISL59114, a three-pole roll-off at 9MHz. The three-pole
function is accomplished with an RC low pass network placed
in series with and before the Sallen Key. One pole provided by
the RC network and poles two and three provided by the
Sallen Key for a nice three-pole roll-off at 9MHz.
Internal Sync Clamp
Embedded video DACs typically use ground as their most
negative supply. This places the sync tip voltage at a
minimum of 0V. Presenting a 0V input to most single supply
amplifiers will saturate the output stage of the amplifier
resulting in a clipped sync tip and degraded video image.
The ISL59114 features an internal sync clamp and offset
function that level shifts the entire video signal to the
optimum level before it reaches the amplifiers’ input stage.
These features also help avoid saturation of the output stage
of the amplifier by setting the signal closer to the best
voltage range.
The simplified block diagram on the front page shows the
basic operation of the ISL59114’s sync clamp. The Y input’s
AC-coupled video sync signal is pulled negative by a current
source at the input. When the sync tip goes below the
comparator threshold, the comparator output goes high,
pulling up on the Y input through the diode, forcing current
into the coupling capacitor until the voltage at the Y input is
again 0V, and the comparator turns off. This forces the sync
tip clamp to always be 0V, setting the offset for the entire
video signal.
8
Output Coupling
The ISL59114 can be AC or DC coupled to its output. When
AC coupling, a 220µF coupling capacitor is recommended to
ensure that low frequencies are passed, preventing video
“tilt” or “droop” across a line.
The ISL59114’s internal sync clamp makes it possible to DC
couple the output to a video load, eliminating the need for
any AC coupling capacitors, saving board space, cost, and
eliminating any “tilt” or offset shift in the output signal. The
trade off is larger supply current draw, since the DC
component of the signal is now dissipated in the load
resistor. Typical load current for AC coupled signals is 5mA
compared to 10mA for DC coupling.
Output Drive Capability
The ISL59114 does not have internal short circuit protection
circuitry. If the output is shorted indefinitely, the power
dissipation could easily overheat the die or the current could
eventually compromise metal integrity. Maximum reliability is
maintained if the output current never exceeds ±40mA. This
limit is set by the design of the internal metal interconnect.
Note that for transient short circuits, the part is robust.
Short circuit protection can be provided externally with a
back match resistor in series with the output placed close as
possible to the output pin. In video applications this would be
a 75 resistor and will provide adequate short circuit
protection to the device. Care should still be taken not to
stress the device with a short at the output.
FN6184.2
September 21, 2006
ISL59114
Power Dissipation
With the high output drive capability of the ISL59114, it is
possible to exceed the +125°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for an application to determine if load conditions
or package types need to be modified to assure operation of
the amplifier in a safe operating area.
The maximum power dissipation allowed in a package is
determined according to:
T JMAX – T AMAX
PD MAX = -------------------------------------------- JA
Where:
TJMAX = Maximum junction temperature
Power Supply Bypassing Printed Circuit Board
Layout
As with any modern operational amplifier, a good printed
circuit board layout is necessary for optimum performance.
Lead lengths should be as short as possible. The power
supply pin must be well bypassed to reduce the risk of
oscillation. For normal single supply operation, a single
4.7µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor from VS+ to GND will suffice.
Printed Circuit Board Layout
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance.
TAMAX = Maximum ambient temperature
JA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
for sourcing:
V OUT
PD MAX = V S  I SMAX +  V S – V OUT   ---------------R
L
for sinking:
PD MAX = V S  I SMAX +  V OUT – V S   I LOAD
Where:
VS = Supply voltage
ISMAX = Maximum quiescent supply current
VOUT = Maximum output voltage of the application
RLOAD = Load resistance tied to ground
ILOAD = Load current
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
FN6184.2
September 21, 2006
ISL59114
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
6
INDEX AREA
2X
A
L10.2.1x1.6A
B
N
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
MILLIMETERS
E
SYMBOL
0.10 C
1
2X
2
0.10 C
TOP VIEW
C
A
SEATING PLANE
1
MAX
0.55
-
A1
-
-
0.05
-
0.127 REF
-
b
0.15
0.20
0.25
5
D
2.05
2.10
2.15
-
E
1.55
1.60
1.65
-
A1
SIDE VIEW
k
0.20
-
-
L
0.35
0.40
0.45
4xk
2
NX L
N
0.50 BSC
-
NX b
2
Nd
4
3
Ne
1
3
0
-
12
NOTES:
5
BOTTOM VIEW
CL
NX (b)
(A1)
L
5
e
SECTION "C-C"
TERMINAL TIP
C C
4
Rev. 3 6/06
0.10 M C A B
0.05 M C
3
(ND-1) X e
-
10

e
-
N
(DATUM B)
N-1
NOTES
0.50
e
(DATUM A)
PIN #1 ID
NOMINAL
0.45
A3
0.10 C
0.05 C
MIN
A
FOR ODD TERMINAL/SIDE
b
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. Same as JEDEC MO-255UABD except:
No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm
"L" MAX dimension = 0.45 not 0.42mm.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
2.50
1.75
0.05 MIN
L
2.00
0.80
0.275
0.10 MIN
DETAIL “A” PIN 1 ID
0.25
0.50
LAND PATTERN 10
10
FN6184.2
September 21, 2006
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