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1
ISL59115
September 21, 2006
FN6185.2
Triple Channel Video Driver with LPF
Features
The ISL59115 is a triple channel reconstruction filter with a
-3dB roll-off frequency of 9MHz. Operating from a single
supply ranging from +2.5V to +3.6V and drawing only 4.5mA
quiescent current, the ISL59115 is ideally suited for low
power, battery-operated applications. Additionally, enable
pins shut the part down in under 14ns.
• 3rd order 9MHz reconstruction filter
The ISL59115 is designed to meet the bandwidth and very
low power requirements of battery-operated communication,
instrumentation, and modern industrial applications such as
video on demand, cable set-top boxes, MP3 players, and
HDTV. The ISL59115 is offered in a space-saving µTQFN
Pb-free package guaranteed to a 0.6mm maximum height
constraint and specified for operation from -40°C to +85°C
temperature range.
• Rail-to-rail output
Pinout
• Communications devices
• 40V/µs slew rate
• Low supply current = 4.5mA
• Maximum Power-down current <0.5µA
• Supplies from 2.5V to 3.6V
• µTQFN package
• Pb-free plus anneal available (RoHS compliant)
Applications
• Video amplifiers
• Portable and handheld products
• Video on demand
ISL59115
(10 LD ΜTQFN)
TOP VIEW
• Cable set-top boxes
• Satellite set-top boxes
GND
• MP3 players
10
• HDTV
YIN
1
9
YOUT
CVBSIN
2
8
CVBSOUT
CIN
3
7
COUT
• Personal video recorder
Block Diagram
+
65mV
YIN
ENCY
6
4
ENCVBS
500mV
9MHz
- +
x2
YOUT
9MHz
65mV
- +
x2
COUT
x2
CVBSOUT
1uA
5
CIN
VDD
+
65mV
9MHz
CVBSIN
ENCY
ENCVBS
Biasing &
Control
- +
1uA
Ordering Information
PART NUMBER (Note)
ISL59115IRUZ-T7
PART MARKING
FK
TAPE AND REEL
TEMP. RANGE (°C)
7”
-40 to +85
PACKAGE (Pb-Free)
10 Ld µTQFN
PKG. DWG. #
L10.2.1x1.6A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas LLC 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL59115
Absolute Maximum Ratings (TA = +25°C)
ESD Classification
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage from VDD to GND . . . . . . . . . . . . . . . . . . . . . . . 4.2V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . VDD +0.3V to GND -0.3V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VDD = 3.3V, TA = +25°C, RL = 150 to GND, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
3.6
V
INPUT CHARACTERISTICS
VDD
Supply Voltage Range
IDD_CY
Quiescent Supply Current - CY Amps
Enabled
VIN = 500mV, ENCY = VDD, no load
3.1
4.0
mA
IDD_CVBS
Quiescent Supply Current - CVBS Amp
Enabled
VIN = 500mV, ENCVBS = VDD, no load
1.4
2.0
mA
IDD
Quiescent Supply Current
VIN = 500mV, ENCY = ENCVBS = VDD, no
load
4.5
6.0
mA
IDD_OFF
Shutdown Supply Current
ENCY = ENCVBS = 0V
0.1
0.5
µA
VY_CLAMP
Y Input Clamp Voltage
IY = -100µA
-30
-15
10
mV
IY_DOWN
Y Input Clamp Discharge Current
VY = 0.5V
0.6
1.1
1.6
µA
IY_UP
Y Input Clamp Charge Current
VY = -0.1V
-3.6
-3.0
mA
RY
Y Input Resistance
0.5V < VY < 1V
10
VCVBS_CLAMP
CVBS Input Clamp Voltage
ICVBS = -100µA
-30
-15
10
mV
ICVBS_DOWN
CVBS Input Clamp Discharge current
VCVBS = 0.5V
0.6
1.1
1.6
µA
ICVBS_UP
CVBS Input Clamp Charge current
VCVBS = -0.1V
-3.6
-3.0
mA
RCVBS
CVBS Input Resistance
0.5V < VCVBS < 1V
10
VC_CLAMP
C Input Clamp Voltage
VY = 0.05V, IC = 0A
500
550
700
mV
RC
C Input Resistance
VY = 0.05V, 0.25V < VC < 0.75V
2.0
2.5
3.0
k
IC
C Input Bias Current
VY = 0.3V
-200
-2
200
nA
VY_SYNC
Y Input Sync Detect Voltage
100
150
200
mV
VOLS
Output Level Shift Voltage
VIN = 0V, no load
60
130
200
mV
AV
Voltage Gain
RL = 150
1.95
1.99
2.04
V/V
AV_CY
AV_CVBS
C-Y Channel Gain Mismatch
-1.75
±0.5
1.75
%
-2
±0.5
2
%
PSRR
DC Power Supply Rejection
VDD = 2.5V to 3.6V
40
60
dB
VOH
Output Voltage High Swing
VIN = 2V, RL = 150 to GND
2.85
3.2
V
ISC
Output Short-Circuit Current
VIN = 2V, to GND through 10
100
145
mA
IENABLE
ENCY, ENCVBS Input Current
0V < VEN < 3.3V
-0.2
0.001
VIL
Disable Threshold
VIH
Enable Threshold
ROUT
Shutdown Output Impedance
2.5
C/Y-CVBS Channel Gain Mismatch
M
+0.2
µA
0.8
V
2.0
EN = 0V, DC
EN = 0V, f = 4.5MHz
2
M
V
5.0
7.5
3.4
k
k
FN6185.2
September 21, 2006
ISL59115
VDD = 3.3V, TA = +25°C, RL = 150 to GND, unless otherwise specified. (Continued)
Electrical Specifications
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW0.1dB
BW3dB
±0.1dB Bandwidth
-3dB Bandwidth
Normalized Stopband Gain
RSOURCE = 75, RL = 150, CL = 5pF
5.6
MHz
RSOURCE = 500, RL = 150, CL = 5pF
3.9
MHz
RSOURCE = 75, RL = 150, CL = 5pF
8.8
MHz
RSOURCE = 500, RL = 150, CL = 5pF
7.8
MHz
f = 27MHz, RSOURCE = 75
-28.5
dB
f = 27MHz, RSOURCE = 500
-30.6
dB
dG
Differential Gain
NTSC and PAL
0.10
%
dP
Differential Phase
NTSC and PAL
0.5
°
D/DT
Group Delay Variation
f = 100kHz, 5MHz
5.4
ns
SNR
Signal to Noise Ratio
100% white signal
65
dB
TON
Enable Time
VIN = 500mV, VOUT to 1%
200
ns
TOFF
Disable Time
VIN = 500mV, VOUT to 1%
14
ns
+SR
Positive Slew Rate
20% to 80%, VIN = 1V step
30
40
50
V/µs
-SR
Negative Slew Rate
80% to 20%, VIN = 1V step
-30
-40
-50
V/µs
tF
Fall Time
2.5VSTEP, 80% - 20%
25
ns
tR
Rise Time
2.5VSTEP, 20% - 80%
22
ns
Connection Diagram
3.3V
0.1uF
VDD
+
Y (luminance)
YIN
9MHz
0.1uF
500mV
C (chrominance)
S-video cable
65mV
- +
x2
YOUT
75
1uA
CIN
9MHz
0.1uF
65mV
- +
x2
COUT
75
+
CVBS (composite)
uC or tie to 3.3V
CVBSIN
9MHz
0.1uF
ENCY
ENCVBS
3
Biasing &
Control
1uA
65mV
- +
x2
CVBSOUT
75
YOUT
75
COUT
75
CVBSOUT
75
FN6185.2
September 21, 2006
ISL59115
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1
YIN
2
CVBSIN
3
CIN
4
ENCY
5
VDD
6
ENCVBS
7
COUT
8
CVBSOUT
9
YOUT
Luminance output
10
GND
Ground
Luminance input
Composite video input
Chrominance input
Enable chrominance and luminance outputs
Positive power supply
Enable composite video output
Chrominance output
Composite video output
Typical Performance Curves
5
0
-5
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
5
-0.1dB BW @ 5.6MHz
-10
-15
-20
-25
-30
-35
VDD = +3.3V
RL = 150
100k
1M
10M
FREQUENCY RESPONSE (Hz)
-28dB BW @ 27MHz
-15
-20
-25
-30
VDD = +3.3V
RL = 150
35M
1M
10M
FREQUENCY RESPONSE (Hz)
100k
FIGURE 2. GAIN vs FREQUENCY -3dB POINT
4.0
2
CL = 470pF
VDD = +3.3V
RL = 150
3.5
3.0
0
VOUT (VP-P)
NORMALIZED GAIN (dB)
-3dB BW @ 8.8MHz
-10
-35
25M
FIGURE 1. GAIN vs FREQUENCY -0.1dB
1
0
-5
-1
-2
CL = 100pF
-3
2.5
2.0
1.5
1.0
-4
CL = 10pF
-5
-6
100k
VDD = +3.3V
RL = 150
FIN = 100kHz
1M
10M
FREQUENCY RESPONSE (Hz)
0.5
25M
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS CLOAD
4
0.0
0.0
0.5
1.0
1.5
2.0
2.5
VIN (VP-P)
3.0
3.5
4.0
FIGURE 4. MAXIMUM OUTPUT MAGNITUDE vs INPUT
MAGNITUDE
FN6185.2
September 21, 2006
ISL59115
Typical Performance Curves (Continued)
270
-20
90
0
-90
-30
-40
-50
-60
-180
-270
100k
VDD = +3.3V
-10
GAIN (dB)
PHASE (°)
180
0
VDD = +3.3V
RL = 150
-70
1M
10M
FREQUENCY (Hz)
-80
100k
100M
FIGURE 5. PHASE vs FREQUENCY
1M
10M
FREQUENCY (Hz)
100M
FIGURE 6. PSRR vs FREQUENCY
-30
VDD = +3.3V
-40
YIN TO COUT
GAIN (dB)
-50
-60
-70
-80
CIN TO YOUT
-90
-100
100k
FIGURE 7. OUTPUT IMPEDANCE vs FREQUENCY
SUPPLY CURRENT (mA)
6
NO LOAD
NO INPUT
5
4
3
2
1
0
0.0
5
50M
FIGURE 8. ISOLATION vs FREQUENCY
7
FIGURE 9. MAXIMUM OUTPUT vs LOAD RESISTANCE
1M
10M
FREQUENCY (Hz)
0.5
1.0
1.5
2.0
2.5
3.0
SUPPLY VOLTAGE (V)
3.5
4.0
FIGURE 10. SUPPLY CURRENT vs SUPPLY VOLTAGE
FN6185.2
September 21, 2006
ISL59115
Typical Performance Curves (Continued)
3.5
1.8
VDD = +3.3V
RL = 150
VIN = 1VP-P
1.5
2.5
AMPLITUDE (V)
AMPLITUDE (V)
3.0
VDD = +3.3V
RL = 150
VOUT = 2.5VP-P
2.0
1.5
TRISE = 26.4ns
1.0
0.5
0
0.9
POSITIVE SLEW
RATE = 41.1V/µs
0.6
NEGATIVE SLEW
RATE = -40.8V/µs
0.3
TFALL = 26.9ns
0.0
-120 -60
1.2
0.0
-60
60 120 180 240 300 360 420 480 540
TIME (ns)
FIGURE 11. LARGE SIGNAL STEP RESPONSE
AMPLITUDE (V)
2.5
3.0
VDD = +3.3V
RL = 150
1.5
1.0
0.5
OUTPUT SIGNAL
30
60
90 120
TIME (ns)
150
180
210
0.5
OUTPUT SIGNAL
-50
3rd HD
-70
2nd HD
1M
10M
FREQUENCY (Hz)
FIGURE 15. HARMONIC DISTORTION vs FREQUENCY
6
-10
0
10
TIME (ns)
20
30
40
-30
THD
VDD = +3.3V
RL = 150
VOUT = 2VP-P
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
480
FIGURE 14. DISABLE TIME
-40
-80
420
1.0
-0.5
-20
-20
-60
360
1.5
FIGURE 13. ENABLE TIME
-30
300
2.0
0.0
0.0
0
180 240
TIME (ns)
DISABLE SIGNAL
ENABLE SIGNAL
-30
120
VDD = +3.3V
RL = 150
2.5
2.0
-0.5
-60
60
FIGURE 12. SLEW RATE
AMPLITUDE (V)
3.0
0
-40
THD
-50
-60
3rd HD
-70
2nd HD
-80
0.5
1.0
1.5
2.0
2.5
OUTPUT VOLTAGE (VP-P)
3.0
FIGURE 16. HARMONIC DISTORTION vs OUTPUT VOLTAGE
FN6185.2
September 21, 2006
ISL59115
Typical Performance Curves (Continued)
16
-3dB BANDWIDTH (MHz)
VDD = +3.3V
RL = 150
VDD = +3.3V
RL = 150
14
12
10
8
6
4
2
80
140
200
260
320
380
440
500
INPUT RESISTANCE ()
FIGURE 18. -3dB BANDWIDTH vs INPUT RESISTANCE
FIGURE 17. GROUP DELAY vs FREQUENCY
44
Vout = 2VP-P
RL = 150
SLEW RATE (V/µs)
43
POSITIVE SLEW RATE
42
41
40
39
NEGATIVE SLEW RATE
38
37
2.0
2.5
3.0
3.5
SUPPLY VOLTAGE (V)
4.0
FIGURE 19. SLEW RATE vs SUPPLY VOLTAGE
NOISE FLOOR  nV/ Hz 
100
10
2
4
10kHz
6
8
1
100kHz
2
4
FREQUENCY (Hz)
6
8
1
1MHz
2
4
4.2MHz
FIGURE 20. UNWEIGHTED NOISE FLOOR
7
FN6185.2
September 21, 2006
ISL59115
Typical Performance Curves (Continued)
3
0.7
0.6 515mW
0.5
0.4
0.3
POWER DISSIPATION (W)
POWER DISSIPATION (W)
0.8
JEDEC JESD51-3 AND SEMI G42-88
(SINGLE LAYER) TEST BOARD
µT
QF

JA
N
=1
94 10
°C
/W
0.2
0.1
0
0
25
75 85 100
50
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD QFN EXPOSED DIEPAD SOLDERED TO
PCB PER JESD51-5
2.5
2
1.5
1
775mW
J
0.5
0
0
25
µT Q
A =12
F N1
0
9°C
/W
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Application Information
The Sallen Key Low Pass Filter
The ISL59115 is a single-supply rail-to-rail triple (one s-video
channel and one composite channel) video amplifier with
internal sync tip clamps, a typical -3dB bandwidth of 9MHz
and slew rate of about 40V/µs. This part is ideally suited for
applications requiring high composite and s-video
performance with very low power consumption. As the
performance characteristics and features illustrate, the
ISL59115 is optimized for portable video applications.
The Sallen Key is a classic low pass configuration. This
provides a very stable low pass function, and in the case of
the ISL59115, a three-pole roll-off at 9MHz. The three-pole
function is accomplished with an RC low pass network placed
in series with and before the Sallen Key. One pole provided by
the RC network and poles two and three provided by the
Sallen Key for a nice three-pole roll-off at 9MHz.
Internal Sync Clamp
The ISL59115 can be AC or DC coupled to its output. When
AC coupling, a 220µF coupling capacitor is recommended to
ensure that low frequencies are passed, preventing video
“tilt” or “droop” across a line.
Embedded video DACs typically use ground as their most
negative supply. This places the sync tip voltage at a
minimum of 0V. Presenting a 0V input to most single supply
amplifiers will saturate the output stage of the amplifier
resulting in a clipped sync tip and degraded video image.
The ISL59115 features an internal sync clamp and offset
function that level shifts the entire video signal to the
optimum level before it reaches the amplifiers’ input stage.
These features also help avoid saturation of the output stage
of the amplifier by setting the signal closer to the best
voltage range.
The simplified block diagram on the front page shows the
basic operation of the ISL59115’s sync clamp. The Y and
CVBS inputs’ AC-coupled video sync signal is pulled
negative by a current source at the input. When the sync tip
goes below the comparator threshold, the comparator output
goes high, pulling up on the input through the diode, forcing
current into the coupling capacitor until the voltage at the
input is again 0V, and the comparator turns off. This forces
the sync tip clamp to always be 0V, setting the offset for the
entire video signal. The C channel is slaved to the Y channel
and clamped to a 500mV level.
8
Output Coupling
The ISL59115’s internal sync clamp makes it possible to DC
couple the output to a video load, eliminating the need for
any AC coupling capacitors, saving board space, cost, and
eliminating any “tilt” or offset shift in the output signal. The
trade off is larger supply current draw, since the DC
component of the signal is now dissipated in the load
resistor. Typical load current for AC coupled signals is 5mA
compared to 10mA for DC coupling.
Output Drive Capability
The ISL59115 does not have internal short circuit protection
circuitry. If the output is shorted indefinitely, the power
dissipation could easily overheat the die or the current could
eventually compromise metal integrity. Maximum reliability is
maintained if the output current never exceeds ±40mA. This
limit is set by the design of the internal metal interconnect.
Note that for transient short circuits, the part is robust.
Short circuit protection can be provided externally with a
back match resistor in series with the output placed close as
possible to the output pin. In video applications this would be
a 75 resistor and will provide adequate short circuit
protection to the device. Care should still be taken not to
stress the device with a short at the output.
FN6185.2
September 21, 2006
ISL59115
Power Dissipation
With the high output drive capability of the ISL59115, it is
possible to exceed the +125°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for an application to determine if load conditions
or package types need to be modified to assure operation of
the amplifier in a safe operating area.
The maximum power dissipation allowed in a package is
determined according to:
T JMAX – T AMAX
PD MAX = -------------------------------------------- JA
Where:
TJMAX = Maximum junction temperature
Power Supply Bypassing Printed Circuit Board
Layout
As with any modern operational amplifier, a good printed
circuit board layout is necessary for optimum performance.
Lead lengths should be as short as possible. The power
supply pin must be well bypassed to reduce the risk of
oscillation. For normal single supply operation, a single
4.7µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor from VS+ to GND will suffice.
Printed Circuit Board Layout
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance.
TAMAX = Maximum ambient temperature
JA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
for sourcing:
V OUT
PD MAX = V S  I SMAX +  V S – V OUT   ---------------R
L
for sinking:
PD MAX = V S  I SMAX +  V OUT – V S   I LOAD
Where:
VS = Supply voltage
ISMAX = Maximum quiescent supply current
VOUT = Maximum output voltage of the application
RLOAD = Load resistance tied to ground
ILOAD = Load current
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
FN6185.2
September 21, 2006
ISL59115
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
6
INDEX AREA
2X
A
L10.2.1x1.6A
B
N
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
MILLIMETERS
E
SYMBOL
0.10 C
1
2X
2
0.10 C
TOP VIEW
C
A
SEATING PLANE
1
MAX
0.55
-
A1
-
-
0.05
-
0.127 REF
-
b
0.15
0.20
0.25
5
D
2.05
2.10
2.15
-
E
1.55
1.60
1.65
-
A1
SIDE VIEW
k
0.20
-
-
L
0.35
0.40
0.45
4xk
2
NX L
N
0.50 BSC
-
NX b
2
Nd
4
3
Ne
1
3
0
-
12
NOTES:
5
BOTTOM VIEW
CL
NX (b)
(A1)
L
5
e
SECTION "C-C"
TERMINAL TIP
C C
4
Rev. 3 6/06
0.10 M C A B
0.05 M C
3
(ND-1) X e
-
10

e
-
N
(DATUM B)
N-1
NOTES
0.50
e
(DATUM A)
PIN #1 ID
NOMINAL
0.45
A3
0.10 C
0.05 C
MIN
A
FOR ODD TERMINAL/SIDE
b
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. Same as JEDEC MO-255UABD except:
No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm
"L" MAX dimension = 0.45 not 0.42mm.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
2.50
1.75
0.05 MIN
L
2.00
0.80
0.275
0.10 MIN
DETAIL “A” PIN 1 ID
0.25
0.50
LAND PATTERN 10
10
FN6185.2
September 21, 2006
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