DATASHEET

Data Sheet
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September 21, 2006
YC to Composite Video Driver with LPF
Features
The ISL59116 is a YC reconstruction filter with a -3dB roll-off
frequency of 9MHz and summer amplifier to create the
composite video signal. Operating from single supplies
ranging from +2.5V to +3.6V and drawing only 4.6mA
quiescent current, the ISL59116 is ideally suited for low
power, battery-operated applications. Additionally, an enable
high pin shuts the part down in under 14ns.
• 3rd order 9MHz reconstruction filter
The ISL59116 is designed to meet the needs for very low
power and bandwidth required in battery-operated
communication, instrumentation, and modern industrial
applications such as video on demand, cable set-top boxes,
MP3 players, and HDTV. The ISL59116 is offered in a
space-saving WLCSP chipscale package guaranteed to a
0.57mm maximum height constraint and specified for
operation from -40°C to +85°C temperature range.
• Rail-to-rail output
Pinout
• Communications devices
2
FN6277.0
• 40V/µs slew rate
• Low supply current = 4.6mA
• Power-down current less than 1µA
• Supplies from 2.5V to 3.6V
• WLCSP package
• Pb-free plus anneal available (RoHS compliant)
Applications
• Video amplifiers
• Portable and handheld products
• Video on demand
ISL59116 (WLCSP)
TOP VIEW
1
ISL59116
• Cable set-top boxes
• Satellite set-top boxes
3
• MP3 players
A
• HDTV
CIN
GND
• Personal video recorder
COUT
Block Diagram
B
ENCLAMP
EN
CVBSOUT
+
YIN
C
500mV
YIN
VDD
YOUT
CIN
9MHz
65mV
- + x2
YOUT
9MHz
65mV
- + x2
COUT
65mV
- + x2
CVBSOUT
5µA
+
ENCLAMP
+
EN
Ordering Information
PART NUMBER
(Note)
ISL59116IIZ
PART MARKING
116Z
TAPE AND REEL
TEMP RANGE (°C)
7”
-40 to +85
PACKAGE (Pb-Free)
WLCSP
PKG. DWG. #
W3x3.9A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas LLC.
Copyright © Intersil Americas LLC. 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL59116
Absolute Maximum Ratings (TA = +25°C)
ESD Classification
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage from VDD to GND . . . . . . . . . . . . . . . . . . . . . . . 4.2V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . VDD +0.3V to GND -0.3V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VDD = 3.3V, TA = +25°C, RL = 150 to GND, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
3.6
V
INPUT CHARACTERISTICS
VDD
Supply Voltage Range
2.5
IDD
Quiescent Supply Current
VIN = 500mV, EN = VDD, no load
4.6
6.5
mA
IDD_OFF
Shutdown Supply Current
EN = 0V
0.1
0.5
µA
VY_CLAMP
Y Input Clamp Voltage
IY = -100µA
-30
-15
10
mV
IY_DOWN
Y input Clamp Discharge Current
VY = 0.5V
3
5.5
7
µA
IY_UP
Y Input Clamp Charge Current
VY = -0.1V
-3.7
-2.5
mA
RY
Y Input Resistance
0.5V < VY < 1V
10
VC_CLAMP
C Input Clamp Voltage
VY = 0.05V, IC = 0A
500
550
700
mV
RC
C Input Resistance
VY = 0.05V, 0.25V < VC < 0.75V
2.0
2.5
3
k
IC
C Input Bias Current
VY = 0.3V
VY_SYNC
Y Input Sync Detect Voltage
VOLS
Output Level Shift Voltage
VIN = 0V, no load
AV_CY
Voltage Gain, C-Y channel
AV_CVBS
Voltage Gain, CVBS channel
AV_CY
C-to-Y Channel Gain Mismatch
AV_CVBS
C/Y-to-CVBS Channel Gain Mismatch
PSRRCY
DC Power Supply Rejection (S-Video)
M
10
pA
100
150
200
mV
60
140
200
mV
RL = 150
1.95
1.99
2.04
V/V
RL = 150
1.93
1.98
2.04
V/V
-1.75
±0.5
1.75
%
-3
±0.7
+3
%
VDD = 2.5V to 3.6V
40
60
dB
PSRRCVBS
DC Power Supply Rejection (Composite) VDD = 2.5V to 3.6V
25
35
dB
VOH
Output Voltage High Swing
VIN = 2V, RL = 150 to GND
2.85
3.2
V
ISC
Output Short-Circuit Current
VIN = 2V, to GND through 10
100
145
mA
IENABLE
EN, ENCLAMP Input Current
0V < VENx < 3.3V
-0.2
VIL
Disable Threshold
VIH
Enable Threshold
ROUT
Shutdown Output Impedance
0.2
µA
0.8
V
2.0
EN = 0V, DC
5
V
6.5
8
k
EN = 0V, f = 4.5MHz
3.4
k
AC PERFORMANCE
BW0.1dB
±0.1dB Bandwidth
RL = 150, CL = 5pF
5
MHz
BW3dB
-3dB Bandwidth
RL = 150, CL = 5pF
9.0
MHz
Normalized Stopband Gain
f = 27MHz
-24.2
dB
2
FN6277.0
September 21, 2006
ISL59116
Electrical Specifications
PARAMETER
VDD = 3.3V, TA = +25°C, RL = 150 to GND, unless otherwise specified. (Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
dG
Differential Gain
NTSC and PAL
0.10
%
dP
Differential Phase
NTSC and PAL
0.5
°
D/DT
Group Delay Variation
f = 100kHz, 5MHz
5.4
ns
SNR
Signal To Noise Ratio
100% white signal
65
dB
TON
Enable Time
VIN = 500mV, VOUT to 1%
200
ns
TOFF
Disable Time
VIN = 500mV, VOUT to 1%
14
ns
+SR
Positive Slew Rate
20% to 80%, VIN = 1V step
30
45
60
V/µs
-SR
Negative Slew Rate
80% to 20%, VIN = 1V step
-30
-45
-60
V/µs
tF
Fall Time
2.5VSTEP, 80% - 20%
25
ns
tR
Rise Time
2.5VSTEP, 20% - 80%
22
ns
Connection Diagram
S-VIDEO CABLE
+
Y (LUMINANCE)
9MHz
0.1µF
-+
YOUT
-+
9MHz
0.1µF
YOUT
75
5µA
65mV
CIN
x2
COUT
75
ENCLAMP
+
+
65mV
-+
µC OR
TIE TO 3.3V
x2
75
500mV
C (CHROMINANCE)
65mV
YIN
COUT
75
CVBSOUT
x2
75
EN
CVBSOUT
75
NOTES:
ENCLAMP IS HIGH FOR AC COUPLED INPUTS (as shown)
ENCLAMP IS LOW FOR DC COUPLED INPUTS
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
A1
CIN
A2
GND
Ground
A3
COUT
Chrominance output
B1
ENCLAMP
B2
EN
B3
CVBSOUT
C1
YIN
Luminance Input
C2
VDD
Positive power supply
C3
YOUT
Chrominance input
Enable clamp. Tie high for AC coupled inputs. Tie low for DC coupled inputs.
Enable
Composite Video output
Luminance output
3
FN6277.0
September 21, 2006
ISL59116
Typical Performance Curves
1
5
VDD = +3.3V
RL = 150
-0.1dB BW @ 3.7MHz
0
-1
-2
-3
-4
-5
-6
100k
1M
10M
0
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
2
-5
-3dB BW @ 9MHz
-30dB BW @ 27MHz
-10
-15
-20
-25
-30
-35
VDD = +3.3V
RL = 150
-40
100k
25M
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 2. GAIN vs FREQUENCY -3dB POINT
FIGURE 1. GAIN vs FREQUENCY -0.1dB
4.0
1
3.5
CL = 10pF
3.0
0
VOUT (VP-P)
NORMALIZED GAIN (dB)
2
VDD = +3.3V
RL = 150
-1
-2
CL = 100pF
-3
2.5
2.0
1.5
0.5
-5
-6
VDD = +3.3V
RL = 150
FIN = 100kHz
1.0
CL = 470pF
-4
40M
10M
0.0
100k
1M
FREQUENCY (Hz)
10M
25M
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS CLOAD
270
180
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VIN (VP-P)
FIGURE 4. MAXIMUM OUTPUT MAGNITUDE vs INPUT
MAGNITUDE
-20
VDD = +3.3V
RL = 150
-30
VDD = +3.3V
-40
PSRR (dB)
PHASE (°)
90
0
-90
-50
-60
-70
-80
-180
-270
-90
100k
1M
10M
FREQUENCY (Hz)
FIGURE 5. PHASE vs FREQUENCY
4
100M
-100
100k
1M
10M
FREQUENCY (Hz)
100M
FIGURE 6. PSRR vs FREQUENCY
FN6277.0
September 21, 2006
ISL59116
Typical Performance Curves (Continued)
-40
-50
VDD = +3.3V
YIN to COUT
PSRR (dB)
-60
-70
-80
-90
CIN to YOUT
-100
-110
100k
1M
10M
50M
FREQUENCY (Hz)
FIGURE 8. ISOLATION vs FREQUENCY
FIGURE 7. OUTPUT IMPEDANCE vs FREQUENCY
8
SUPPLY CURRENT (mA)
VDD = +3.3V
FIN = 1MHz
NO LOAD
NO INPUT
7
6
5
4
3
2
1
0
0.5
FIGURE 9. MAXIMUM OUTPUT vs LOAD RESISTANCE
AMPLITUDE (V)
AMPLITUDE (V)
TRISE = 10.46ns
0.7
TFALL = 26.81ns
0
100
200 300
TIME (ns)
400
500
VDD = +3.3V
RL = 150
VOUT = 200mVP-P
0.3
0.2
TRISE = 27.85ns
0.1
600
FIGURE 11. LARGE SIGNAL STEP RESPONSE
5
4.0
0.4
1.2
-0.3
-100
3.5
0.5
VDD = +3.3V
RL = 150
VOUT = 1VP-P
0.2
1.5
2.0
2.5
3.0
SUPPLY VOLTAGE (V)
FIGURE 10. SUPPLY CURRENT vs SUPPLY VOLTAGE
2.2
1.7
1.0
0
-100
TFALL = 27.92ns
0
100
200
300
TIME (ns)
400
500
600
FIGURE 12. SMALL SIGNAL STEP RESPONSE
FN6277.0
September 21, 2006
ISL59116
Typical Performance Curves (Continued)
AMPLITUDE (V)
2.0
2.5
VDD = +3.3V
RL = 150
ENABLE SIGNAL
1.5
1.0
0.5
0.0
-0.5
-50
0
50
100
TIME (ns)
VDD = +3.3V
RL = 150
1.5
1.0
0.5
OUTPUT SIGNAL
0.0
-0.5
OUTPUT SIGNAL
-1.0
-100
DISABLE SIGNAL
2.0
AMPLITUDE (V)
2.5
150
-1.0
-20
200
FIGURE 13. ENABLE TIME
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
20
30
-10
VDD = +3.3V
RL = 150
VOUT = 2VP-P
THD
-40
-50
-60
2nd HD
-70
-80
0
10
TIME (ns)
FIGURE 14. DISABLE TIME
-20
-30
-10
3rd HD
1M
10M
-20
-30
VDD = +3.3V
RL = 150
FIN = 500kHz
-50
-60
-70
-80
0.5
FREQUENCY (Hz)
FIGURE 15. HARMONIC DISTORTION vs FREQUENCY
THD
-40
2nd HD
3rd HD
1.0
1.5
2.0
OUTPUT VOLTAGES (VP-P)
2.5
FIGURE 16. HARMONIC DISTORTION vs OUTPUT VOLTAGE
16
-3dB BANDWIDTH (MHz)
VDD = +3.3V
RL = 150
14
12
10
8
6
4
2
20
FIGURE 17. GROUP DELAY vs FREQUENCY
6
VDD = +3.3V
RL = 150
100
180
260
340
INPUT RESISTANCE ()
420
500
FIGURE 18. -3dB BANDWIDTH vs INPUT RESISTANCE
FN6277.0
September 21, 2006
ISL59116
Typical Performance Curves (Continued)
50
VIN = 1VP-P
RL = 150
SLEW RATE (V/µs)
45
POSITIVE SLEW RATE
40
45
NEGATIVE SLEW RATE
35
30
25
2.0
2.5
3.0
3.5
SUPPLY VOLTAGE (V)
4.0
FIGURE 19. SLEW RATE vs SUPPLY VOLTAGE
NOISE FLOOR  nV/ Hz 
100
10
2
4
6
8
10kHz
1
100kHz
2
4
6
8
1
2
4
1MHz
FREQUENCY (Hz)
4.2MHz
FIGURE 20. UNWEIGHTED NOISE FLOOR
JEDEC JESD51-3 LOW EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
1.4
0.9
POWER DISSIPATION (W)
POWER DISSIPATION (W)
1
0.8
0.7
0.6
0.5
462mW
WLCSP (3x3 BUMP)
0.4
JA=216°C/W
0.3
0.2
0.1
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
7
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
1.2
952mW
1
WLCSP (3x3 BUMP)
0.8
JA=105°C/W
0.6
0.4
0.2
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN6277.0
September 21, 2006
ISL59116
Application Information
Output Drive Capability
The ISL59116 is a single-supply rail-to-rail triple (two in,
three out) video amplifier with internal sync tip clamps, a
typical -3dB bandwidth of 9MHz and slew rate of about
40V/µs. The Y and C channels are internally mixed to create
a third CVBS (composite) video output. This part is ideally
suited for applications requiring high composite and S-video
performance with very low power consumption. As the
performance characteristics and features illustrate, the
ISL59116 is optimized for portable video applications.
The ISL59116 does not have internal short circuit protection
circuitry. If the output is shorted indefinitely, the power
dissipation could easily overheat the die or the current could
eventually compromise metal integrity. Maximum reliability is
maintained if the output current never exceeds ±40mA. This
limit is set by the design of the internal metal interconnect.
Note that for transient short circuits, the part is robust.
Internal Sync Clamp
Embedded video DACs typically use ground as their most
negative supply. This places the sync tip voltage at a
minimum of 0V. Presenting a 0V input to most single supply
amplifiers will saturate the output stage of the amplifier
resulting in a clipped sync tip and degraded video image.
The ISL59116 features an internal sync clamp and offset
function that level shifts the entire video signal to the optimum
level before it reaches the amplifiers’ input stage. These
features also help avoid saturation of the output stage of the
amplifier by setting the signal closer to the best voltage range.
The simplified block diagram on the front page shows the
basic operation of the ISL59116’s sync clamp. The Y input’s
AC-coupled video sync signal is pulled negative by a current
source at the input. When the sync tip goes below the
comparator threshold, the comparator output goes high,
pulling up on the Y input through the diode, forcing current
into the coupling capacitor until the voltage at the Y input is
again 0V, and the comparator turns off. This forces the sync
tip clamp to always be 0V, setting the offset for the entire
video signal.
The Sallen Key Low Pass Filter
Short circuit protection can be provided externally with a
back match resistor in series with the output placed close as
possible to the output pin. In video applications this would be
a 75 resistor and will provide adequate short circuit
protection to the device. Care should still be taken not to
stress the device with a short at the output.
Power Dissipation
With the high output drive capability of the ISL59116, it is
possible to exceed the +125°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for an application to determine if load conditions
or package types need to be modified to assure operation of
the amplifier in a safe operating area.
The maximum power dissipation allowed in a package is
determined according to:
T JMAX – T AMAX
PD MAX = -------------------------------------------- JA
Where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
JA = Thermal resistance of the package
The Sallen Key is a classic low pass configuration. This
provides a very stable low pass function, and in the case of
the ISL59116, a three-pole roll-off at 9MHz. The three-pole
function is accomplished with an RC low pass network placed
in series with and before the Sallen Key. The first pole is
formed by an RC network, with poles two and three generated
with a Sallen Key, creating a nice three-pole roll-off at 9MHz.
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
Output Coupling
for sinking:
The ISL59116 can be AC or DC coupled to its output. When
AC coupling, a 220µF coupling capacitor is recommended to
ensure that low frequencies are passed, preventing video
“tilt” or “droop” across a line.
The ISL59116’s internal sync clamp makes it possible to DC
couple the output to a video load, eliminating the need for
any AC coupling capacitors, saving board space, cost, and
eliminating any “tilt” or offset shift in the output signal. The
trade off is larger supply current draw, since the DC
component of the signal is now dissipated in the load
resistor. Typical load current for AC coupled signals is 5mA
compared to 10mA for DC coupling.
8
for sourcing:
V OUT
PD MAX = V S  I SMAX +  V S – V OUT   ---------------R
L
PD MAX = V S  I SMAX +  V OUT – V S   I LOAD
Where:
VS = Supply voltage
ISMAX = Maximum quiescent supply current
VOUT = Maximum output voltage of the application
RLOAD = Load resistance tied to ground
ILOAD = Load current
FN6277.0
September 21, 2006
ISL59116
Power Supply Bypassing Printed Circuit Board
Layout
As with any modern operational amplifier, a good printed
circuit board layout is necessary for optimum performance.
Lead lengths should be as short as possible. The power
supply pin must be well bypassed to reduce the risk of
oscillation. For normal single supply operation, a single
4.7µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor from VS+ to GND will suffice.
9
Printed Circuit Board Layout
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance.
FN6277.0
September 21, 2006
ISL59116
Wafer Level Chip Scale Package (WLCSP)
W3x3.9A
3x3 ARRAY 9 BALL WAFER LEVEL CHIP SCALE PACKAGE
(For ISL59116, ISL59117 Only)
E
PIN A1 ID AREA
SYMBOL
MILLIMETERS
NOTES
A
0.62 +0.05 -0.08
-
A1
0.24 ±0.025
-
A2
0.38 REF.
-
b
0.32 ±0.03
-
bb
 0.30 REF.
-
D
1.45 ±0.05
-
D1
1.00 BASIC
-
E
1.45 ±0.05
-
E1
1.00 BASIC
-
D
TOP VIEW
bb
A2
A
A1
b
e
0.50 BASIC
-
SD
0.00 BASIC
-
N
9
3
Rev. 1 6/06
SIDE VIEW
NOTES:
1. Dimensions are in Millimeters.
E1
2. Dimensioning and tolerancing conform to ASME 14.5M-1994.
3. Symbol “N” is the actual number of solder balls.
C
4. Reference JEDEC MO-211-C, variation DD.
SD D1
B
A
1
2
3
b
BOTTOM VIEW
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN6277.0
September 21, 2006
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