DATASHEET

HA4314B
®
Data Sheet
September 11, 2007
FN3679.12
400MHz, 4x1 Video Crosspoint Switch
Features
The HA4314B is a very wide bandwidth 4x1 crosspoint switch
ideal for professional video switching, HDTV, computer monitor
routing, and other high performance applications. The circuit
features very low power dissipation (105mW Enabled, 4mW
Disabled), excellent differential gain and phase, and very high
off isolation. When disabled, the output is switched to a high
impedance state, making the HA4314B ideal for routing matrix
equipment.
• Low Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 105mW
The HA4314B requires no external current source, and
features fast switching and symmetric slew rates.
• Symmetrical Slew Rates. . . . . . . . . . . . . . . . . . . . . 1400V/μs
• 0.1dB Gain Flatness . . . . . . . . . . . . . . . . . . . . . . . . . 100MHz
• -3dB Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400MHz
• Off Isolation (100MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 70dB
• Crosstalk Rejection (30MHz) . . . . . . . . . . . . . . . . . . . . . 80dB
• Differential Gain and Phase . . . . . . . . . . . . . . . 0.01%/0.01 °
• High ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2000V
For a 4x1 crosspoint with Tally outputs (channel indicators) or
with synchronous control signals, please refer to the HA4404B
and HA4344B data sheets, respectively.
• TTL Compatible Control Inputs
• Improved Replacement for GX4314 and GX4314L
For audio channels requiring larger signal swings, please refer
to the CD22M3494 (16x8) data sheet.
• Pb-Free Available (RoHS Compliant)
Ordering Information
• Professional Video Switching and Routing
Applications
PART
NUMBER
PART
MARKING
TEMP.
RANGE
(°C)
HA4314BCA
HA 4314BCA
0 to +70
16 Ld QSOP M16.15A
• RF Switching and Routing
HA4314BCAZ* HA43 14BCAZ
(Note)
0 to +70
16 Ld QSOP M16.15A
(Pb-free)
• PCM Data Routing
HA4314BCB*
0 to +70
14 Ld SOIC
M14.15
HA4314BCBZ* 4314BCBZ
(Note)
0 to +70
14 Ld SOIC
(Pb-free)
M14.15
HA4314BCP
0 to +70
14 Ld PDIP
0 to +70
HA4314BCB
HA4314BCP
HA4314BCPZ HA4314BCPZ
(Note)
• HDTV
PACKAGE
PKG.
DWG. #
Truth Table
CS
A1
A0
OUT
0
0
0
IN0
E14.3
0
0
1
IN1
14 Ld PDIP** E14.3
(Pb-free)
0
1
0
IN2
0
1
1
IN3
1
X
X
HIGH - Z
*Add “96” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
**Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
1
• Computer Graphics
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HA4314B
T
Pinouts
HA4314B
(16 LD QSOP)
TOP VIEW
HA4314B
(14 LD SOIC, PDIP)
TOP VIEW
IN0
GND
IN1
1
2
14 V+
IN0 1
16 V+
13 A0
GND 2
15 A0
IN1 3
14 A1
GND 4
13 CS
12 A1
3
GND
4
11 CS
IN2
5
10 OUT
GND
6
9
NC
IN3
7
8
V-
IN2 5
12 OUT
GND 6
11 NOTE
IN3 7
10 NOTE
GND 8
9 V-
NOTE: These pins must be left floating or connected to ground
2
FN3679.12
September 11, 2007
HA4314B
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY
Digital Input Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . ±25mA
Analog Input Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . ±5mA
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2000V
Thermal Resistance (Typical, Note 1)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
θJA (°C/W)
14 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . .
95
14 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
120
16 Ld QSOP Package . . . . . . . . . . . . . . . . . . . . . . .
140
Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . +175°C
Maximum Junction Temperature (Plastic Package) . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
Electrical Specifications
VSUPPLY = ±5V, RL = 10kΩ, VCS = 0.8V, Unless Otherwise Specified.
TEMP. (°C)
MIN
(Note 4)
TYP
MAX
(Note 4)
UNITS
Full
±4.5
±5.0
±5.5
V
VCS = 0.8V
25, 70
-
10.5
13
mA
VCS = 0.8V
0
-
-
15.5
mA
VCS = 2.0V
25, 70
-
400
450
µA
VCS = 2.0V
0
-
400
580
µA
25, 70
±2.7
±2.8
-
V
0
±2.4
±2.5
-
V
Output Current
Full
15
20
-
mA
Input Bias Current
Full
-
30
50
µA
Output Offset Voltage
Full
-10
-
10
mV
Output Offset Voltage Drift (Note 3)
Full
-
25
50
µV/°C
Turn-On Time
25
-
160
-
ns
Turn-Off Time
25
-
320
-
ns
Output Glitch During Switching
25
-
±10
-
mV
Input Logic High Voltage
Full
2
-
-
V
Input Logic Low Voltage
Full
-
-
0.8
V
0V to 4V
Full
-2
-
2
µA
1VP-P
25
-
0.055
0.063
dB
Full
-
0.07
0.08
dB
Full
-
±0.004
±0.006
dB
PARAMETER
TEST CONDITIONS
DC SUPPLY CHARACTERISTICS
Supply Voltage
Supply Current (VOUT = 0V)
ANALOG DC CHARACTERISTICS
Output Voltage Swing without Clipping
VOUT = VIN ± VIO ± 20mV
SWITCHING CHARACTERISTICS
DIGITAL DC CHARACTERISTICS
Input Current
AC CHARACTERISTICS
Insertion Loss
Channel-to-Channel Insertion Loss Match
3
FN3679.12
September 11, 2007
HA4314B
Electrical Specifications
VSUPPLY = ±5V, RL = 10kΩ, VCS = 0.8V, Unless Otherwise Specified. (Continued)
TEMP. (°C)
MIN
(Note 4)
TYP
MAX
(Note 4)
UNITS
RS = 50Ω, CL = 10pF
25
-
400
-
MHz
RS = 20Ω, CL = 20pF
25
-
280
-
MHz
RS = 16Ω, CL = 36pF
25
-
140
-
MHz
RS = 13Ω, CL = 49pF
25
-
110
-
MHz
RS = 50Ω, CL = 10pF
25
-
100
-
MHz
RS = 20Ω, CL = 20pF
25
-
100
-
MHz
RS = 16Ω, CL = 36pF
25
-
85
-
MHz
RS = 13Ω, CL = 49pF
25
-
75
-
MHz
Input Resistance
Full
200
400
-
kΩ
Input Capacitance
Full
-
1.5
-
pF
Enabled Output Resistance
Full
-
15
-
Ω
PARAMETER
TEST CONDITIONS
-3dB Bandwidth
±0.1dB Flat Bandwidth
Disabled Output Capacitance
VCS = 2.0V
Full
-
2.5
-
pF
Differential Gain
4.43MHz, (Note 3)
25
-
0.01
0.02
%
Differential Phase
4.43MHz, (Note 3)
25
-
0.01
0.02
°
Off Isolation
1VP-P, 100MHz, VCS = 2.0V,
RL = 10Ω
Full
-
70
-
dB
Crosstalk Rejection
1VP-P, 30MHz
Full
-
80
-
dB
Slew Rate (1.5VP-P, +SR/-SR)
RS = 50Ω, CL = 10pF
25
-
1425/1450
-
V/µs
RS = 20Ω, CL = 20pF
25
-
1010/1010
-
V/µs
RS = 16Ω, CL = 36pF
25
-
725/750
-
V/µs
RS = 13Ω, CL = 49pF
25
-
600/650
-
V/µs
Total Harmonic Distortion
10MHz, RL = 1kΩ, (Note 3)
Full
-
0.01
0.1
%
Disabled Output Resistance
VCS = 2.0V
Full
-
12
-
MΩ
NOTES:
3. Limits should be considered typical and are not production tested.
4. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
AC Test Circuit
PC Board Layout
500Ω
400Ω
The frequency response of this circuit depends greatly on
the care taken in designing the PC board. The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane is a must!
510Ω
HA4314
RS
VIN
75Ω
+
VOUT
HFA1100
75Ω
10kΩ
CX
NOTE:
CL = CX + Test Fixture Capacitance.
4
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
(0.1µF) chip capacitor works well in most cases.
Keep input and output traces as short as possible, because
trace inductance and capacitance can easily become the
performance limiting items.
FN3679.12
September 11, 2007
HA4314B
Application Information
General
The HA4314B is a 4x1 crosspoint switch that is ideal for the
matrix element of high performance switchers and routers.
This crosspoint’s low input capacitance and high input
resistance provide excellent video terminations when used
with an external 75Ω resistor. Nevertheless, if several
HA4314B inputs are connected together, the use of an input
buffer should be considered (see Figure 1). This crosspoint
contains no feedback or gain setting resistors, so the output
is a true high impedance load when the IC is disabled
(CS = 1).
Ground Connections
All GND pins are connected to a common point on the die,
so any one of them will suffice as the functional GND
connection. For the best isolation and crosstalk rejection,
however, all GND pins must connect to the GND plane.
Frequency Response
Most applications utilizing the HA4314B require a series
output resistor, RS, to tune the response for the specific load
capacitance, CL, driven. Bandwidth and slew rate degrade
as CL increases (as shown in the “Electrical Specifications”
on page 4), so give careful consideration to component
placement to minimize trace length. In big matrix
configurations where CL is large, better frequency response
is obtained by cascading two levels of crosspoints in the
case of multiplexed outputs (see Figure 2), or distributing the
load between two drivers if CL is due to bussing and
subsequent stage input capacitance.
Control Signals
CS - This is a TTL/CMOS compatible, active low Chip Select
input. When driven high, CS forces the output to a true high
impedance state and reduces the power dissipation by a
factor of 25. The CS input has no on-chip pull-down resistor,
so it must be connected to a logic low (recommend GND) if
the enable function isn’t utilized.
A0, A1 - These are binary coded, TTL/CMOS compatible
address inputs that select which one of the four inputs
connect to the crosspoint output.
5
Switcher/Router Applications
Figure 1 illustrates one possible implementation of a
wideband, low power, 4x4 switcher/router utilizing the
HA4314B for the switch matrix. A 4x4 switcher/router allows
any of the four outputs to be driven by any one of the four
inputs (e.g., each of the four inputs may connect to a
different output, or an input may connect to multiple outputs).
This application utilizes the HA4600 (video buffer with output
disable) for the input buffer, the HA4314B as the switch
matrix, and the HFA1112 (programmable gain buffer) as the
gain of two output driver. Figure 2 details a 16x1 switcher
(basically a 16:1 mux) which uses the HA4201 (1x1
crosspoint) and the HA4314B in a cascaded stage
configuration to minimize capacitive loading at each output
node, thus increasing system bandwidth.
Power-Up Considerations
No signals should be applied to the analog or digital inputs
before the power supplies are activated. Latch-up may occur
if the inputs are driven at the time of power-up. To prevent
latch-up, the input currents during power-up must not
exceed the values listed in the “Absolute Maximum Ratings”
on page 3.
Intersil’s Crosspoint Family
Intersil offers a variety of 4x1 and 1x1 crosspoint switches. In
addition to the HA4314B, the 4x1 family includes the
HA4404 and HA4344. The HA4404 is a 16 Ld device with
Tally outputs to indicate the selected channel. The HA4344
is a 16 Ld crosspoint with synchronized control lines (A0, A1,
CS). With synchronization, the control information for the
next channel switch can be loaded into the crosspoint
without affecting the current state. On a subsequent clock
edge the stored control state effects the desired channel
switch.
The 1x1 family is comprised of the HA4201 and HA4600.
They are essentially similar devices, but the HA4201
includes a Tally output (enable indicator). The 1x1s are
useful as high performance video input buffers, or in a switch
matrix requiring very high off isolation.
FN3679.12
September 11, 2007
HA4314B
SWITCH MATRIX
INPUT BUFFERS
+5V
EN
SOURCE 0
75Ω
OUT
HA4600
RS
IN0
SOURCE 1
IN0
HA4314
HA4314
SOURCE 2
RS
CS
RS
OUT
IN3
HA4314
CS
RS
OUT
75Ω +5V
IN0
HA4314
CS
CS
75Ω
IN0
RS
OUT
IN3
OUT
IN3
IN3
EN
SOURCE 3
-+
X2
-+
75Ω
-+
OUT RS
HA4600
OUTPUT BUFFERS
(HFA1112 OR HFA1115)
X2
75Ω
OUT0
-+
75Ω
X2
75Ω
OUT1
OUT2
X2
75Ω
OUT3
FIGURE 1. 4x4 SWITCHER/ROUTER APPLICATION
HA4314
SOURCE0
SEL0:3 SEL4:7
IN0
75Ω
IN1
IN2
IN3
SOURCE3
1/4 CD74HCT00
CS
75Ω
RS
EN
OUT
IN0
SOURCE4
75Ω
OUT
IN2
HA4201
RS
IN1
RS
CS
IN3
SOURCE7
HFA1112 OR HFA1115
75Ω
+
X2
75Ω
HA4314
SOURCE8
SEL8:11 SEL12:15
OUT
IN0
75Ω
IN1
1/4 CD74HCT00
IN2
SOURCE11
IN3
CS
75Ω
RS
OUT
SOURCE12
IN0
75Ω
OUT
RS
IN1
IN2
EN
RS
HA4201
CS
IN3
SOURCE15
75Ω
HA4314
SWITCHING
MATRIX
ISOLATION
MUX
OUTPUT
BUFFER
FIGURE 2. 16x1 SWITCHER APPLICATION
6
FN3679.12
September 11, 2007
HA4314B
Typical Performance Curves
VSUPPLY = ±5V, TA = +25°C, RL = 10kΩ, Unless Otherwise Specified
1.00
A1 (V)
0.50
0.25
0
-0.25
-0.50
-0.75
IN1 = +250mV
IN3 = 0V
A0 = +3V
2.4
1.6
OUTPUT VOLTAGE (mV)
OUTPUT VOLTAGE (V)
0.75
0.8
0
250
125
0
-1.00
TIME (200ns/DIV)
TIME (5ns/DIV)
FIGURE 4. CHANNEL-TO-CHANNEL SWITCHING RESPONSE
FIGURE 3. LARGE SIGNAL PULSE RESPONSE
VIN = 1VP-P
VIN = 1VP-P
12
0.4
9
0.3
3
0
-3
0
-0.1
CL = 20pF
-0.2
-9
CL = 36pF
-0.3
-12
CL = 49pF
-0.4
10M
FREQUENCY (Hz)
100M
CL = 10pF
0.1
-6
1M
CL = 20pF
0.2
CL = 10pF
GAIN (dB)
GAIN (dB)
6
500M
CL = 49pF
CL = 36pF
CL = 20pF
1M
FIGURE 5. FREQUENCY RESPONSE
-40
-10
-20
200M
VIN = 1VP-P
RL = 10Ω
-30
-60
-70
PDIP
SSOP
-80
-90
SOIC
-100
OFF ISOLATION (dB)
-50
CROSSTALK (dB)
100M
FIGURE 6. GAIN FLATNESS
VIN = 1VP-P
RL = 10kΩ
-40
-60
-70
-80
PDIP
-90
-120
-100
10M
100M 200M
FREQUENCY (Hz)
FIGURE 7. ALL HOSTILE CROSSTALK REJECTION
7
SOIC
-50
-110
0.6M 1M
10M
FREQUENCY (Hz)
0.3M
1M
10M
FREQUENCY (Hz)
SSOP
100M 200M
FIGURE 8. ALL HOSTILE OFF ISOLATION
FN3679.12
September 11, 2007
HA4314B
Typical Performance Curves
VSUPPLY = ±5V, TA = +25°C, RL = 10kΩ, Unless Otherwise Specified (Continued)
3.4
VIN = 1VP-P
RL = 1kΩ
3.2
CH 0
INPUT CAPACITANCE (pF)
TOTAL HARMONIC DISTORTION (%)
0.20
0.15
0.10
0.05
3.0
2.8
2.6
2.4
2.2
2.0
CH 3
1.8
CH 1
CH 2
1.6
0
10M
1.4
20M
30M
40M 50M 60M 70M
FREQUENCY (Hz)
80M
1M
90M 100M
FIGURE 9. TOTAL HARMONIC DISTORTION vs FREQUENCY
10M
FREQUENCY (Hz)
100M
500M
FIGURE 10. INPUT CAPACITANCE vs FREQUENCY
35
NOISE (nV/√Hz)
30
25
20
15
10
5
0
1
10
100
1k
FREQUENCY (Hz)
10k
100k
FIGURE 11. NOISE vs FREQUENCY
8
FN3679.12
September 11, 2007
HA4314B
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
65 milsx118 milsx19 mils
1640μmx3000μmx483μm
Type: Nitride
Thickness: 4kÅ ±0.5kÅ
METALLIZATION:
TRANSISTOR COUNT:
Type: Metal 1: AlCu (1%)/TiW
Thickness: Metal 1: 6kÅ ±0.8kÅ
Type: Metal 2: AlCu (1%)
Thickness: Metal 2: 16kÅ ±1.1kÅ
200
SUBSTRATE POTENTIAL (POWERED UP):
V-
Metallization Mask Layout
HA4314B
GND
NC
V+
IN1
A0
NC
A1
GND
CS
NC
OUT
IN2
NC
GND
NC
IN3
9
IN0
GND
NC
V-
FN3679.12
September 11, 2007
HA4314B
Dual-In-Line Plastic Packages (PDIP)
E14.3 (JEDEC MS-001-AA ISSUE D)
N
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
SYMBOL
-BD
A2
SEATING
PLANE
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MAX
NOTES
-
0.210
-
5.33
4
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8
eA
C
0.008
0.014
0.204
0.355
-
D
0.735
0.775
18.66
D1
0.005
-
0.13
A
L
D1
MIN
A
E
-C-
MAX
A1
-ABASE
PLANE
MILLIMETERS
MIN
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
19.68
-
5
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
eA
0.300 BSC
7.62 BSC
6
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
eB
-
0.430
-
10.92
7
L
0.115
0.150
2.93
3.81
4
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be
perpendicular to datum -C- .
N
14
14
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads
unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).
10
FN3679.12
September 11, 2007
HA4314B
Small Outline Plastic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
N
INDEX
AREA
H
0.25(0.010) M
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
α
A1
B
0.25(0.010) M
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3367
0.3444
8.55
8.75
3
E
0.1497
0.1574
3.80
4.00
4
e
C
0.10(0.004)
B S
0.050 BSC
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
NOTES:
MILLIMETERS
α
14
0o
14
8o
0o
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
11
FN3679.12
September 11, 2007
HA4314B
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M16.15A
N
INDEX
AREA
H
0.25(0.010) M
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
B M
E
-B1
2
INCHES
GAUGE
PLANE
3
0.25
0.010
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
α
A2
A1
B
0.17(0.007) M
L
C
0.10(0.004)
C A M
B S
NOTES:
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.061
0.068
1.55
1.73
-
A1
0.004
0.0098
0.102
0.249
-
A2
0.055
0.061
1.40
1.55
-
B
0.008
0.012
0.20
0.31
9
C
0.0075
0.0098
0.191
0.249
-
D
0.189
0.196
4.80
4.98
3
E
0.150
0.157
3.81
3.99
4
e
0.025 BSC
0.635 BSC
-
H
0.230
0.244
5.84
6.20
-
h
0.010
0.016
0.25
0.41
5
L
0.016
0.035
0.41
0.89
6
8°
0°
N
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
MILLIMETERS
α
16
0°
16
7
8°
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Rev. 2 6/04
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.10mm (0.004 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN3679.12
September 11, 2007
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