DATASHEET

Data Sheet
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1-888-I
500MHz Triple 2:1 Gain-of-2, Multiplexing
Amplifier
The ISL59448 is a triple channel 2:1 multiplexer featuring
integrated buffers with a fixed gain of 2, high slew-rate and
excellent bandwidth for video switching. The device features
a three-state output (HIZ), which allows the outputs of
multiple devices to be tied together. A power-down mode
(ENABLE) is included to turn off un-needed circuitry in power
sensitive applications. When the ENABLE pin is pulled high,
the part enters a power-down mode and consumes just
14mW. An additional feature is a latch enable function (LE)
that allows independent logic control using a common logic
bus.
PACKAGE
ISL59448IAZ
(See Note)
24 Ld QSOP (Pb-free)
ISL59448IAZ-T7
(See Note)
24 Ld QSOP (Pb-free)
FN6160.2
Features
• 500MHz bandwidth
• ±1600 V/µs slew rate
• High impedance buffered inputs
• Internally set gain-of-2
• High speed three-state outputs (HIZ)
• Power-down mode (ENABLE)
• Latch enable
• ±5V operation
• Supply current 11mA/ch
• Pb-free plus anneal available (RoHS compliant)
Ordering Information
PART NUMBER
ISL59448
TAPE &
REEL
PKG.
DWG. #
-
MDP0040
Applications
• HDTV/DTV analog inputs
• Video projectors
7”
MDP0040
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
• Computer monitors
• Set-top boxes
• Security video
• Broadcast video equipment
TABLE 1. CHANNEL SELECT LOGIC TABLE ISL59448
S0
ENABLE
HIZ
LE
OUTPUT
0
0
0
0
INO (A, B, C)
1
0
0
0
IN1 (A, B, C)
X
1
X
X
Power-down
X
0
1
X
High Z
X
0
0
1
Last S0 State
Preserved
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas LLC 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL59448
Functional Diagram (each channel)
Pinout
ISL59448
(24 LD QSOP)
TOP VIEW
IN0A
1
24 NIC
GND A
2
23 LE
IN0B
3
22 ENABLE
NIC
4
21 HIZ
GND B
5
IN0C
6
NIC
7
IN1A
8
NIC
9
S0
x2
EN0
DECODE
20 OUTA
EN1
DL Q
C
IN0(A,B,C)
DL Q IN1(A,B,C)
C
+
OUT
19 V+
AMPLIFIER BIAS
x2
18 OUTB
17 OUTC
x2
IN1B 10
16 V15 NIC
GND C 11
LE
HIZ
ENABLE
A logic high on LE will latch the last S0 state.
This logic state is preserved when cycling HIZ
or ENABLE functions.
14 S0
IN1C 12
13 NIC
LATCHED ON HIGH LE
NIC = NO INTERNAL CONNECTION
2
FN6160.2
March 29, 2006
ISL59448
Absolute Maximum Ratings (TA = 25°C)
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V
Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Digital & Analog Input Current (Note 1) . . . . . . . . . . . . . . . . . . 50mA
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
V+ = +5V, V- = -5V, GND = 0V, TA = 25°C, Vout = ±2VP-P & RL = 500 to GND, CL = 0pF, unless otherwise
specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL
+IS Enabled
Enabled Supply Current
No load, VIN = 0V, Enable Low
27
31
35
mA
-IS Enabled
Enabled Supply Current
No load, VIN = 0V, Enable Low
-32
-29
-25
mA
+IS Disabled
Disabled Supply Current
No load, VIN = 0V, Enable High
2.3
2.7
3.3
mA
-IS Disabled
Disabled Supply Current
No load, VIN = 0V, Enable High
-0.1
0.1
mA
VOUT
Positive and Negative Output Swing
VIN = ±2.5V; RL = 500
±3.1
IOUT
Output Current
VIN = 0.825V RL = 10
±80
VOS
Output Offset Voltage
Ib
±3.9
V
±180
mA
-40
-25
-10
mV
-3
-2
-1
µA
700
900
1150

Input Bias Current
VIN = 0V
ROUT
HIZ Output Resistance
HIZ = Logic High
ROUT
Enabled Output Resistance
HIZ = Logic Low
0.2

Input Resistance
VIN = ±1.75V
10
M
Voltage Gain
RL = 500
RIN
ACL or AV
1.94
1.98
2.035
V/V
LOGIC
VIH
Input High Voltage (Logic Inputs)
2
V
VIL
Input Low Voltage (Logic Inputs)
0.8
V
IIH
Input High Current (Logic Inputs)
VH = 5V
200
IIL
Input Low Current (Logic Inputs)
VL = 0V
-3
PSRR
Power Supply Rejection Ratio
DC, PSRR V+ & V- combined
VOUT = 0dBm
52
Xtalk
Channel to Channel Crosstalk
258
319
µA
3
µA
AC GENERAL
72
dB
f = 10MHz, ChX-Ch Y-Talk
VIN = 1Vp-p; CL = 1.1pF
88
dB
Off-state Isolation
f = 10MHz, Ch-Ch Off Isolation
VIN = 1Vp-p; CL = 1.1pF
72
dB
dG
Differential Gain Error
NTC-7, RL = 150, CL = 1.1pF
0.015
%
dP
Differential Phase Error
NTC-7, RL = 150, CL = 1.1pF
0.015
°
Off - ISO
3
FN6160.2
March 29, 2006
ISL59448
Electrical Specifications
PARAMETER
BW
FBW
SR
V+ = +5V, V- = -5V, GND = 0V, TA = 25°C, Vout = ±2VP-P & RL = 500 to GND, CL = 0pF, unless otherwise
specified. (Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
Small Signal -3dB Bandwidth
VOUT = 0.2Vp-p; RL = 500, CL = 1.1pF
570
MHz
Large Signal -3dB Bandwidth
VOUT = 2Vp-p; RL = 500, CL = 1.1pF
280
MHz
Small Signal -3dB Bandwidth
VOUT = 0.2Vp-p; RL = 150, CL = 1.1pF
510
MHz
Large Signal -3dB Bandwidth
VOUT = 2Vp-p; RL = 150, CL = 1.1pF
260
MHz
0.1dB Bandwidth
VOUT = 2Vp-p; RL = 500, CL = 1.1pF
140
MHz
0.1dB Bandwidth
VOUT = 2Vp-p; RL = 150, CL = 1.1pF
60
MHz
Slew Rate
25% to 75%, RL = 150, Input Enabled,
CL = 1.1pF
1600
V/µs
TRANSIENT RESPONSE
tr, tf Large
Signal
Large Signal Rise, Fall TImes, tr, tf,
10% - 90%
VOUT = 2Vp-p; RL = 500, CL = 1.1pF
1.2
ns
VOUT = 2Vp-p; RL = 150, CL = 1.1pF
1.3
ns
tr, tf, Small
Signal
Small Signal Rise, Fall TImes, tr, tf,
10% - 90%
VOUT = 0.2Vp-p; RL = 500, CL = 1.1pF
0.7
ns
VOUT = 0.2Vp-p; RL = 150, CL = 1.1pF
0.85
ns
Settling TIme 0.1%
VOUT = 2Vp-p; RL = 500, CL = 1.1pF
5
ns
VOUT = 2Vp-p; RL = 150, CL = 1.1pF
4.5
ns
VOUT = 2Vp-p; RL = 500, CL = 1.1pF
2
ns
VOUT = 2Vp-p; RL = 150, CL = 1.1pF
2.5
ns
Channel -to-Channel Switching Glitch
VIN = 0V, CL = 1.1pF
40
mVP-P
Enable Switching Glitch
VIN = 0V CL = 1.1pF
250
mVP-P
HIZ Switching Glitch
VIN = 0V CL = 1.1pF
200
mVP-P
tSW-L-H
Channel Switching Time Low to High
1.2V logic threshold to 10% movement of
analog output
18
ns
tSW-H-L
Channel Switching Time High to Low
1.2V logic threshold to 10% movement of
analog output
20
ns
tpd
Propagation Delay
10% to 10%
0.9
ns
tLH
Latch Enable Hold time
LE = 0
10
ns
ts 0.1%
ts 1%
Settling TIme 1%
SWITCHING CHARACTERISTICS
VGLITCH
4
FN6160.2
March 29, 2006
ISL59448
Typical Performance Curves VS = ±5V, RL = 500 to GND, TA = 25°C, unless otherwise specified.
10
10
Vout=0.2Vp-p
6
CL=9.3pF
4
CL=6.7pF
0
-2
CL=3.3pF
-4
CL=2.1pF
-6
-8
-10
CL=0.6pF
CL INCLUDES 0.6pF
BOARD CAPACITANCE
10
100
CL=9.3pF
4
2
0
CL=5.1pF
-2
CL=0.6pF
-4
-6
CL INCLUDES 0.6pF
BOARD CAPACITANCE
-8
-10
1
1k
1
10
0.2
RL=1k
Vout=0.2Vp-p
CL=1.1pF
RL=150
0
-1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
Vout=0.2Vp-p
CL=1.1pF
0.1
RL=500
0
RL=150
-2
RL=250
-3
-4
-5
-6
-7
-8
-0.1
RL=500
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
1
10
100
-0.8
1k
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 4. 0.1dB GAIN FLATNESS
FIGURE 3. GAIN vs FREQUENCY vs RL
10k
100
VSOURCE=2Vp-p
OUTPUT IMPEDANCE ()
VSOURCE=2Vp-p
OUTPUT IMPEDANCE ()
1k
FIGURE 2. LARGE SIGNAL GAIN vs FREQUENCY vs CL
INTO 500 LOAD
FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY vs CL
INTO 500 LOAD
1
100
FREQUENCY (MHz)
FREQUENCY (MHz)
2
CL=13.1pF
6
CL=5.1pF
2
Vout=2Vp-p
8
CL=13.1pF
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
8
10
1
0.1
0.1
1
10
100
FREQUENCY (MHz)
FIGURE 5. ZOUT vs FREQUENCY - ENABLED
5
1k
1000
100
10
0.1
1
10
100
1k
FREQUENCY (MHz)
FIGURE 6. ZOUT vs FREQUENCY - HIZ
FN6160.2
March 29, 2006
ISL59448
Typical Performance Curves VS = ±5V, RL = 500 to GND, TA = 25°C, unless otherwise specified.
1M
0
VSOURCE
2Vp-p
SOURCE==2Vp-p
VIN=1Vp-p
-10
100k
INPUT IMPEDANCE ()
(Continued)
INPUT X TO OUTPUT Y
CROSSTALK
-20
-30
10k
(dB)
-40
1k
OFF ISOLATION
INPUT X TO OUTPUT X
-50
-60
100
-70
-80
10
-90
1
0.3
1
10
100
FREQUENCY (MHz)
-100
0.1
1k
1
10
100
1k
FREQUENCY (MHz)
FIGURE 7. ZIN vs FREQUENCY
FIGURE 8. CROSSTALK AND OFF-ISOLATION
0
60
VSOURCE=1Vp-p
PSRR (dB)
-20
VOLTAGE NOISE (nV/Hz)
-10
PSRR (V-)
-30
-40
PSRR (V+)
-50
40
30
20
10
-60
-70
0.3
50
1
10
FREQUENCY (MHz)
100
0
100
1k
1k
10k
FIGURE 10. INPUT NOISE vs FREQUENCY
FIGURE 9. PSRR
VOUT=0.2Vp-p
VOUT=0.2Vp-p
RL=500
CL=1.1pF
0.1
RL=150
CL=1.1pF
0.2
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
0.2
100k
FREQUENCY (Hz)
0.1
0
0
TIME (5ns/DIV)
FIGURE 11. SMALL SIGNAL TRANSIENT RESPONSE; RL=500
6
TIME (5ns/DIV)
FIGURE 12. SMALL SIGNAL TRANSIENT RESPONSE;
RL=150
FN6160.2
March 29, 2006
ISL59448
Typical Performance Curves VS = ±5V, RL = 500 to GND, TA = 25°C, unless otherwise specified.
(Continued)
VOUT=2Vp-p
RL=150
CL=1.1pF
2.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
VOUT=2Vp-p
RL=500
CL=1.1pF
2.0
1.0
0
1.0
0
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 13. LARGE SIGLNAL TRANSIENT RESPONSE;
RL=500
FIGURE 14. LARGE SIGNAL TRANSIENT RESPONSE;
RL=150
50
50
INPUT RISE, FALL TIMES
< 200ps
VOUT=1.4Vp-p
VOUT=1Vp-p
30
VOUT=0.2Vp-p
20
VOUT=1Vp-p
30
2
4
CL (Pf)
6
8
20
0
10
2
4
CL (Pf)
6
8
10
FIGURE 16. POSITIVE PULSE OVERSHOOT vs VOUT, CL;
RL=150
FIGURE 15. POSITIVE PULSE OVERSHOOT vs VOUT, CL;
RL=500
50
50
INPUT RISE, FALL TIMES
< 200ps
VOUT=2Vp-p
40
OVERSHOOT (%)
40
OVERSHOOT (%)
VOUT=0.2Vp-p
10
10
0
VOUT=1.4Vp-p
40
OVERSHOOT (%)
OVERSHOOT (%)
40
VOUT=2Vp-p
INPUT RISE, FALL TIMES
< 200ps
VOUT=2Vp-p
VOUT=1.4Vp-p
30
20
INPUT RISE, FALL TIMES
< 200ps
VOUT=2Vp-p
VOUT=1.4Vp-p
30 VOUT=1Vp-p
20
VOUT=1Vp-p
10
10
VOUT=0.2Vp-p
0
2
4
CL (pF)
6
VOUT=0.2Vp-p
8
10
FIGURE 17. NEGATIVE PULSE OVERSHOOT vs VOUT, CL;
RL=500
7
0
2
4
CL (Pf)
6
8
10
FIGURE 18. NEGATIVEPULSE OVERSHOOT vs VOUT, CL;
RL=150
FN6160.2
March 29, 2006
ISL59448
Typical Performance Curves VS = ±5V, RL = 500 to GND, TA = 25°C, unless otherwise specified.
VIN=0V
1V/DIV
0
1V/DIV
20mV/DIV
0
0
VOUT A, B, C
0
VOUT A, B, C
20ns/DIV
20ns/DIV
FIGURE 19. CHANNEL TO CHANNEL SWITCHING GLITCH
VIN = 0V
ENABLE
50
TERM.
FIGURE 20. CHANNEL TO CHANNEL TRANSIENT RESPONSE
VIN = 1V
1V/DIV
50
TERM.
1V/DIV
0
VOUT A, B, C
2V/DIV
100mV/DIV
VIN=1V
ENABLE
VIN=0V
0
0
0
VOUT A, B, C
20ns/DIV
20ns/DIV
FIGURE 22. ENABLE TRANSIENT RESPONSE VIN = 1V
FIGURE 21. ENABLE SWITCHING GLITCH VIN = 0V
HIZ
HIZ
VIN=0V
VIN=1V
50
TERM.
1V/DIV
1V/DIV
50
TERM.
0
0
VOUT A, B, C
10ns/DIV
FIGURE 23. HIZ SWITCHING GLITCH VIN = 0V
8
2V/DIV
0
200mv/DIV
VIN=1V
S0, S1
50
TERM.
1V/DIV
S0, S1
50
TERM.
(Continued)
VOUT A, B, C
0
10ns/DIV
FIGURE 24. HIZ TRANSIENT RESPONSE VIN = 1V
FN6160.2
March 29, 2006
ISL59448
Typical Performance Curves VS = ±5V, RL = 500 to GND, TA = 25°C, unless otherwise specified.
1
1.2
QSOP24
JA=88°C/W
0.8
0.6
0.4
0.2
0
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.136W
POWER DISSIPATION (W)
POWER DISSIPATION (W)
1.2
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
(Continued)
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
9
1
870mW
0.8
QSOP24
JA=115°C/W
0.6
0.4
0.2
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN6160.2
March 29, 2006
ISL59448
Pin Descriptions
ISL59448
(24 LD QSOP)
PIN NAME
EQUIVALENT
CIRCUIT
8
IN1A
Circuit 1
4, 7, 9, 13, 15, 24
NIC
10
IN1B
Circuit 1
Channel 1 input for output amplifier "B"
12
IN1C
Circuit 1
Channel 1 input for output amplifier "C"
5
GNDB
Circuit 4
Ground pin for output amplifier “B”
11
GNDC
Circuit 4
Ground pin for output amplifier “C”
14
S0
Circuit 2
Channel selection pin. LSB (binary logic code)
17
OUTC
Circuit 3
Output of amplifier “C”
18
OUTB
Circuit 3
Output of amplifier “B”
16
V-
Circuit 4
Negative power supply
20
OUTA
Circuit 3
Output of amplifier “A”
19
V+
Circuit 4
Positive power supply
22
ENABLE
Circuit 2
Device enable (active low) w/Internal pull-down resistor. A logic High puts device into
power-down mode with the only logic circuitry active. All logic states are preserved post
power-down. This state is not recommended for logic control where more than one MUXamp share the same video output line.
23
LE
Circuit 2
Device latch enable on the ISL59424. A logic high on LE will latch the last (S0, S1) logic
state. HIZ and ENABLE functions are not latched with the LE pin.
21
HIZ
Circuit 2
Output disable (active high) w/internal pull-down resistor. A logic high, puts the outputs in
a high impedance state. Use this state to control logic when more than one MUX-amp
share the same video output line.
6
IN0C
Circuit 1
Channel 0 for output amplifier "C"
3
IN0B
Circuit 1
Channel 0 for output amplifier "B"
1
IN0A
Circuit 1
Channel 0 for output amplifier "A"
2
GNDA
Circuit 4
Ground pin for output amplifier “A”
DESCRIPTION
Channel 1 input for output amplifier "A"
Not Internally Connected; it is recommended these pins be tied to ground to minimize
crosstalk.
10
FN6160.2
March 29, 2006
ISL59448
Application Information
AC Test Circuits
General
LCRIT
ISL59448
VIN
VOUT
*CL
1.1pF
50
or
75
RL
500or
150
*CL Includes PCB trace capacitance
FIGURE 27A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
ISL59448
LCRIT
VIN
CL
50
or
75
VIN
RS
CS
RL
500or
75
TEST
EQUIPMENT
RS
475
*CL
1.1pF
50
56.2
50
*CL Includes PCB trace capacitance
FIGURE 27C. 500 TEST CIRCUIT WITH 50LOAD
ISL59448
LCRIT
TEST
EQUIPMENT
RS
VIN
118
*CL
1.1pF
50or
75
86.6
50
*CL Includes PCB trace capacitance
FIGURE 27D. 150 TEST CIRCUIT WITH 50LOAD
ISL59448
LCRIT
TEST
EQUIPMENT
RS
VIN
50 or 75
*CL
1.1pF
50
or
75
For the best isolation and crosstalk rejection, all GND pins
and NIC pins must connect to the GND plane.
AC Design Considerations
FIGURE 27B. INTER-STAGE APPLICATION CIRCUIT
ISL59448
LCRIT
Key features of the ISL59448 include a fixed gain of 2,
buffered high impedance analog inputs and excellent AC
performance at output loads down to 150 for video cabledriving. The current feedback output amplifiers are stable
operating into capacitive loads.
50 or 75
*CL Includes PCB trace capacitance
FIGURE 27E. BACKLOADED TEST CIRCUIT FOR 75 VIDEO
CABLE APPLICATION
AC Test Circuits
Figure 27C and 27D illustrate the optimum output load for
testing AC performance at 500 and 150 loads. Figure
27E illustrates the optimun output load for 50 and 75
cable-driving.
11
High speed current-feed amplifiers are sensitive to
capacitance at the inverting input and output terminals. The
ISL59448 has an internally set gain of 2, so the inverting
input is not accessible. Capacitance at the output terminal
increases gain peaking (Figure 1) and pulse overshoot
(Figures15 thru 18). The AC response of the ISL59448 is
optimized for a total capacitance of 1.1pF over the load
range of 150 to 500
PC board trace length should be kept to a minimum in order
to minimize output capacitance and prevent the need for
controlled impedance lines. At 500MHz trace lengths
approaching 1” begin exhibiting transmission line behavior
and may cause excessive ringing if controlled impedance
traces are not used. Figure 27A shows the optimum interstage circuit when the total output trace length is less than
the critical length of the highest signal frequency.
For applications where pulse response is critical and where
inter-stage distances exceed LCRIT, the circuit shown in
Figure 27B is recommended. Resistor RS constrains the
capacitance seen by the amplifier output to the trace
capacitance from the output pin to the resistor. Therefore,
RS should be placed as close to the ISL59448 output pin as
possible. For inter-stage distances much greater than LCRIT,
the back-loaded circuit shown in Figure 27E should be used
with controlled impedance PCB lines, with RS and RL equal
to the controlled impedance.
For applications where inter-stage distances are long, but
pulse response is not critical, capacitor CS can be added to
low values of RS to form a low-pass filter to dampen pulse
overshoot. This approach avoids the need for the large gain
correction required by the -6dB attenuation of the backloaded controlled impedance interconnect. Load resistor RL
is still required but can be 500 or greater, resulting in a
much smaller attenuation factor.
Control Signals
S0, S1, ENABLE, LE, HIZ - These are binary coded,
TTL/CMOS compatible control inputs. The S0, S1 pins select
the inputs. All three amplifiers are switched simultaneously
from their respective inputs. The ENABLE, LE, HIZ pins are
used to disable the part to save power, latch in the last logic
state and three-state the output amplifiers, respectively. For
FN6160.2
March 29, 2006
ISL59448
control signal rise and fall times less than 10ns the use of
termination resistors close to the part will minimize transients
coupled to the output.
ENABLE and Power-down States
The enable pin is active low. An internal pull-down resistor
ensures the device will be active with no connection to the
ENABLE pin. The Power-down state is established within
approximately 200ns (Figure 22), if a logic high (>2V) is
placed on the ENABLE pin. In the power-down state, the
output has no leakage but has a large variable capacitance
(on the order of 15pF), and is capable of being back-driven.
Under this condition, large incoming slew rates can cause
fault currents of tens of mA. Therefore, the parallel
connection of multiple outputs is not recommended unless
the application can tolerate the limited powerdown output
impedance.
Power-up Considerations
The ESD protection circuits use internal diodes from all pins
the V+ and V- supplies. In addition, a dV/dT- triggered clamp
is connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 section of the Pin Description
table. The dV/dT triggered clamp imposes a maximum
supply turn-on slew rate of 1V/µs. Damaging currents can
flow for power supply rates-of-rise in excess of 1V/µs, such
as during hot plugging. Under these conditions, additional
methods should be employed to ensure the rate of rise is not
exceeded.
LE State
The ISL59448 is equipped with a Latch Enable pin. A logic
high (>2V) on the LE pin latches the last logic state. This
logic state is preserved when cycling HIZ or ENABLE
functions.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic
input pins. Schottky diodes (Motorola MBR0550T or
equivalent) connected from V+ to ground and V- to ground
(Figure 4) will shunt damaging currents away from the
internal V+ and V- ESD diodes in the event that the V+
supply is applied to the device before the V- supply.
Limiting the Output Current
No output short circuit current limit exists on these parts. All
applications need to limit the output current to less than
50mA. Adequate thermal heat sinking of the parts is also
required.
If positive voltages are applied to the logic or analog video
input pins before V+ is applied, current will flow through the
internal ESD diodes to the V+ pin. The presence of large
decoupling capacitors and the loading effect of other circuits
connected to V+, can result in damaging currents through
the ESD diodes and other active circuits within the device.
Therefore, adequate current limiting on the digital and
analog inputs is needed to prevent damage during the time
the voltages on these inputs are more positive than V+.
HIZ State
An internal pull-down resistor ensures the device will be
active with no connection to the HIZ pin. The HIZ state is
established within approximately 15ns (Figure 14) by placing
a logic high (>2V) on the HIZ pin. If the HIZ state is selected,
the output impedance is ~1000 (Figure 6). The supply
current during this state is same as the active state.
V+ SUPPLY
SCHOTTKY
PROTECTION
LOGIC
V+
LOGIC
CONTROL
S0
POWER
GND
GND
SIGNAL
IN0
EXTERNAL
CIRCUITS
V+
V-
V+
V+
V+
OUT
V-
DE-COUPLING
CAPS
IN1
VV-
V-
V- SUPPLY
FIGURE 28. SCHOTTKY PROTECTION CIRCUIT
12
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ISL59448
PC Board Layout
The AC performance of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
sharp corners, use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces greater than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. High frequency performance may be
degraded for traces greater than one inch, unless strip line
are used.
• Match channel-channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
• Maximize use of AC de-coupled PCB layers. All signal I/O
lines should be routed over continuous ground planes (i.e.
no split planes or PCB gaps under these lines). Avoid vias
in the signal I/O lines.
• Use proper value and location of termination resistors.
Termination resistors should be as close to the device as
possible.
• When testing use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
• Minimum of 2 power supply de-coupling capacitors are
recommended (1000pF, 0.01µF) as close to the devices
as possible - Avoid vias between the cap and the device
because vias add unwanted inductance. Larger caps can
be farther away. When vias are required in a layout, they
should be routed as far away from the device as possible.
• The NIC pins are placed on both sides of the input pins.
These pins are not internally connected to the die. It is
recommended these pins be tied to ground to minimize
crosstalk.
13
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ISL59448
QSOP Package Outline Drawing
®
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
<http://www.intersil.com/design/packages/index.asp>
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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14
FN6160.2
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