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1-888-IN
12-Bit, 80 MSPS,
High Speed Video D/A Converter
HI5735KCB
0 to 70
• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650mW
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . 0.75 LSB
• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . . 3.0pV-s
• TTL/CMOS Compatible Inputs
• Improved Hold Time . . . . . . . . . . . . . . . . . . . . . . . . 0.25ns
• Excellent Spurious Free Dynamic Range
Applications
• Professional Video
• Cable TV Headend Equipment
PACKAGE
28 Lead SOIC
PKG.
NO.
Pinout
HI5735 (SOIC)
TOP VIEW
M28.3
D11 (MSB)
1
FN4133.4
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 80 MSPS
Ordering Information
PART NUMBER
May 2003
Features
The HI5735 is a 12-bit, 80 MSPS, D/A converter which is
implemented in the Intersil BiCMOS 10V (HBC-10) process.
Operating from +5V and -5.2V, the converter provides
-20.48mA of full scale output current and includes an input
data register and bandgap voltage reference. Low glitch
energy and excellent frequency domain performance are
achieved using a segmented architecture. The digital inputs
are TTL/CMOS compatible and translated internally to ECL.
All internal logic is implemented in ECL to achieve high
switching speed with low noise. The addition of laser
trimming assures 12-bit linearity is maintained along the
entire transfer curve.
TEMP.
RANGE (oC)
HI5735
1
28 DGND
D10 2
27 AGND
D9 3
26 REF OUT
D8 4
25 CTRL OUT
D7 5
24 CTRL IN
D6 6
23 RSET
D5 7
22 AVEE
D4 8
21 IOUT
D3 9
20 IOUT
D2 10
19 ARTN
D1 11
18 DVEE
D0 (LSB) 12
17 DGND
NC 13
16 DVCC
NC 14
15 CLOCK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI5735
Typical Application Circuit
+5V
HI5735
0.01F
VCC (16)
D11
D11 (MSB) (1)
D10
D10 (2)
D9
D9 (3)
D8
D8 (4)
D7
D7 (5)
D6
D6 (6)
D5
D5 (7)
D4
D4 (8)
D3
D3 (9)
D2
D2 (10)
D1
D1 (11)
D0
D0 (LSB) (12)
0.1F
(24) CTRL IN
(25) CTRL OUT
-5.2V (AVEE)
(26) REF OUT
D/A OUT
(21) IOUT
64
64
(20) IOUT
(23) RSET
976
(19) ARTN
CLK (15)
(27) AGND
50
DGND (17, 28)
(22) AVEE
DVEE (18)
0.01F
0.01F
0.1F
0.1F
- 5.2V(AVEE)
- 5.2V(DVEE)
Functional Block Diagram
(LSB) D0
D1
D2
D3
8 LSBs
CURRENT
CELLS
D4
DATA
BUFFER/
LEVEL
SHIFTER
12-BIT
MASTER
REGISTER
D5
D6
R2R
NETWORK
ARTN
SLAVE
REGISTER
227
D7
227
D8
15
D9
15
UPPER
4-BIT
DECODER
D10
15
SWITCHED
CURRENT
CELLS
IOUT
(MSB) D11
IOUT
REF CELL
CLK
+
OVERDRIVEABLE
VOLTAGE
REFERENCE
AVEE
AGND
DVEE
2
DGND
VCC
-
REF OUT
RSET
25
CTRL
IN
CTRL
OUT
HI5735
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage VCC to DGND . . . . . . . . . . . . . . . . . . . +5.5V
Negative Digital Supply Voltage DVEE to DGND . . . . . . . . . . -5.5V
Negative Analog Supply Voltage AVEE to AGND, ARTN. . . . . -5.5V
Digital Input Voltages (D11-D0, CLK) to DGND . . . . . DVCC to -0.5V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . 2.5mA
Voltage from CTRL IN to AVEE . . . . . . . . . . . . . . . . . . . . 2.5V to 0V
Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . 2.5mA
Reference Input Voltage Range. . . . . . . . . . . . . . . . . .-3.7V to AVEE
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Thermal Resistance (Typical, Note 1)
JA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range
HI5735KCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
AVEE , DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, VREF = Internal TA = 25oC for All Typical Values
Electrical Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
12
-
-
Bits
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
(Note 4) (“Best Fit” Straight Line)
-
0.75
1.5
LSB
Differential Linearity Error, DNL
(Note 4)
-
0.5
1.0
LSB
Offset Error, IOS
(Note 4)
-
20
75
A
Full Scale Gain Error, FSE
(Notes 2, 4)
-
1
10
%
Offset Drift Coefficient
(Note 3)
-
-
0.05
A/oC
-
20.48
-
mA
(Note 3)
-1.25
-
0
V
Throughput Rate
(Note 5)
80
-
-
MSPS
Output Voltage Full Scale Step
Settling Time, tSETT Full Scale
To 0.5 LSB Error Band RL = 50
(Note 3)
-
20
-
ns
Single Glitch Area, GE (Peak)
RL = 50(Note 3)
-
5
-
pV-s
-
3
-
pV-s
Full Scale Output Current, IFS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Doublet Glitch Area, (Net)
Output Slew Rate
RL = 50DAC Operating in Latched Mode
(Note 3)
-
1,000
-
V/s
Output Rise Time
RL = 50DAC Operating in Latched Mode
(Note 3)
-
675
-
ps
Output Fall Time
RL = 50DAC Operating in Latched Mode
(Note 3)
-
470
-
ps
Differential Gain
RL = 50 (Note 3)
-
0.15
-
%
Differential Phase
RL = 50 (Note 3)
-
0.07
-
Deg
Spurious Free Dynamic Range to Nyquist
(Note 3)
fCLK = 40MHz, fOUT = 2.02MHz, 20MHz Span
-
70
-
dBc
fCLK = 80MHz, fOUT = 2.02MHz, 40MHz Span
-
70
-
dBc
REFERENCE/CONTROL AMPLIFIER
3
HI5735
AVEE , DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, VREF = Internal TA = 25oC for All Typical Values
Electrical Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Internal Reference Voltage, VREF
(Note 4)
-1.27
-1.23
-1.17
V
Internal Reference Voltage Drift
(Note 3)
-
50
-
V/oC
Internal Reference Output Current Sink/Source
Capability
(Note 3)
-125
-
+50
A
Internal Reference Load Regulation
IREF = 0 to IREF = -125A
-
50
-
V
Input Impedance at REF OUT pin
(Note 3)
-
1.4
-
k
Amplifier Large Signal Bandwidth (0.6VP-P)
Sine Wave Input, to Slew Rate Limited (Note 3)
-
3
-
MHz
Amplifier Small Signal Bandwidth (0.1VP-P)
Sine Wave Input, to -3dB Loss (Note 3)
-
10
-
MHz
Reference Input Impedance
(Note 3)
-
12
-
k
Reference Input Multiplying Bandwidth (CTL IN)
RL = 50, 100mV Sine Wave, to -3dB Loss at IOUT
(Note 3)
-
200
-
MHz
DIGITAL INPUTS (D9-D0, CLK, INVERT)
Input Logic High Voltage, VIH
(Note 4)
2.0
-
-
V
Input Logic Low Voltage, VIL
(Note 4)
-
-
0.8
V
Input Logic Current, IIH
(Note 4)
-
-
400
A
Input Logic Current, IIL
(Note 4)
-
-
700
A
Digital Input Capacitance, CIN
(Note 3)
-
3.0
-
pF
TIMING CHARACTERISTICS
Data Setup Time, tSU
See Figure 1 (Note 3)
3.0
2.0
-
ns
Data Hold Time, tHLD
See Figure 1 (Note 3)
0.5
0.25
-
ns
Propagation Delay Time, tPD
See Figure 1 (Note 3)
-
4.5
-
ns
CLK Pulse Width, tPW1, tPW2
See Figure 1 (Note 3)
3.0
-
-
ns
POWER SUPPLY CHARACTERISITICS
IEEA
(Note 4)
-
42
50
mA
IEED
(Note 4)
-
70
85
mA
ICCD
(Note 4)
-
13
20
mA
Power Dissipation
(Note 4)
-
650
-
mW
Power Supply Rejection Ratio
VCC 5%, VEE 5%
-
5
-
A/V
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 1.28mA). Ideally the
ratio should be 16.
3. Parameter guaranteed by design or characterization and not production tested.
4. All devices are 100% tested at 25oC. 100% production tested at temperature extremes for military temperature devices, sample tested for
industrial temperature devices.
5. Dynamic Range must be limited to a 1V swing within the compliance range.
4
HI5735
Timing Diagrams
50%
CLK
GLITCH AREA = 1/2 (H x W)
V
D11-D0
HEIGHT (H)
1/2 LSB ERROR BAND
IOUT
t(ps)
WIDTH (W)
tPD
tSETT
FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM
tPW1
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
tPW2
50%
CLK
tSU
tSU
tHLD
tSU
tHLD
tHLD
D11-D0
tPD
IOUT
tPD
tPD
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
5
HI5735
Typical Performance Curves
-1.21
680
CLOCK FREQUENCY DOES NOT
ALTER POWER DISSIPATION
-1.23
(V)
(mW)
640
-1.25
600
-1.27
-1.29
560
-50
-30
-10
10
30
50
70
90
-50
-30
-10
10
30
50
70
90
TEMPERATURE
TEMPERATURE
FIGURE 4. TYPICAL POWER DISSIPATION OVER
TEMPERATURE
FIGURE 5. TYPICAL REFERENCE VOLTAGE OVER
TEMPERATURE
1.5
0.8
0.5
(LSB)
(LSB)
0.4
0.0
-0.5
-0.4
-0.8
1.5
0
600
1200
1800
2400
3000
3600
400
4200
1000
CODE
1600
2200
CODE
2800
3400
4000
FIGURE 7. TYPICAL DNL
FIGURE 6. TYPICAL INL
ATTEN 20dB
RL -10.0dBm
10dB/
MKR -87.33dB
-73kHz
fC = 10 MSPS
28
(A)
24
S
20
16
C
12
-40
-20
-0
20
40
60
80
100
CENTER 1.237MHz
SPAN 2.000MHz
TEMPERATURE
FIGURE 8. OFFSET CURRENT OVER TEMPERATURE
6
FIGURE 9. SPURIOUS FREE DYNAMIC RANGE = 87.3dBc
HI5735
Pin Descriptions
PIN NUMBER
1-12
PIN NAME
PIN DESCRIPTION
D11 (MSB) thru Digital Data Bit 11, the Most Significant Bit thru Digital Data Bit 0, the Least Significant Bit.
D0 (LSB)
15
CLK
Data Clock Pin DC to 80 MSPS.
13, 14
NC
No Connect.
16
VCC
Digital Logic Supply +5V.
17, 28
DGND
Digital Ground.
18
DVEE
-5.2V Logic Supply.
23
RSET
External resistor to set the full scale output current. IFS = 16 x (VREF OUT / RSET). Typically 976.
27
AGND
Analog Ground supply current return pin.
19
ARTN
Analog Signal Return for the R/2R ladder.
21
IOUT
Current Output Pin.
20
IOUT
Complementary Current Output Pin.
22
AVEE
-5.2V Analog Supply.
24
CTRL IN
Input to the current source base rail. Typically connected to CTRL OUT and a 0.1F capacitor to AVEE . Allows
external control of the current sources.
25
CTRL OUT
Control Amplifier Out. Provides precision control of the current sources when connected to CTRL IN such that
IFS = 16 x (VREF OUT / RSET).
26
REF OUT
-1.23V (typical) bandgap reference voltage output. Can sink up to 125A or be overdriven by an external
reference capable of delivering up to 2mA.
Detailed Description
Clocks and Termination
The HI5735 is a 12-bit, current out D/A converter. The DAC
can convert at 80 MSPS and runs on +5V and -5.2V supplies.
The architecture is an R/2R and segmented switching current
cell arrangement to reduce glitch. Laser trimming is employed
to tune linearity to true 12-bit levels. The HI5735 achieves its
low power and high speed performance from an advanced
BiCMOS process. The HI5735 consumes 650mW (typical)
and has an improved hold time of only 0.25ns (typical).
The internal 12-bit register is updated on the rising edge of
the clock. Since the HI5735 clock rate can run to 80 MSPS,
to minimize reflections and clock noise into the part, proper
termination should be used. In PCB layout clock runs should
be kept short and have a minimum of loads. To guarantee
consistent results from board to board, controlled impedance
PCBs should be used with a characteristic line impedance
ZO of 50.
Digital Inputs
To terminate the clock line, a shunt terminator to ground is
the most effective type at a 80 MSPS clock rate. A typical
value for termination can be determined by the equation:
The HI5735 is a TTL/CMOS compatible D/A. Data is latched
by a Master register. Once latched, data inputs D0 (LSB)
thru D11 (MSB) are internally translated from TTL to ECL.
The internal latch and switching current source controls are
implemented in ECL technology to maintain high switching
speeds and low noise characteristics.
Decoder/Driver
The architecture employs a split R/2R ladder and
Segmented Current source arrangement. Bits D0 (LSB) thru
D7 directly drive a typical R/2R network to create the binary
weighted current sources. Bits D8 thru D11 (MSB) pass thru
a “thermometer” decoder that converts the incoming data
into 15 individual segmented current source enables. This
split architecture helps to improve glitch, thus resulting in a
more constant glitch characteristic across the entire output
transfer function.
7
RT = ZO ,
for the termination resistor. For a controlled impedance
board with a ZO of 50, the RT = 50. Shunt termination is
best used at the receiving end of the transmission line or as
close to the HI5735 CLK pin as possible.
HI5735
DAC
ZO = 50
CLK
RT = 50
FIGURE 10. CLOCK LINE TERMINATION
HI5735
Rise and Fall times and propagation delay of the line will be
affected by the Shunt Terminator. The terminator should be
connected to DGND.
Noise Reduction
To reduce power supply noise, separate analog and digital
power supplies should be used with 0.1F and 0.01F
ceramic capacitors placed as close to the body of the
HI5735 as possible on the analog (AVEE) and digital (DVEE)
supplies. The analog and digital ground returns should be
connected together back at the device to ensure proper
operation on power up. The VCC power pin should also be
decoupled with a 0.1F capacitor.
Reference
The internal reference of the HI5735 is a -1.23V (typical)
bandgap voltage reference with 50V/oC of temperature drift
(typical). The internal reference is connected to the Control
Amplifier which in turn drives the segmented current cells.
Reference Out (REF OUT) is internally connected to the
Control Amplifier. The Control Amplifier Output (CTRL OUT)
should be used to drive the Control Amplifier Input (CTRL
IN) and a 0.1F capacitor to analog VEE . This improves
settling time by providing an AC ground at the current source
base node. The Full Scale Output Current is controlled by
the REF OUT pin and the set resistor (RSET). The ratio is:
IOUT (Full Scale) = (VREF OUT /RSET) x 16.
The internal reference (REF OUT) can be overdriven with a
more precise external reference to provide better
performance over temperature. Figure 11 illustrates a typical
external reference configuration.
HI5735
-1.25V
(26) REF OUT
R
-5.2V
FIGURE 11. EXTERNAL REFERENCE CONFIGURATION
Outputs
The outputs IOUT and IOUT are complementary current
outputs. Current is steered to either IOUT or IOUT in proportion
to the digital input code. The sum of the two currents is always
equal to the full scale current minus one LSB. The current
output can be converted to a voltage by using a load resistor.
Both current outputs should have the same load resistor (64
typically). By using a 64 load on the output, a 50 effective
output resistance (ROUT) is achieved due to the 227 (15%)
parallel resistance seen looking back into the output. This is the
nominal value of the R2R ladder of the DAC. The 50 output is
needed for matching the output with a 50 line. The load
resistor should be chosen so that the effective output resistance
(ROUT) matches the line resistance.
8
The output voltage is:
VOUT = IOUT x ROUT.
IOUT is defined in the reference section. IOUT is not trimmed
to 12 bits, so it is not recommended that it be used in
conjunction with IOUT in a differential-to-single-ended
application. The compliance range of the output is from 1.25V to 0V, with a 1VP-P voltage swing allowed within this
range.
TABLE 2. INPUT CODING vs CURRENT OUTPUT
INPUT CODE (D11-D0)
IOUT (mA)
IOUT (mA)
1111 1111 1111
-20.48
0
1000 0000 0000
-10.24
-10.24
0000 0000 0000
0
-20.48
Settling Time
The settling time of the HI5735 is measured as the time it
takes for the output of the DAC to settle to within a ±1/2 LSB
error band of its final value during a full scale (code 0000...
to 1111.... or 1111... to 0000...) transition. All claims made by
Intersil with respect to the settling time performance of the
HI5735 have been fully verified by the National Institute of
Standards and Technology (NIST) and are fully traceable.
Glitch
The output glitch of the HI5735 is measured by summing the
area under the switching transients after an update of the
DAC. Glitch is caused by the time skew between bits of the
incoming digital data. Typically, the switching time of digital
inputs are asymmetrical, meaning that the turn off time is
faster than the turn on time (TTL designs). Unequal delay
paths through the device can also cause one current source
to change before another. In order to minimize this, the
Intersil HI5735 employes an internal register, just prior to the
current sources, which is updated on the clock edge. Lastly,
the worst case glitch on traditional D/A converters usually
occurs at the major transition (i.e., code 2047 to 2048).
However, due to the split architecture of the HI5735, the
glitch is moved to the 255 to 256 transition (and every
subsequent 256 code transitions thereafter). This split R/2R
segmented current source architecture, which decreases the
amount of current switching at any one time, makes the
glitch practically constant over the entire output range. By
making the glitch a constant size over the entire output
range, this effectively integrates this error out of the end
application.
In measuring the output glitch of the HI5735 the output is
terminated into a 64 load. The glitch is measured at any
one of the current cell carry (code 255 to 256 transition or
any multiple thereof) throughout the DACs output range.
The glitch energy is calculated by measuring the area under
the voltage-time curve. Figure 13 shows the area considered
HI5735
as glitch when changing the DAC output. Units are typically
specified in picoVolt-seconds (pV-s).
HI5735
100MHz
LOW PASS
FILTER
(21) IOUT
50
Feedthru, is the measure of the undesirable switching noise
coupled to the output.
FIGURE 12. GLITCH TEST CIRCUIT
Applications
Output Voltage Full Scale Settling Time, is the time
required from the 50% point on the clock input for a full scale
step to settle within an 1/2 LSB error band.
Bipolar Applications
Output Voltage Small Scale Settling Time, is the time
required from the 50% point on the clock input for a 100mV
step to settle within an 1/2 LSB error band. This is used by
applications reconstructing highly correlated signals such as
sine waves with more than 5 points per cycle.
a (mV)
Glitch Area, GE, is the switching transient appearing on the
output during a code transition. It is measured as the area
under the curve and expressed as a picoVolt•Time
specification (typically pV•s).
GLITCH ENERGY = (a x t)/2
t (ns)
Differential Gain, AV, is the gain error from an ideal sine
wave with a normalized amplitude.
FIGURE 13. MEASURING GLITCH ENERGY
To convert the output of the HI5735 to a bipolar 4V swing, the
following applications circuit is recommended. The reference
can only provide 125A of drive, so it must be buffered to
create the bipolar offset current needed to generate the -2V
output with all bits “off”. The output current must be converted
to a voltage and then gained up and offset to produce the
proper swing. Care must be taken to compensate for the
voltage swing and error.
5k
REF OUT
(26)
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Differential Linearity Error, DNL, is the measure of the
error in step size between adjacent codes along the
converter’s transfer curve. Ideally, the step size is 1 LSB
from one code to the next, and the deviation from 1 LSB is
known as DNL. A DNL specification of greater than -1 LSB
guarantees monotonicity.
SCOPE
64
Definition of Specifications
-
+
+
1/2 CA2904
1/2 CA2904
0.1F
HI5735
60
240
240
50
IOUT
(21)
-
VOUT
+
HFA1100
FIGURE 14. BIPOLAR OUTPUT CONFIGURATION
9
Signal to Noise Ratio, SNR, is the ratio of a fundamental to
the noise floor of the analog output. The first 5 harmonics
are ignored, and an output filter of 1/2 the clock frequency is
used to eliminate alias products.
Total Harmonic Distortion, THD, is the ratio of the DAC
output fundamental to the RMS sum of the harmonics. The
first 5 harmonics are included, and an output filter of 1/2 the
clock frequency is used to eliminate alias products.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from a fundamental to the largest harmonically or
non-harmonically related spur. A sine wave is loaded into the
D/A and the output filtered at 1/2 the clock frequency to
eliminate noise from clocking alias terms.
-
5k
Differential Phase, , is the phase error from an ideal sine
wave.
Intermodulation Distortion, IMD, is the measure of the
sum and difference products produced when a two tone
input is driven into the D/A. The distortion products created
will arise at sum and difference frequencies of the two tones.
IMD can be calculated using the following equation:
20Log (RMS of Sum and Difference Distortion Products)
IMD = ------------------------------------------------------------------------------------------------------------------------------------------------------- .
 RMS Amplitude of the Fundamental 
HI5735
PASSIVATION:
Die Characteristics
Type: Sandwich Passivation Undoped Silicon Glass
(USG) + Nitride
Thickness: USG - 8kÅ, Nitride - 4.2kÅ
Total 12.2kÅ +2kÅ
DIE DIMENSIONS:
161.5 mils x 160.7 mils x 19 mils 1 mil
METALLIZATION:
Type: AlSiCu
Thickness: M1 - 8kÅ, M2 - 17kÅ
DIE ATTACH:
Silver Filled Epoxy
SUBSTRATE POTENTIAL (POWERED UP):
VEED
Metallization Mask Layout
D9
D10
D11
DGND
REF OUT
D8
AGND
HI5735
CTRL OUT
D7
CTRL IN
D6
RSET
D5
AVEE
D4
IOUT
D3
IOUT
D2
ARTN
D1
D0
10
CLK
DVCC
DGND
DVEE
HI5735
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
B S
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
0.05 BSC
10.00
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
28
0o
10.65
-
0.394

0.419
1.27 BSC
H
N
NOTES:
MAX
A1
e

MIN
28
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
-
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000
ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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11
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