an9626

Using The HI5741 Evaluation Module
TM
Application Note
July 1996
Introduction
AN9626
incoming 4 bits to 15 control lines to enable the most
significant current sources.
The HI5741 is a 14-bit 100MHz Digital to Analog Converter.
This current out DAC is designed for low glitch and high
Spurious Free Dynamic Range operation. As a result, this
DAC is ideally suited for Signal Reconstruction and DDS
(Direct Digital Synthesis) applications due to its inherent low
noise design.
As shown in Figure 2, the thermometer decoder translates
the 4 bit binary input data into a decode that enables
individual current sources. For example, a binary code of
0110 on the data bits D10 through D13 will enable current
sources I1, I2, I3, I4, I5, and I6. The thermometer decoding
architecture ensures good differential non-linearity, which is
further enhanced by the addition of laser trimming. Also,
compared to a straight R/2R design, the worst case glitch is
greatly reduced since creating the MSB current is the sum of
current sources I1 through I8. Overall glitch is therefore
reduced by a factor of 16. This also reduces the theoretical
switching skew from current source to current source by
using identically sized switches with identical gain, leakage,
and transient responses.
Architecture
The HI5741 DAC is designed with a split architecture to
minimize glitch while maximizing linearity. Figure 1 shows
the functional architecture of the device. The 10 least
significant bits of the converter are derived by a traditional
R/2R network to binarily weight the 1.28mA (nominal)
current sources. The upper 4, or most significant bits, are
implemented as segmented or thermometer decoded
current sources. The thermometer decoder converts the
(LSB) D0
D1
D2
D3
D4
10 LSBs
CURRENT
CELLS
D5
14-BIT
MASTER
REGISTER
D6
D7
DATA
BUFFER/
LEVEL
SHIFTER
R/2R
NETWORK
SLAVE
REGISTER
D8
D9
D10
D11
15
SWITCHED
CURRENT
CELLS
UPPER
4-BIT
DECODER
D12
IOUT
IOUT
(MSB) D13
REF CELL
CLK
AGND
DVEE
DGND
CTRL AMP
OUT
-
REF OUT
VCC
25Ω
+
OVERDRIVEABLE
VOLTAGE
REFERENCE
AVEE
CTRL AMP
IN
RSET
FIGURE 1. HI5741 BLOCK DIAGRAM
3-1
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Application Note 9626
V
I15
BIT 13 (MSB)
I14
BIT 12
I13
GLITCH AREA = 1/2 (H x W)
HEIGHT (H)
I12
BIT 11
t(ps)
WIDTH (W)
I11
FIGURE 3. GLITCH AREA
BIT 10
I10
Since the glitch is a transient event, this leads designers to
believe that a simple low pass filter can be used to eliminate
or reduce the size of the glitch. In effect, low pass filtering a
glitch tends to “smear” the event and does little to remove
the energy of the transient.
I9
I8
4-BIT BINARY
TO
THERMOMETER
DECODER
I7
Input Timing/Logic Levels
I6
The HI5741 has a maximum clock rate specification of
100MHz. The data setup time before the 50% point of the
rising edge of the clock is tS = 3ns (Min) and the hold time is
tH = 0.5ns (Min). Logic levels are 0.8V (Max) for an input low
and 2.0V (Min) for a logic high. The HI5741 is both TTL and
CMOS input compatible.
I5
I4
I3
I2
I1
D11 - D0
CLK
SUMMING
JUNCTION (IOUT)
tS
FIGURE 2. THERMOMETER DECODER
tH
FIGURE 4. HI5741 DATA TIMING
Designing to Minimize Glitch
One cause of Glitch is the time skew between bits of the
incoming digital data. Typically the switching time of digital
inputs are asymmetrical, meaning that the turn off time is
faster than the turn on time. Unequal delay paths through the
device can cause one current source to change before
another. To minimize this, the Intersil HI5741 employes an
internal register just prior to the current sources which is
updated on the rising clock edge. In traditional DACs the
worst case glitch usually occurs at the major transition i.e.,
01 1111 1111 1111 to 10 0000 0000 0000. But in the HI5741
the worst case glitch is moved to the 00 0011 1111 1111 to
11 1100 000 0000 transition. This is achieved by the split
R/2R segmented current source architecture. This
decreases the amount of current switching at any one time
and reduces the glitch by a factor of 16.
3-2
Integral Linearity
The HI5741 has a full-scale range of 20.48mA. When driving
a 64Ω load the full scale voltage swing is 0V to -1V (the
internal 227Ω ladder resistance in parallel with the 64Ω load
results in an equivalent 50Ω load resistance). Most video
and communication applications use a 1VP-P voltage swing
which yields 20.48mA full scale current sink capability. With
a 1VP-P voltage swing on the HI5741 output an LSB is:
LSB = Full Scale Range/(2N-1)
where N is the number of bits and the Full Scale Range is
1VP-P.
The LSB size for this application is 62.5µV. To determine the
Integral Linearity of the HI5741 the bit weights of each major
transition is taken. The Best Fit Straight Line method is used
to calculate the overall INL. Measurements are taken at bits
0 through 9 at each bit transition. Then all combinations of
the upper 4 bits are measured. Finally some worst case
codes are measured and the full scale is measured. Once
this is completed a best fit straight line is drawn through the
data points and the worst case deviation is determined.
Application Note 9626
The worst case integral linearity of the HI5741 is specified to
be less than 1.5 LSB. The implementation of laser trim
assures 14-bit match from current cell to current cell.
Figure 5 graphically illustrates the typical linearity
performance of the HI5741.
Shown in Figure 6, as the input code increases the output
voltage should increase. When an error of -1.0 LSB or less is
incurred, that bit can be assumed to be a missing code since
the output did not increase but rather remained the same.
INPUT CODE GREATER THAN ZERO
1.5
11
1.0
GREATER THAN
-1.0 LSB
ERROR
0.5
LSB
10
(MISSING CODE)
0
01
-0.5
-0.5 LSB ERROR
-1.0
OUTPUT
VOLTAGE
00
FIGURE 6. DNL EXAMPLE
-1.5
0
5000
10,000
15,000
The Control Amplifier
CODE
FIGURE 5A. INL TYPICAL PERFORMANCE CURVE
0.8
The internal control amplifier converts the reference voltage
appearing on the REFOUT pin to a reference current via the
circuit shown in Figure 7A. The bias voltage generated at the
control amplifier output is used to mirror this current in all of
the precision current cells.
0.5
LSB
0.25
RSET
0
CONTROL
AMPOUT
+
REFOUT
-
-0.25
VEE
FIGURE 7A.
-0.5
-0.8
Adjusting Full Scale
0
5000
10,000
15,000
CODE
FIGURE 5B. DNL TYPICAL PERFORMANCE CURVE
Differential Linearity and Missing Codes
For a D/A Converter, the differential non-linearity is the worst
case deviation from the ideal step size throughout the entire
transfer curve. For the HI5741, this worst case deviation is
said to be at most 1.0 LSB in magnitude. For any given D/A
converter o guarantee no missing codes the converter must
be monotonic.
The definition of monotonicity is; as the input code is
increased the output should increase. When an input code is
increased and the output of the DAC does not increase or
reverses direction, then this converter is assumed to be nonmonotonic, or missing codes.
Monotonicity is guaranteed as long as a DNL value of
greater than -1.0 LSB is maintained.
3-3
The RSET pin is used to set the Full Scale Output Current.
The output current is a function of the reference voltage
applied to the CONTROL AMP IN pin and the value of the
RSET resistor. To calculate the IOUT Full Scale Current use
the following formula:
IOUT Full Scale = 16 x (REFOUT/RSET)
So where REFOUT = -1.20V
and RSET = 931Ω
IOUT = -20.62mA
To adjust the output full scale current, use a potentiometer in
rheostat mode as shown in Figure 7B.
The Evaluation Board
The HI5741 Evaluation board is a 1/2 size daughter board
designed to interface to the HSP-EVAL board. When used
together these boards create a flexible and powerful DDS
system. The HSP45116 board is used to generate the high
speed digital sine wave patterns for the D/A module. The
Application Note 9626
The fundamental of a pure 1MHz tone should appear as an
impulse in the frequency domain at 1MHz. In a sampled
system noise terms are produced near the sampling
frequencies called aliases. These aliases are related to the
fundamental in that they are located at ±fN around the
sampling frequency as shown in Figure 9.
RSET (17)
100Ω
909Ω
0
FUNDAMENTAL
(PURE TONE)
FIGURE 7B. FULL SCALE OUTPUT APPLICATION CIRCUIT
HI5741 board reconstructs the incoming digital data to an
analog representation that can be analyzed on a spectrum
analyzer or oscilloscope.
Plugging In
AMPLITUDE
(dB)
-50
NOISE FLOOR
-85
After setting-up the HSP45116 board and the HI5741 board;
power should be applied to the banana jacks. A +5V, and a
-5.2V supply will be needed. To reduce noise the power
supply leads should be twisted pairs.
Connect the interface cable to an IBM PC or compatible’s
parallel port. Power should be applied to the board and then
run the software directly from floppy disk. To run the software
place the floppy disk into drive A: and type:
f
1MHz
fN
FIGURE 8. FREQUENCY PLOT OF 1MHz TONE
FUNDAMENTAL
0
SAMPLING FUNCTION
(SIN X)/X
AMPLITUDE
(dB)
-50
A: NCOMCTRL
the HSP45116 Control Panel will be loaded. To exercise the
board the following parameters should be set:
BINFMT = 0
ALIAS
(fS - 1MHz)
-85
and then set the Center Frequency to:
CENTER FREQUENCY = 01000000HEX
where the center frequency is in hex. At this point the output
of the HI5741 DAC module should be converting a sine wave
at 48kHz. Connect the output of the HI5741 module to an
oscilloscope.
DDS Interface
The HSP45116 board is a TTL/CMOS compatible logic
board. The HI5741 is a TTL/CMOS compatible logic D/A
converter. The design of the DAC module is to interface to
the 14 Most Significant Bits of the NCO. The HI5741 module
should be plugged into P2 of the HSP-EVAL board.
Spurious Free Dynamic Range
The Spurious Free Dynamic Range of the HI5741 DAC is the
most important specification for communication applications.
This specification shows how Integral Linearity, Glitch, and
Switching noise affect the spectral purity of the output signal.
Several important things must be noted first.
When a quantized signal is reconstructed, certain artifacts
are created. Let’s take the example of trying to recreate a
1MHz sine wave with a 1VP-P output. In the frequency
domain the fundamental should appear at 1MHz as shown in
Figure 8.
3-4
f
1MHz
fN
4MHz
fS
FIGURE 9. SAMPLING ALIAS PRODUCTS
So for a 1MHz fundamental and a 5MHz sampling rate an
alias term is created at 4MHz and 6MHz. A (SIN)/X function
shaping is also induced by sampling a signal. Aliases
continue up through the frequency spectrum repeating around
the sampling frequency and its harmonics (i.e., 2fS, 3fS, 4fS).
Also, when dealing with devices that posses high degrees of
dynamic range such as the HI5741, one must contend with
some fundamental limitations of the measurement system
being used. Since the HI5741 typically meets (and in some
cases exceeds) the dynamic range of the spectrum analyzer
used to evaluate the device, the use of a notch filter can greatly
alleviate the burden being placed on the equipment. By filtering
out the fundamental, and in the process eliminating a large
percentage of the power as seen by the spectrum analyzer, one
can bring to bear the full dynamic range of the equipment,
therefore truly evaluating the dynamic range of the DAC. Refer
to Application Note AN9619 “Optimizing Setup Conditions for
High Accuracy Measurements of the HI5741” for further details
on the use of filtering for evaluation purposes.
A reconstructed sine wave out of the HI5741 is not ideal and
as such has harmonics of the fundamental. The difference
between the magnitude of the fundamental and the highest
Application Note 9626
noise spur whether it is harmonically related to the
fundamental or not, is the definition of Spurious Free
Dynamic Range. Figures 10 through 15 are sample plots
taken of the HI5741 at various frequencies. In all the cases
presented, the fundamental has been notched out to make
maximum use of the dynamic range of the spectrum
analyzer. Oscilloscope plots of the unfiltered signals are also
included.
Typical Performance Curves
0
SFDR = 80.17dBc
-10
-20
-30
dB
-40
-50
-60
-70
-80
-90
CH1 200mV~
M 100ns
-100
START 500kHz
FIGURE 10A. OSCILLOSCOPE PLOT
FIGURE 10B. SAMPLE PLOT
f CLK
FIGURE 10. A 1MHz FUNDAMENTAL TO -------------- . fCLK = 20MHz
2
0
-10
SFDR = 86.83dBc
-20
dB
-30
-40
-50
-60
-70
-80
-90
-100
CENTER 1.000MHz
SPAN 1.000MHz
FIGURE 11. A 1MHz FUNDAMENTAL ON A 1MHz SPAN UNFILTERED
3-5
STOP 10.000MHz
Application Note 9626
Typical Performance Curves
(Continued)
0
SFDR = 87.67dBc
-10
-20
-30
dB
-40
-50
-60
-70
-80
-90
CH1 200mV
M 50.0ns
-100
START 500kHz
FIGURE 12A. OSCILLOSCOPE PLOT
STOP 10.000MHz
FIGURE 12B. SAMPLE PLOT
f CLK
FIGURE 12. A 5MHz FUNDAMENTAL TO -------------- . fCLK = 20MHz
2
0
SFDR = 79.34dBc
-10
-20
-30
dB
-40
-50
-60
-70
-80
-90
CH1 200mV~
M 100ns
-100
START 500kHz
FIGURE 13A. OSCILLOSCOPE PLOT
FIGURE 13B. SAMPLE PLOT
f CLK
FIGURE 13. A 1MHZ FUNDAMENTAL TO -------------- . FCLK = 40MHZ
2
3-6
STOP 20.00MHz
Application Note 9626
Typical Performance Curves
(Continued)
0
SFDR = 86.83dBc
-10
-20
dB
-30
-40
-50
-60
-70
-80
-90
-100
CENTER 1.000MHz
SPAN 1.000MHz
FIGURE 14. A 1MHz FUNDAMENTAL ON A 1MHz SPAN UNFILTERED
0
SFDR = 75.34dBc
-10
-20
dB
-30
-40
-50
-60
-70
-80
-90
CH1 200mV~
M 50.0ns
-100
START 500kHz
FIGURE 15A. OSCILLOSCOPE PLOT
STOP 20.00MHz
FIGURE 15B. SAMPLE PLOT
f CLK
FIGURE 15. A 5MHz FUNDAMENTAL TO -------------- . fCLK = 40MHz
2
Using the HSP-EVAL Test Platform
Center FrequencyHEX = (Desired Frequency/25MHz) x 232
The HSP-EVAL DDS platform allows quick testing of spectral
properties of a given DAC. The Numerically Controlled
Oscillator/Modulator (NCOM) generates digital sinewave
patterns that are loaded into the DAC. The analog output of
the DAC is the reconstructed sinewave pattern. The program
NCOMCTRL allows downloading of the desired center
frequency. The clock or sampling frequency is 25MHz. To
determine the center frequency codeword the following
formula is used:
This 32-bit hexadecimal word will create the fundamental. In
order to ensure zero phase offset the cursor should be
moved to the LOAD select. Pressing the spacebar the value
should be toggled from 1 to 0 and back to 1 again. This will
ensure that any previous values in the phase register are
cleared and the sinewave pattern is started at zero phase.
3-7
The HSP-EVAL setup is powered from the DAC module
power-supply banana jacks. The output of the setup can be
observed on an oscilloscope or a spectrum analyzer.
Application Note 9626
Evaluating Multi-Tone Power Ratio (MTPR)
Performance
For cellular base station users, the HI5741 evaluation
module provides accessibility to the digital inputs via the
edge connector. Unlike DDS applications, base station users
provide multi-tone inputs to the DAC, and evaluate the
dynamic range performance under these conditions.
Figures 17 and 18 graphically illustrate two examples of test
patterns used to evaluate MTPR performance on the
HI5741. In figure 17, a ten tone pattern is used with tones
ranging from 2MHz to 3MHz with 100kHz tone spacing.
Figure 18 illustrates a similar pattern, however 40kHz tone
spacing is used. In both cases, the fifth tone has been
removed to observe the third order harmonic products and
the amount of distortion they introduce into the spectrum.
In testing for MTPR, a ten tone pattern is created and input
to the HI5741 at a clock frequency of 20MHz. One tone
(typically the fifth) is removed in order to observe the third
order harmonic products (2f1-f2, 2f2-f1,etc.) created by the
DAC in the resulting ‘dead zone’. The multi-tone power ratio
of the device is then measured as the dynamic range from
peak power to peak distortion.
HI5741
DAC MODULE
HSP-EVAL/HPS45116
NCOM EVALUATION BOARD
CLOCK
CIRCUIT
HSP45116
NUMERICALLY
CONTROLLED
OSCILLATOR
HI5741
DAC
PC INTERFACE
50Ω
SMA
CABLE
-5.2V
+5V
POWER
SUPPLY
SOFTWARE
INCLUDED
SPECTRUM ANALYZER
PERSONAL COMPUTER
FIGURE 16. INTERSIL HI5741/DDS EVALUATION SYSTEM SETUP BLOCK DIAGRAM
3-8
Application Note 9626
Test Patterns
0
MTPR = 77.17dBc
-10
-20
-30
dB
-40
-50
-60
-70
-80
-90
CH1 200mV
M 2.00µs
-100
START 1.500MHz
FIGURE 17A. SCOPE PLOT OF MTPR TEST WAVEFORM
STOP 3.500MHz
FIGURE 17B. MTPR PERFORMANCE
0
MTPR = 81.83dBc
-10
-20
-30
dB
-40
-50
-60
-70
-80
-90
CH1 200mV
M 200µs
-100
START 1.9500MHz
FIGURE 17C. SCOPE PLOT OF MTPR TEST WAVEFORM
3-9
STOP 2.4000MHz
FIGURE 17D. MTPR PERFORMANCE
Schematic Diagram
VCCD
J1A
J1B
DB0
DB2
DB4
3-10
DB7
DB9
DB11
DB13
GND
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DB1
DB3
DB5
DB6
DB8
DB10
DB12
GND
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NOTES:
1. All passive components are SMT devices, except
polarized capacitors.
2. Place ground shapes on top and bottom layers. Use split
planes for analog, digital and power.
R19
0Ω
SMA
J3
R20
50Ω
R18
200Ω
CLK
R17
R16
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
200Ω
200Ω
200Ω
200Ω
200Ω
200Ω
200Ω
200Ω
200Ω
200Ω
200Ω
200Ω
200Ω
DVDD
DVEE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
16
18
17
28
CLK
IOUT
D0 (LSB)
IOUTB
D1
COMPIN
D2
COMPOUT
D3
REFOUT
D4
RSET
D5
ARET
D6
AVSS
D7
AVEE
D8
D9
HI5741
D10
D11
D12
D13 (MSB)
DVDD
DVEE
DVSS
DVSS
21
20
24
25
26
23
19
27
22
R2
64Ω
R1
64Ω
R3
976Ω
GND
GND
C1
0.1µF
C9
0.01µF
GND
GND
SMA
J2
AVEE
AVEE
C10
10.0µF
C4
0.1µF
C5
0.01µF
GND
GND
GND
DVDD
+5V
DVDD
C6
10µF
C312
0.1µF
C313
0.01µF
GND
GND
NOTE: Place as close to device pin 22 as possible.
SYSTEM GND
C7
10µF
VEE
ECL SUPPLY
-5.2V
DVEE
R20
GND
10Ω
GND
GND
C2
0.1µF
C3
0.01µF
GND
GND
NOTE: Place as close to device pin 18 as possible.
FIGURE 18.
Application Note 9626
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
J1C
Application Note 9626
FIGURE 19A. SILKSCREEN
FIGURE 19B. LAYER 1
FIGURE 19C. LAYER 2
3-11
Application Note 9626
FIGURE 19D. LAYER 3
FIGURE 19E. LAYER 4
FIGURE 19F. SILKSCREEN
3-12
Application Note 9626
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
3-13
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Mercure Center
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1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
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Republic of China
TEL: (886) 2 2716 9310
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