an9821

HI5760EVAL1 Evaluation Board User’s Manual
TM
Application Note
October 1998
AN9821.1
Description
Features
The HI5760EVAL1 evaluation board provides a quick and
easy method for evaluating the HI5760, 125 MSPS high
speed DAC. The converter outputs a current into a load
resistor to form a voltage which can be measured by using
the included SMA connector. The amount of current out of
the DAC is determined by an external resistor and either an
internal or external reference voltage. The CMOS digital
inputs have optional external termination resistors. The
evaluation board also includes a VME digital interface that is
compatible with the HSP-EVAL board, so DDS (Direct Digital
Synthesis) can be performed with minimal setup time.
• HI5760, 125 MSPS CMOS DAC
• Simple and Easy to Use
• Standard VME/DSP Interface, HSP-EVAL Compatible
• SMA Outputs
• Easily Selectable Internal or External Reference
Applications
• Single or Multi-Carrier Tone Generation
• Modulated Carrier Generation
• General DAC Performance Evaluation
Ordering Information
PART
NUMBER
TEMP.
RANGE (oC)
PACKAGE
CLOCK
SPEED
HI5760EVAL1
25
Evaluation Platform
125MHz
• Amplitude Modulation Via External Reference
Functional Block Diagram
DVDD
P1
AVDD
U1
VME
96PIN
CONNECTOR
IOUTA
SMA2
10 BITS
HI5760
DAC
IOUTB
SMA3
CLOCK
REF SELECT
J2
AVDD
J1
SLEEP
EXTERNAL
REFERENCE
(OPTIONAL)
SMA1
3-1
J3
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright
© Intersil Corporation 2000
Application Notes 9821
Functional Description
Voltage Reference
The HI5760 has an internal 1.2V voltage reference with a
±60ppm/oC drift coefficient over the full temperature range
of the converter. The REFLO pin (16) selects the reference.
Access to pin 16 is provided through the center pin of
Jumper J2. To enable the internal reference, it is necessary
that the jumper be placed such that pin 16 is grounded (if
facing the evaluation board so that the SMAs are on the
user’s left-hand side, then the jumper should be placed in
the ‘right’ position of the three-stemmed jumper). The
REFIO pin (17) provides access to the internal voltage
reference, or can be overdriven if the user wishes to use an
external source for the reference. Notice that a 0.1µF
capacitor is placed as close as possible to the REFIO pin.
This capacitor is necessary for ensuring a noise free
reference voltage. If the user wishes to use an external
reference voltage, jumper J3 must be in place and an
external voltage reference provided via SMA1, labeled
‘EXT REF’. The recommended limits of the external
reference are between 15mV and 1.2V. Performance of the
converter can be expected to decline as the reference
voltage is reduced due to the reduction in LSB voltage size.
If the user wants to amplitude modulate the DAC, they can
overdrive the REFIO pin with a waveform. The input
multiplying bandwidth of the REFIO input is approximately
1.4MHz. It is necessary that the multiplying signal be DC
offset so that the minimum and maximum peaks of the
signal do not exceed the limits imposed above. Jumper J2
must be changed so that pin 16 is tied high (the supply
voltage, which is the ‘left’ position of J2) when using an
external reference. The output current of the converter,
IOUTA and IOUTB, is a function of the voltage reference
used and the value of RSET (R14 on the schematic).
Outputs
The output current of the device is set by choosing RSET
and VREF such that the resultant of the following equation is
between 2mA and 20mA:
IOUT = 32 x VREF/RSET.
For example, using the internal VREF of 1.2V and an RSET
(R14 on the schematic) value of 1.91kΩ results in an IOUT
of approximately 20mA (maximum allowed). Choose the
output loading so that the ‘Output Voltage Compliance
Range’ is not violated (0 to 1.25V). If an external VREF is
chosen, it should not exceed +1.2V.
The output can be configured to drive a load resistor, a
transformer, an operational amplifier, or any other type of
output configuration so long as the output voltage
compliance range and the maximum output current is not
violated.
3-2
Load Resistor Output
The evaluation board comes with the simple resistor load
output configuration. Both IOUTA and IOUTB have a 50Ω
resistor connected to ground next to their respective SMAs.
See the attached schematic for clarification.
Sleep
The converter can be put into ‘sleep’ mode by connecting pin
15 to either of the converter’s supply voltages. For normal
operation, it is recommended that pin 15 be tied to ground.
However, the sleep pin does have an active pulldown
current, so the pin can be left disconnected for normal
operation. On the evaluation board, jumper J1 is provided for
controlling the sleep pin. Remove the jumper from J1 for
normal operation and replace it for sleep mode.
Power Supply(s) and Ground(s)
The user can operate from either a single supply or dual
supplies. The DAC is designed to function with the digital
and analog voltages at the same value. The evaluation
board contains two power supply connections to allow for
measuring the current drawn from the digital and analog
sections independently. For single supply mode, it is
recommended that a single power supply wire be attached
to either DVDD1 or AVDD1, and then a jumper wire placed
from E2 to E3 (holes). A single ground wire should be
attached to either DCOM1 or ACOM1 from the power supply.
These grounds are identical, as the evaluation board uses a
single ground plane. The user can select to use dual ground
planes in their design connected at a single point near the
converter (this is the recommended configuration). For dual
supply mode, connect a power supply wire to both AVDD1
and DVDD1 and ground wires to DCOM1 and ACOM1
independently.
Getting Started
A summary of the external supplies, equipment, and signal
sources needed to operate the board is given below:
1. +5V for HI5760.
2. Data generator capable of generating 10-bit patterns. The
HSP-EVAL with the HSP45116 NCOM daughter board is
an option (see ‘Learning Your Way Around’).
3. Square wave clock source (usually part of the Data
Generator).
4. Spectrum analyzer or oscilloscope for viewing the output
of the converter.
Attach a +5V power supply to the evaluation board. Connect
the 10 input bits from the data generator to the evaluation
board, preferably by using a male, 64 or 96-pin VME (Versa
Module Eurocard) connector that mates with the eval board.
Connect the clock source to the eval board, also preferably
through the 64-pin connector. Failure to make clean and
short connections to the data input lines and clock source
will result in a decrease in spectral performance.
Application Notes 9821
Using a coaxial cable with the proper SMA connector, attach
the output of the converter, either IOUTA or IOUTB, to the
measurement equipment that will be evaluating the
converter’s performance. Make sure that the jumpers are in
their proper placement. Consult the ‘Voltage Reference’
section and the ‘Sleep’ section of this document for a
definition of the jumpers’ functionality. Optimum singleended performance is usually achieved by either grounding
or equally terminating the unused output so that its loading
matches that of the output being measured.
3. HSP-EVAL Board with the HSP45116 NCOM Daughter
Board attached and included software, NCOMCTRL (or a
data/pattern generator).
4. Personal computer with a parallel port.
5. 50Ω SMA cable.
Two +5V power supplies. One for the DAC Eval Board and
one for the HSP Eval Board.
Connections
Note: If the HSP-EVAL Board is to be used, it is highly
recommended that the user obtain the User’s Manual, the
datasheet for the HSP45116 NCOM, and the User’s Manual for
the HSP45116-DB. This platform is capable of testing the
converter up to 25 MSPS, which is the speed of the
HSP-EVAL’s on-board clock. The user can choose to substitute
this clock with a slower one, but the DSP chip and DSP Eval
Board are only designed to work at a maximum of 25MHz (a
52MHz version of this DSP chip does exist but not in this
evaluation platform; see the HSP45116A). For testing of the
HI5760 at higher speeds, it is recommended that the user
obtain a high speed data generator capable of generating 10-bit
patterns at clock speeds up to at least 125MHz.
Learning Your Way Around
Direct Digital Synthesis
To ensure that everything on the board is configured
properly and functional, it is suggested that the following test
be performed. The board test requires:
1. HI5760 Evaluation Board.
2. Spectrum analyzer.
HSP-EVAL/HSP45116
NCOM EVALUATION BOARD
OR A DATA GENERATOR
CLOCK
CIRCUIT
HI5760EVAL1
DAC MODULE
HSP-EVAL/HSP45116DB
NUMERICALLY
CONTROLLED
OSCILLATOR
EVAL KIT
HI5760
DAC
PC INTERFACE
+5V
POWER
SUPPLY
50Ω
SMA
CABLE
+5V
POWER
SUPPLY
SOFTWARE
INCLUDED
WITH HSP-EVAL
SPECTRUM ANALYZER
PERSONAL COMPUTER
FIGURE 1. INTERSIL HI5760/DDS EVALUATION SYSTEM SETUP BLOCK DIAGRAM
3-3
Application Notes 9821
HSP-Eval Setup for DDS
Appendix A Description of Architecture
Attach the HSP-EVAL and the HSP45116 Daughter Board
together. Consult their respective user manuals for details.
Connect the HI5760EVAL1 board to the P2 connector of
the HSPEVAL board. Then connect these to an IBM
compatible PC via the parallel port. Provide power to both
boards. To run the software (NCOMCTRL) that
accompanied the HSP evaluation kit, place the diskette into
the A: drive of the PC and type:
The segmented current source architecture has the ability to
improve the converter’s performance by reducing the amount
of current that is switching at any one time. In traditional
architectures, major transition points required the converter to
switch on or off large amounts of current. In a traditional 10-bit
R/2R ladder design, for example, the midscale transition
required approximately equal amounts of currents switching
on and off. In a segmented current source arrangement,
transitions such as midscale become one in which you simply
have an additional intermediate current source turning on and
several minor ones turning off. In the case of the HI5760,
there are 31 intermediate current segments that represent the
5 MSBs and five, binary-weighted current sources
representing each of the five LSBs. See the Functional Block
Diagram in the datasheet for a visual representation. To relate
the midscale transition example to the HI5760, consider the
following: The code 0111111111 would be represented by 15
intermediate current segments and each of the 5 LSB current
sources all turned on. To transition to code 1000000000 would
simply require turning off the 5 LSB current sources and
turning on the next intermediate current segment, bringing the
total amount of current switching at this ‘major’ code transition
equal to the same amount switching at 30 other code
transition points in the code ramp from 0 to 1023, so that the
total glitch energy is distributed more evenly.
A:\NCOMCTRL,
which will run the HSP45116 Control Panel software. Set
the control panel’s selections to the following and check the
output of the DAC at either IOUTA or IOUTB for a frequency
equal to 1.63MHz.
The clock select of the control panel should be set to ‘Osc.
CLK’. The control signals should be as follows:
0ENPHREG
0CLROFR
1LOAD
0BINFMT
1PMSEL
The amplitude of the real output (RIN0-15) should be 8000HEX
for full scale output. The center frequency register can be set to
10ABCDEFHEX for a 1.63MHz tone. The Offset Frequency,
Phase Offset, and Time Accumulator Registers should all be
set to zeros. The spurious free dynamic range that can be
expected is typically 70dBc with this setup operating at this
frequency.
Appendix B Pin Descriptions
PIN NO.
1-10
PIN NAME
PIN DESCRIPTION
D9 (MSB) Through Digital data bit-9, (most significant bit) through digital data bit-0, (least significant bit).
D0 (LSB)
11-14
NC
No Connect. Recommend ground.
15
SLEEP
16
REFLO
Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference.
17
REFIO
Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is enabled. Use
0.1µF cap to ground when internal reference is enabled.
18
FSADJ
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full scale output
current = 32 x VREFIO/RSET.
19
COMP1
For use in reducing bandwidth/noise. Recommended: Connect 0.1µF to AVDD.
20
ACOM
Analog Ground.
21
IOUTB
The complementary current output of the device. Full scale output current is achieved when all input bits are set
to binary 0.
22
IOUTA
Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.
23
COMP2
24
AVDD
25
NC
26
DCOM
Digital ground.
27
DVDD
Digital supply (+3V to +5V).
28
CLK
Control Pin for Power-Down Mode. Sleep mode is active high; Connect to ground for normal mode. Sleep pin has
internal 20µA active pull-down current.
Connect to ACOM directly or through a 0.1µF capacitor.
Analog supply (+3V to +5V).
No connect.
Input for clock. Positive edge of clock latches data.
3-4
Application Notes 9821
Appendix C Circuit Board Layout
FIGURE 2. PRIMARY SIDE
FIGURE 3. POWER LAYER (2)
3-5
Application Notes 9821
Appendix C Circuit Board Layout
(Continued)
FIGURE 4. GROUND LAYER (3)
FIGURE 5. SECONDARY SIDE
3-6
Appendix D Schematic
SMA1
EXT_REF 5
(OPTIONAL)
NOTE: JUMPERS SHOWN IN SHIPPED MODE:
J1 : SLEEP IS UNINSTALLED.
J2 : INTERNAL REFERENCE IS ENABLED.
J3 : EXTERNAL REFERENCE IS UNINSTALLED.
VME CONNECTOR (96 PIN)
A28
LSB
A8
P1-28
R4
50Ω
C28
P1-8
P1-92
R5
P1-91
P1-10
R6
50Ω
A26
A11
P1-26
R7
J1
P1-11
A13
A25
P1-13
P1-25
A27
14
13
12
11
10
9
8
7
6
5
4
3
2
1
50Ω
R9
50Ω
P1-89
R10
C32
P1-96
A24
C23
P1-24
P1-87
50Ω
R11
50Ω
C24
C18
R12
P1-88
P1-82
C3
50Ω
A23
MSB
P1-67
P1-23
R13
C13
CLK
P1-77
NOTE: ALL OTHER PINS ON THE 96 PIN, VME
CONNECTOR ARE DISCONNECTED.
C7
10µF
+
C6
10µF
+
AVDD1
NC
NC
NC
NC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
U1
SLEEP
REFLO
REFIO
FSADJ
COMP1
ACOM
IOUTB
IOUTA
COMP2
AVDD
NC
DCOM
DVDD
CLOCK
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2
0.1µF
R14
2kΩ
0.1µF
C1
C2
0.1µF
SMA3
IOUTB
IOUTA
SMA2
C3
R3
50Ω
R2
50Ω
TP1
TEST POINT (GND)
C9
0.1µF
C5
0.1µF
FB1
10µH
R1
50Ω
E3
DVDD1
ACOM1
2
J3
C8
0.1µF
50Ω
FB2
10µH
DCOM1
2
3
R8
C25
P1-27
1
C4
0.1µF
R1-13 (50Ω, 1210 PACKAGE)
R14 (2kΩ, 1206 PACKAGE)
C1-5, 8, 9 (0.1µF, 1206 PACKAGE)
C6, 7 (10µF, CASE B PACKAGE)
FB1,2 (10µH, FERRITE BEAD)
SMA1-3 (STRAIGHT JACK,
PCB MOUNT)
P1 (96 PIN VME CONNECTOR)
J1,3 (1X2 HEADERS)
J2 (1X3 HEADER)
U1 (HI5760BIB)
E2
Application Notes 9821
P1-90
P1-12
1
J2
50Ω
C28
A12
1
2X1 JUMPERS
A10
50Ω
3X1 JUMPERS
C27
2X1 JUMPERS
3-7
A9
P1-9
E1
Application Notes 9821
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
3-8
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Similar pages