DATASHEET

HI5828
TM
Data Sheet
April 2001
12-Bit, 130MSPS, Dual High Speed CMOS
D/A (2.7V-5.5V)
The HI5828 is a Dual 12-bit, 130MSPS (Mega Samples Per
Second), high speed, low power, D/A converter which is
implemented in an advanced CMOS process. Operating
from a single +3V to +5V supply, the converter provides
20mA of full scale output current and includes edge-triggered
CMOS input data latches. Low glitch energy and excellent
frequency domain performance is achieved by the HI5828’s
segmented current source architecture.
This device complements the HI5x60 and HI5x28 family of
high speed converters, which includes 8, 10, 12, and 14-bit
devices.
HI5828IN
PACKAGE
-40 to 85
48 Ld LQFP
25
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . ±0.75 LSB (Typ)
• Adjustable Full Scale Output Current . . . . . . 2mA to 20mA
• Internal 1.2V Bandgap Voltage Reference
• Single or Dual Power Supply from +3V to +5V
• Power Down Mode
• Basestations (Cellular, WLL)
Q48.7x7A 130MSPS
Evaluation Platform
130MSPS
• Quadrature Modulation
• Wireless Communications Systems
• Direct Digital Frequency Synthesis
• Signal Reconstruction
• High Resolution Imaging Systems
QD3
• Arbitrary Waveform Generators
QD1
QD2
QD0 (LSB)
N.C.
N.C.
ID11 (MSB)
ID8
ID9
ID10
ID7
ID6
• Medical/Test Instrumentation
ID5
1
48 47 46 45 44 43 42 41 40 39 38 37
36
QD4
ID4
2
35
QD5
ID3
ID2
3
34
QD6
4
33
ID1
5
32
(LSB) ID0
6
7
31
QD7
QD8
QD9
30
QD10
N.C.
8
29
SLEEP
DVDD
9
28
QD11 (MSB)
CLK
10
27
DGND
11
12
26
AGND
QCOMP2
AVDD
QCOMP1
QOUTB
QOUTA
AGND
FSADJ
REFIO
1
REFLO
IOUTA
IOUTB
AVDD
25
13 14 15 16 17 18 19 20 21 22 23 24
ICOMP1
ICOMP2
• Low Power . . . . .312mW at 5V, 46mW at 3V (at 60MSPS)
Applications
CLOCK
SPEED
PKG. NO.
HI5828
(LQFP)
TOP VIEW
AGND
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 130MSPS
• Excellent Spurious Free Dynamic Range
(76dBc, f S = 50MSPS, fOUT = 2.51MHz)
Pinout
N.C.
Features
• Excellent Multitone Intermodulation Distortion
TEMP.
RANGE
(oC)
HI5828EVAL2
4658.3
• CMOS Compatible Inputs
Ordering Information
PART
NUMBER
File Number
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
HI5828
Functional Block Diagram
(LSB) QD0
QD1
QD2
QD3
QD4
QD5
QD6
QD7
QD8
QD9
QD10
(MSB) QD11
7
SLAVE
LATCH
MASTER
LATCH
5
THERMOMETER
DECODER
38
SWITCH
DRIVERS
38
QOUTA
CURRENT
CELLS
7 LSBs
31
+
QOUTB
31 MSB
SEGMENTS
QCOMP1
BIAS
GENERATION
(LSB) ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9
ID10
(MSB) ID11
QCOMP2
7
38
SLAVE
LATCH
MASTER
LATCH
5
THERMOMETER
DECODER
SWITCH
DRIVERS
38
CURRENT
CELLS
7 LSBs
+
31
IOUTA
IOUTB
31 MSB
SEGMENTS
CLK
BIAS
GENERATION
ICOMP2
DVDD
DGND
AVDD
AGND
AVDD
BANDGAP
VOLTAGE
REFERENCE
SLEEP
-
ICOMP1
+
REFLO
REFIO
2
FSADJ
HI5828
48 47 46 45 44 43 42 41 40 39 38 37
36
1
35
2
34
3
33
4
32
5
31
6
30
7 N.C.
29
8 N.C.
CLK 28
9
DGND 27
10 DVDD
AGND 26
11 AGND
25
12
13 14 15 16 17 18 19 20 21 22 23 24
QD4
QD5
QD6
QD7
QD8
QD9
QD10
QD11 (MSB)
N.C.
N.C.
ID5
ID4
ID3
ID2
ID1
ID0 (LSB)
REFIO
REFLO
AGND
FSADJ
SLEEP
DVPP
C1
0.1µF
QD0 (LSB)
QD1
QD2
QD3
ID6
ID7
ID8
ID9
ID10
ID11 (MSB)
Typical Applications Circuit
ICOMP2
C2
0.1µF
AVDD
AVPP
ICOMP1
QCOMP1
R2
R3
50Ω 50Ω
CONN 1
(IOUTA)
AVPP
C5
0.1µF
C6
0.1µF
C7
0.1µF
AVPP
C3
0.1µF
AVDD
C4
0.1µF
R1
50Ω
QCOMP2
RSET
1.91kΩ
CONN2
(IOUTB)
R5
R4
50Ω 50Ω
CONN 3
(QOUTB)
C8
0.1µF
AVPP
CONN 4
(QOUTA)
BEAD
FERRITE
+ C11
10µF
L1
10µH
DVP-P (DIGITAL POWER PLANE)
C9
0.1µF
C10
1µF
C12
0.1µF
C13
1µF
+5V OR +3V POWER SOURCE
FERRITE
BEAD
+ C14
10µF
L2
10µH
AVP-P (ANALOG POWER PLANE)
NOTE: Separate analog and digital grounds should be used, in which case the grounds should be tied together at a single point near the device.
The analog and digital grounds should be connected together by a thin single trace and never connected together by an inductor.
3
HI5828
Pin Descriptions
PIN NO.
PIN NAME
11, 19, 26
AGND
Analog Ground.
13, 24
AVDD
Analog Supply (+2.7V to +5.5V).
28
CLK
Clock Input. The master and slave latches shown in the functional block diagram are simple D-latches.
Input data to the DAC passes through the “master” latches when the clock is low and is latched into the
“master” latches when the clock is high. Data presented to the “slave” latch passes through when the
clock is logic high and is latched into the “slave” latches when the clock is logic low. Adequate setup time
must be allowed for the MSBs to pass through the thermometer decoder before the clock goes high. This
master-slave arrangement comprises an edge-triggered flip-flop, with the DAC being updated on the
rising clock edge. It is recommended that the clock edge be skewed such that setup time is larger than
hold time for optimum spectral performance.
27
DGND
Connect to Digital Ground.
10
DVDD
Digital Supply (+2.7V to +5.5V).
20
FSADJ
Full Scale Current Adjust. Use a resistor to analog ground to adjust full scale output current. Full Scale
Output Current = 32 x VFSADJ/RSET. Where VFSADJ is the voltage at this pin. VFSADJ tracks the voltage
on the REFIO pin (refer to the functional block diagram); which is typically 1.2V if the internal reference
is used.
14, 23
ICOMP1, QCOMP1
Compensation Pin for Use in Reducing Bandwidth/Noise. Each pin should be individually decoupled to
AVDD with a 0.1µF capacitor. To minimize crosstalk, the part was designed so that these pins must be
connected externally, ideally directly under the device packaging. The voltage on these pins is used to
drive the gates of the PMOS devices that make up the current cells. Only the ICOMP1 pin is driven and
therefore QCOMP1 needs to be connected to ICOMP1, but de-coupled separately to minimize crosstalk.
If placed equally close to both pins, then only one decoupling capacitor might be necessary.
12, 25
ICOMP2, QCOMP2
Compensation Pin for Internal Bias Generation. Each pin should be individually decoupled to AGND with
a 0.1µF capacitor. The voltage generated at these pins represents the voltage used to supply power to
the switch drivers (refer to the functional block diagram) which is 2.0V nominal. This arrangement helps
to minimize clock feedthrough to the current cell transistors for reduced glitch energy and improved
spectral performance.
43-48, 1-6,
29-40
PIN DESCRIPTION
ID11-ID0, QD11-QD0 Digital Data Input Ports. Bit 11 is Most Significant Bit (MSB) and bit 0 is the Least Significant Bit (LSB).
15, 22
IOUTA, QOUTA
Current Outputs of the Device. Full scale output current is achieved when all input bits are set to binary 1.
16, 21
IOUTB, QOUTB
Complementary Current Outputs of the Device. Full scale output current is achieved on the
complementary outputs when all input bits are set to binary 0.
7, 8, 41, 42
N.C.
17
REFIO
Reference voltage input if Internal reference is disabled. The internal reference is not intended to drive an
external load. Use 0.1µF cap to ground when internal reference is enabled.
18
REFLO
Reference Low Select. When the internal reference is enabled, this pin serves as the precision ground
reference point for the internal voltage reference circuitry and therefore needs to have a good connection
to analog ground to enable internal 1.2V reference. To disable the internal reference circuitry this pin
should be connected to AVDD.
9
SLEEP
Control Pin for Power-Down Mode. Sleep Mode is active high; connect to ground for Normal Mode. The
Sleep pin has internal 25µA (nominal) active pulldown current.
No Connection. Future LSBs for dual 14-bit DAC.
4
HI5828
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DVDD to DGND . . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AVDD to AGND . . . . . . . . . . . . . . . . . . +5.5V
Grounds, AGND TO DGND . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D11-D0, CLK, SLEEP). . . . . . . DVDD + 0.3V
Reference Input Voltage Range . . . . . . . . . . . . . . . . . . .AVDD + 0.3V
Analog Output Current (IOUTA/B, QOUTA/B) . . . . . . . . . . . . . 24mA
Thermal Resistance (Typical, Note 1)
θJA(oC/W)
LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(LQFP - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
AVDD = DVDD = +5V (except where otherwise noted), VREF = Internal 1.2V,
IOUTFS = 20mA, TA = 25oC for All Typical Values
TA = -40oC TO 85oC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
12
-
-
Bits
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 8)
-2.0
±0.75
+2.0
LSB
Differential Linearity Error, DNL
(Note 8)
-1.0
±0.5
+1.0
LSB
Offset Error, IOS
(Note 8)
-0.025
-
+0.025
% FSR
Offset Drift Coefficient
(Note 8)
-
0.1
-
ppm
FSR/oC
Full Scale Gain Error, FSE
With External Reference (Notes 2, 8)
-10
±2
+10
% FSR
With Internal Reference (Notes 2, 8)
-10
±1
+10
% FSR
With External Reference (Note 8)
-
±50
-
ppm
FSR/oC
With Internal Reference (Note 8)
-
±100
-
ppm
FSR/oC
2
-
20
mA
fCLK = 100MSPS, fOUT = 10MHz
-
85
-
dB
fCLK = 100MSPS, fOUT = 40MHz
-
64
-
dB
Gain Matching Between Channels
(DC Measurement)
As a percentage of Full Scale Range
-5
-
+5
% FSR
-0.445
-
+0.420
dB FSR
Output Voltage Compliance Range
(Note 3, 8)
-0.3
-
1.25
V
Maximum Clock Rate, fCLK
(Note 3)
130
-
-
MHz
Output Settling Time, (tSETT)
±0.05% (±2 LSB) (Note 8)
-
35
-
ns
Singlet Glitch Area (Peak Glitch)
RL = 25Ω (Note 8)
-
5
-
pV•s
Output Rise Time
Full Scale Step
-
2.5
-
ns
Output Fall Time
Full Scale Step
-
2.5
-
ns
-
10
-
pF
Full Scale Gain Drift
Full Scale Output Current, IFS
Crosstalk
In dB Full Scale Range
DYNAMIC CHARACTERISTICS
Output Capacitance
5
HI5828
Electrical Specifications
AVDD = DVDD = +5V (except where otherwise noted), VREF = Internal 1.2V,
IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued)
TA = -40oC TO 85oC
PARAMETER
TEST CONDITIONS
Output Noise
MIN
TYP
MAX
UNITS
IOUTFS = 20mA
-
50
-
pA/√Hz
IOUTFS = 2mA
-
30
-
pA/√Hz
fCLK = 100MSPS, fOUT = 20.2MHz, 30MHz Span (Notes 4, 8)
-
77
-
dBc
fCLK = 100MSPS, fOUT = 5.04MHz, 8MHz Span (Notes 4, 8)
-
93
-
dBc
fCLK = 50MSPS, fOUT = 5.02MHz, 8MHz Span (Notes 4, 8)
-
93
-
dBc
fCLK = 100MSPS, fOUT = 4.0MHz (Notes 4, 8)
-
-72
-
dB
fCLK = 50MSPS, fOUT = 2.0MHz (Notes 4, 8)
-
-74
-
dB
fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8)
-
-73
-
dB
fCLK = 130MSPS, fOUT = 40.4MHz (Notes 4, 8)
-
55
-
dBc
fCLK = 130MSPS, fOUT = 10.1MHz (Notes 4, 8)
-
66
-
dBc
66
72
-
dBc
66
-
-
dBc
fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 8)
-
54
-
dBc
fCLK = 100MSPS, fOUT = 20.2MHz (Notes 4, 8)
-
62
-
dBc
fCLK = 100MSPS, fOUT = 5.04MHz, T = 25oC (Notes 4, 8)
66
72
-
dBc
fCLK = 100MSPS, fOUT = 5.04MHz, T = Min to Max (Notes 4, 8)
66
-
-
dBc
fCLK = 100MSPS, fOUT = 2.51MHz (Notes 4, 8)
-
75
-
dBc
fCLK = 50MSPS, fOUT = 20.2MHz (Notes 4, 8)
-
64
-
dBc
fCLK = 50MSPS, fOUT = 5.02MHz, T = 25oC (Notes 4, 8)
66
72
-
dBc
fCLK = 50MSPS, fOUT = 5.02MHz, T = Min to Max (Notes 4, 8)
66
-
-
dBc
fCLK = 50MSPS, fOUT = 2.51MHz (Notes 4, 8)
-
76
-
dBc
fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 8)
-
78
-
dBc
fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8)
-
77
-
dBc
fCLK = 20MSPS, fOUT = 2.0MHz to 2.99MHz, 8 Tones at 110kHz
Spacing (Notes 4, 8)
-
76
-
dBc
fCLK = 100MSPS, fOUT = 10MHz to 14.95MHz, 8 Tones at 530kHz
Spacing (Notes 4, 8)
-
76
-
dBc
fCLK = 100MSPS, fOUT = 20.2MHz, 30MHz Span (Notes 4, 8)
-
73
-
dBc
fCLK = 100MSPS, fOUT = 5.04MHz, 8MHz Span (Notes 4, 8)
-
91
-
dBc
fCLK = 50MSPS, fOUT = 5.02MHz, 8MHz Span (Notes 4, 8)
-
91
-
dBc
fCLK = 100MSPS, fOUT = 4.0MHz (Notes 4, 8)
-
-71
-
dB
fCLK = 50MSPS, fOUT = 2.0MHz (Notes 4, 8)
-
-75
-
dB
fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8)
-
-74
-
dB
AC CHARACTERISTICS
+5V Power Supply
Spurious Free Dynamic Range,
SFDR Within a Window
+5V Power Supply
Total Harmonic Distortion (THD) to
Nyquist
+5V Power Supply
Spurious Free Dynamic Range,
SFDR to Nyquist (fCLK/2)
fCLK = 130MSPS, fOUT
= 5.02MHz, T = 25oC (Notes 4, 8)
fCLK = 130MSPS, fOUT = 5.02MHz, T = Min to Max (Notes 4, 8)
+5V Power Supply
Multitone Power Ratio
+3V Power Supply
Spurious Free Dynamic Range,
SFDR Within a Window
+3V Power Supply
Total Harmonic Distortion (THD) to
Nyquist
6
HI5828
Electrical Specifications
AVDD = DVDD = +5V (except where otherwise noted), VREF = Internal 1.2V,
IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued)
TA = -40oC TO 85oC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
fCLK = 130MSPS, fOUT = 40.4MHz (Notes 4, 8)
-
47
-
dBc
fCLK = 130MSPS, fOUT = 10.1MHz (Notes 4, 8)
-
66
-
dBc
fCLK = 130MSPS, fOUT = 5.02MHz (Notes 4, 8)
-
73
-
dBc
fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 8)
-
48
-
dBc
fCLK = 100MSPS, fOUT = 20.2MHz (Notes 4, 8)
-
58
-
dBc
fCLK = 100MSPS, fOUT = 5.04MHz (Notes 4, 8)
-
72
-
dBc
fCLK = 100MSPS, fOUT = 2.51MHz (Notes 4, 8)
-
76
-
dBc
fCLK = 50MSPS, fOUT = 20.2MHz (Notes 4, 8)
-
53
-
dBc
68
73
-
dBc
66
-
-
dBc
fCLK = 50MSPS, fOUT = 2.51MHz (Notes 4, 8)
-
76
-
dBc
fCLK = 50MSPS, fOUT = 1.00MHz(Notes 4, 8)
-
76
-
dBc
fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8)
-
76
-
dBc
fCLK = 20MSPS, fOUT = 2.0MHz to 2.99MHz, 8 Tones at 110kHz
Spacing (Notes 4, 8)
-
76
-
dBc
fCLK = 100MSPS, fOUT = 10MHz to 14.95MHz, 8 Tones at 530kHz
Spacing (Notes 4, 8)
-
76
-
dBc
1.15
1.22
1.29
V
Internal Reference Voltage Drift
-
±10
-
ppm/oC
Internal Reference Output Current
Sink/Source Capability
-
±100
-
nA
Reference Input Impedance
-
1
-
MΩ
Reference Input Multiplying Bandwidth (Note 8)
-
1.4
-
MHz
+3V Power Supply
Spurious Free Dynamic Range,
SFDR to Nyquist (fCLK/2)
fCLK = 50MSPS, fOUT
= 5.02MHz, T = 25oC (Notes 4, 8)
fCLK = 50MSPS, fOUT = 5.02MHz, T = Min to Max (Notes 4, 8)
+3V Power Supply
Multitone Power Ratio
VOLTAGE REFERENCE
Internal Reference Voltage, VFSADJ
DIGITAL INPUTS
Pin 18 Voltage with Internal Reference
D11-D0, CLK
Input Logic High Voltage with
5V Supply, VIH
(Note 3)
3.5
5
-
V
Input Logic High Voltage with
3V Supply, VIH
(Note 3)
2.1
3
-
V
Input Logic Low Voltage with
5V Supply, VIL
(Note 3)
-
0
1.3
V
Input Logic Low Voltage with
3V Supply, VIL
(Note 3)
-
0
0.9
V
Input Sleep Current, IIH
-25
-
+25
µA
Input Logic Current, IIH
-10
-
+10
µA
Input Logic Current, IIL
-10
-
+10
µA
-
5
-
pF
Digital Input Capacitance, CIN
7
HI5828
Electrical Specifications
AVDD = DVDD = +5V (except where otherwise noted), VREF = Internal 1.2V,
IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued)
TA = -40oC TO 85oC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS
Data Setup Time, tSU
See Figure 4 (Note 3)
-
1.5
-
ns
Data Hold Time, tHLD
See Figure 4 (Note 3)
-
1.2
-
ns
Propagation Delay Time, tPD
See Figure 4
-
2.5
-
ns
CLK Pulse Width, tPW1 , tPW2
See Figure 4 (Note 3)
4
-
-
ns
POWER SUPPLY CHARACTERISTICS
AVDD Power Supply
(Note 9)
2.7
5.0
5.5
V
DVDD Power Supply
(Note 9)
2.7
5.0
5.5
V
Analog Supply Current (IAVDD)
5V or 3V, IOUTFS = 20mA (Note 7)
-
44
50
mA
5V or 3V, IOUTFS = 2mA
-
7
-
mA
5V (Note 5)
-
12
-
mA
5V (Note 6)
-
17.6
-
mA
5V (Note 7)
-
29
38
mA
3V (Note 5)
-
4
-
mA
3V (Note 6)
-
8.2
-
mA
3V (Note 7)
-
9.6
12
mA
Supply Current (IAVDD) Sleep Mode
5V or 3V, IOUTFS = Don’t Care
-
2.7
-
mA
Power Dissipation
5V, IOUTFS = 20mA (Note 5)
-
280
-
mW
5V, IOUTFS = 20mA (Note 6)
-
312
-
mW
5V, IOUTFS = 20mA (Note 7)
-
365
440
mW
5V, IOUTFS = 2mA (Note 6)
-
137
-
mW
3V, IOUTFS = 20mA (Note 5)
-
144
-
mW
3V, IOUTFS = 20mA (Note 6)
-
158
3V, IOUTFS = 20mA (Note 7)
-
161
177
mW
3V, IOUTFS = 2mA (Note 6)
-
46
-
mW
-0.2
-
+0.2
% FSR/V
Digital Supply Current (IDVDD)
Power Supply Rejection
Single Supply (Note 8)
mW
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625µA). Ideally the
ratio should be 32.
3. Parameter guaranteed by design or characterization and not production tested.
4. Spectral measurements made with differential transformer coupled output and no external filtering.
5. Measured with the clock at 60MSPS and the output frequency at 10MHz.
6. Measured with the clock at 100MSPS and the output frequency at 40MHz.
7. Measured with the clock at 130MSPS and the output frequency at 5MHz.
8. See “Definition of Specifications”.
9. It is recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V. DVDD and AVDD
do not have to be equal.
8
HI5828
Definition of Specifications
Differential Linearity Error, DNL, is the measure of the
step size output deviation from code to code. Ideally the step
size should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
by using a sinusoidal waveform as the external reference
with the digital inputs set to all 1’s. The frequency is
increased until the amplitude of the output waveform is 0.707
(-3dB) of its original value.
Full Scale Gain Drift, is measured by setting the data inputs
to be all logic high (all 1s) and measuring the output voltage
through a known resistance as the temperature is varied
from TMIN to TMAX . It is defined as the maximum deviation
from the value measured at room temperature to the value
measured at either TMIN or TMAX . The units are ppm of FSR
(full scale range) per oC.
Singlet Glitch Area, is the switching transient appearing on
the output during a code transition. It is measured as the
area under the overshoot portion of the curve and is
expressed as a Volt-Time specification. This is tested using
a single code transition across a major current source.
Full Scale Gain Error, is the error from an ideal ratio of 32
between the output current and the full scale adjust current
(through RSET).
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Internal Reference Voltage Drift, is defined as the
maximum deviation from the value measured at room
temperature to the value measured at either TMIN or TMAX .
The units are ppm per oC.
Offset Drift, is measured by setting the data inputs to all
logic low (all 0’s) and measuring the output voltage through a
known resistance as the temperature is varied from TMIN to
TMAX . It is defined as the maximum deviation from the value
measured at room temperature to the value measured at
either TMIN or TMAX . The units are ppm of FSR (full scale
range) per degree oC.
Offset Error, is measured by setting the data inputs to all
logic low (all 0’s) and measuring the output voltage through a
known resistance. Offset error is defined as the maximum
deviation of the output current from a value of 0mA.
Output Settling Time, is the time required for the output
voltage to settle to within a specified error band measured
from the beginning of the output transition. The
measurement is done by switching quarter scale.
Termination impedance was 25Ω due to the parallel
resistance of the 50Ω loading on the output and the
oscilloscope’s 50Ω input. This also aids the ability to resolve
the specified error band without overdriving the oscilloscope.
Output Voltage Compliance Range, is the voltage limit
imposed on the output. The output impedance should be
chosen such that the voltage developed does not violate the
compliance range.
Power Supply Rejection, is measured using a single power
supply. The supply’s nominal +5V is varied ±10% and the
change in the DAC full scale output is noted.
Reference Input Multiplying Bandwidth, is defined as the
3dB bandwidth of the voltage reference input. It is measured
9
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from the fundamental signal to the largest
harmonically or non-harmonically related spur within the
specified frequency window.
Total Harmonic Distortion, THD, is the ratio of the RMS
value of the fundamental output signal to the RMS sum of
the first five harmonic components.
Detailed Description
The HI5828 is a dual 12-bit, current out, CMOS, digital to
analog converter. Its maximum update rate is 130MSPS and
can be powered by either single or dual power supplies in
the recommended range of +3V to +5V. Operation with clock
rates higher than 130MSPS is possible; please contact the
factory for more information. It consumes 370mW of power
when using a +5V supply with the data switching at
130MSPS. The architecture is based on a segmented
current source arrangement that reduces glitch by reducing
the amount of current switching at any one time. In previous
architectures that contained all binary weighted current
sources or a binary weighted resistor ladder, the converter
might have a substantially larger amount of current turning
on and off at certain, worst-case transition points such as
midscale and quarter scale transitions. By greatly reducing
the amount of current switching at certain ‘major’ transitions,
the overall glitch of the converter is dramatically reduced,
improving settling time, transient problems, and accuracy.
Digital Inputs and Termination
The HI5828 digital inputs are guaranteed to CMOS levels.
However, TTL compatibility can be achieved by lowering the
supply voltage to 3V due to the digital threshold of the input
buffer being approximately half of the supply voltage. The
internal register is updated on the rising edge of the clock. To
minimize reflections, proper termination should be
implemented. If the lines driving the clock and the digital
inputs are long 50Ω lines, then 50Ω termination resistors
should be placed as close to the converter inputs as possible
connected to the digital ground plane (if separate grounds
are used). These termination resistors are not likely needed
as long as the digital waveform source is within a few inches
of the DAC.
HI5828
Ground Planes
Outputs
Separate digital and analog ground planes should be used.
All of the digital functions of the device and their
corresponding components should be located over the
digital ground plane and terminated to the digital ground
plane. The same is true for the analog components and the
analog ground plane. Consult Application Note AN9855.
The 5 MSBs for each DAC on the HI5828 drive a
thermometer decoder, which is a digital decoder that has an
N-bit (5 bits for the HI5828) binary coded input word with
2N-1 (31 for the HI5828) output bits, where the number of
output bits that are active correlate directly to the input
binary word. The HI5828 uses a thermometer decoder to
significantly minimize the output glitch energy for each DAC.
I/QOUTA and I/QOUTB are complementary current outputs.
The sum of the two currents is always equal to the full scale
output current minus one LSB. If single ended use is
desired, a load resistor can be used to convert the output
current to a voltage. It is recommended that the unused
output be either grounded or equally terminated. The voltage
developed at the output must not violate the output voltage
compliance range of -0.3V to 1.25V. RLOAD (the impedance
loading each current output) should be chosen so that the
desired output voltage is produced in conjunction with the
output full scale current. If a known line impedance is to be
driven, then the output load resistor should be chosen to
match this impedance. The output voltage equation is:
Noise Reduction
To minimize power supply noise, 0.1µF capacitors should be
placed as close as possible to the converter’s power supply
pins, AVDD and DVDD. Also, the layout should be designed
using separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for
DVDD and to the analog ground for AVDD. Additional filtering
of the power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal
value of + 1.2V with a ±10ppm/ oC drift coefficient over the full
temperature range of the converter. It is recommended that a
0.1µF capacitor be placed as close as possible to the REFIO
pin, connected to the analog ground. The REFLO pin (18)
selects the reference. The internal reference can be selected
if pin 18 is tied low (ground). If an external reference is
desired, then pin 18 should be tied high (the analog supply
voltage) and the external reference driven into REFIO, pin 17.
The full scale output current of the converter is a function of
the voltage reference used and the value of RSET. IOUT
should be within the 2mA to 20mA range, though operation
below 2mA is possible, with performance degradation.
VFSADJ and VREFIO will be equivalent except for a small
offset voltage. If the internal reference is used, VFSADJ will
equal approximately 1.2V on the FSADJ pin (20). If an
external reference is used, VFSADJ will equal the external
reference. The calculation for IOUT(Full Scale) is:
VOUT = IOUT X RLOAD.
These outputs can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. The
SFDR measurements in this data sheet were performed with
a 1:1 transformer on the output of the DAC (see Figure 1).
With the center tap grounded, the output swing of pins 15/22
and 16/21 will be biased at zero volts. The loading as shown
in Figure 1 will result in a 500mV signal at the output of the
transformer if the full scale output current of the DAC is set to
20mA. VOUT = 2 x IOUT x REQ, where REQ is ~12.5Ω.
REQ IS THE IMPEDANCE
LOADING EACH OUTPUT.
50Ω
IOUT(Full Scale) = (VFSADJ/RSET) X 32.
PIN 15/22
If the full scale output current is set to 20mA by using the
internal voltage reference (1.2V) and a 1.91kΩ RSET
resistor, then the input coding to output current will resemble
the following:
PIN 16/21
100Ω
TABLE 1. INPUT CODING vs OUTPUT CURRENT
INPUT CODE (D11-D0)
I/QOUTA (mA)
I/QOUTB (mA)
11 11111 11111
20
0
10 00000 00000
10
10
00 00000 00000
0
20
10
HI5828
VOUT = (2 x IOUT x REQ )V
I/QOUTA
50Ω
I/QOUTB
50Ω
50Ω REPRESENTS THE
SPECTRUM ANALYZER
FIGURE 1.
Allowing the center tap to float will result in identical
transformer output, however the output pins of the DAC will
have positive DC offset. Since the DAC’s output voltage
compliance range is -0.3V to +1.25V, the center tap may
need to be left floating or DC offset in order to increase the
amount of signal swing available. The 50Ω load on the
output of the transformer represents the spectrum analyzer’s
input impedance.
HI5828
Timing Diagrams
50%
CLK
D11-D0
GLITCH AREA = 1/2 (H x W)
V
1/ LSB ERROR BAND
2
HEIGHT (H)
IOUT
t(ps)
WIDTH (W)
tSETT
tPD
FIGURE 2. OUTPUT SETTLING TIME DIAGRAM
tPW1
FIGURE 3. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
tPW2
50%
CLK
tSU
tSU
tHLD
tSU
tHLD
tHLD
D11-D0
tPD
tSETT
IOUT
tPD
tSETT
tPD
tSETT
FIGURE 4. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
11
HI5828
Thin Plastic Quad Flatpack Packages (LQFP)
Q48.7x7A (JEDEC MS-026BBC ISSUE B)
48 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE
D
D1
-D-
INCHES
-A-
-B-
E E1
e
PIN 1
SEATING
A PLANE
-H-
0.08
0.003
-C-
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.062
-
1.60
-
A1
0.002
0.005
0.05
0.15
-
A2
0.054
0.057
1.35
1.45
-
b
0.007
0.010
0.17
0.27
6
b1
0.007
0.009
0.17
0.23
-
D
0.350
0.358
8.90
9.10
3
D1
0.272
0.280
6.90
7.10
4, 5
E
0.350
0.358
8.90
9.10
3
E1
0.272
0.280
6.90
7.10
4, 5
L
0.018
0.029
0.45
0.75
N
48
48
e
0.020 BSC
0.50 BSC
7
Rev. 2 1/99
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane -C- .
0.08
0.003 M
C A-B S
b
11o-13o
0.020
0.008 MIN
b1
0o MIN
A2 A1
GAGE
PLANE
0.25
0.010
11o-13o
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall not cause the lead width to exceed
the maximum b dimension by more than 0.08mm (0.003
inch).
0.09/0.16
0.004/0.006
BASE METAL
WITH PLATING
L
0o-7o
D S
7. “N” is the number of terminal positions.
0.09/0.20
0.004/0.008
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