an9855

HI5828EVAL2 User’s Manual
TM
Application Note
February 2000
AN9855.1
Description
Features
The HI5828EVAL2 evaluation board provides a quick and
easy method for evaluating the HI5828, 125MSPS Dual High
Speed DAC. Each converter outputs a current into a load
resistor to form a voltage which can be measured by using
the included SMA connectors. The amount of current out of
the DACs is determined by an external resistor and either an
internal or external reference voltage. The evaluation board
also includes a VME (Versa Module Eurocard) digital
interface that is compatible with all previous INTERSIL DAC
evaluation boards. Transformers are included to take
advantage of differential signal drive.
• HI5828, Dual 12-Bit, 125MSPS CMOS DACs
Ordering Information
• Modulated Carrier Generation
PART
NUMBER
TEMP.
RANGE (oC)
PACKAGE
HI5828EVAL2
25
Evaluation Platform
• Single or Dual 3-5V Supply Range
• Future Dual 14-Bit Ready
• Standard VME/DSP Interface, HSP-EVAL Compatible
• SMA Outputs with Transformer Option
• Easily Selectable Internal or External Reference
Applications
• I and Q Signal Generation
• General DAC Performance Evaluation
CLOCK
SPEED
• Amplitude Modulation Via External Reference
125MHz
Functional Block Diagram
P1
RSET
R15 OR 43
DVDD
AVDD
I-CHANNEL 14 BITS
VME
64 OR 96-PIN
CONNECTOR
IOUTA
IOUTB
Q-CHANNEL 14 BITS
HI5828
DAC
U3
CLK
XFMR
IOUT
XFMR
QOUT
QOUTB
QOUTA
CLOCK
T2
T1
REF SELECT
J21/22
AVDD
J15
SLEEP
EXTERNAL
REFERENCE
(OPTIONAL)
3-1
J23
1-888-INTERSIL or 321-724-7143
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Intersil and Design is a trademark of Intersil Corporation.
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Copyright
© Intersil Corporation 2000
Application Note 9855
Functional Descriptions
Voltage Reference
The HI5828 has an internal nominal 1.2V voltage reference
with a ±10ppm/oC drift coefficient over the industrial
temperature range. The REFLO pin (18) selects the
reference. Access to pin 18 is provided through solder
jumpers J21 and J22. These jumpers are labeled INT and
EXT for internal or external reference. The REFIO pin (17)
provides access to the internal voltage reference and can be
overdriven if the user wishes to use an external source for the
reference. The internal reference was not designed to drive an
external load. Notice that a 0.1µF capacitor is placed as close
as possible to the REFIO pin. This capacitor is necessary for
ensuring a noise free reference voltage.
If the user wishes to use an external reference voltage, jumper
J23 must be in place and an external voltage reference
provided via J18, an SMA connector labeled ‘EXT REF’.
Jumper J22 must be soldered so that pin 18 (REFLO) is tied
to a logic high (the supply voltage). The recommended limits
of the external reference are between 15mV and 1.2V.
Performance of the converter can be expected to decline as
the reference voltage is reduced due to the reduction in LSB
current size.
If the user wishes to amplitude modulate the DAC, the REFIO
pin can be overdriven with a waveform. The input multiplying
bandwidth of the REFIO input is approximately 1.4MHz when
driving a 100mV signal into the REFIO pin, biased at 0.6VDC.
The 3dB BW reduces as this amplitude is increased. It is
necessary that the multiplying signal be DC offset so that the
minimum and maximum peaks are positive and below 1.2V.
The output current of the converter, IOUTA and IOUTB, is a
function of the voltage reference used and the value of RSET,
R43.
Output Current
The output current of the device is set by choosing RSET
and VFSADJ such that the resultant of the following equation
is less than 20mA:
IOUT = 32 x VFSADJ/RSET.
REFIO (Pin 17) and FSADJ (Pin 20) of the DAC are the
inputs to an operational amplifier. The voltage at the FSADJ
pin (VFSADJ) will be approximately equal to the voltage at
the REFIO pin, which will either be the value of the internal
or external reference. For example, using the internal
reference of (nominal) 1.2V and an RSET value of 1.91kΩ
results in an IOUT of approximately 20mA (maximum
allowed). Choose the output loading so that the Output
Voltage Compliance Range is not violated (-0.3 to 1.25V).
The output can be configured to drive a load resistor, a
transformer, an operational amplifier, or any other type of
output configuration so long as the output voltage
compliance range and the maximum output current are not
violated.
3-2
Transformer Output
The evaluation board is configured with a transformer output
configuration, shown in Figure 1. This configuration was
chosen because it provides: even harmonic performance
improvement due to the complimentary differential signaling;
~12.5Ω REQ loading to each output of the DAC; drive
impedance of 50Ω for matching with a spectrum analyzer;
and 2x voltage gain. The output of this configuration will be
biased at zero volts and have an amplitude of ~500mV
(VOUT) when the DAC is configured to drive IOUTFS of
20mA.
HI5828
VOUT = (2 x IOUTFS x REQ)V
50Ω
IOUTA(QOUTA)
PIN 15 (22)
100Ω
PIN 16 (21)
IOUTB(QOUTB)
50Ω
SPECTRUM
ANALYZER’S
INPUT
IMPEDANCE
50Ω
FIGURE 1.
Sleep
The converter can be put into ‘sleep’ mode by connecting pin
9 of the DAC to either of the converter’s supply voltages. The
sleep pin has an active pull-down current, so the pin can be
left disconnected or be grounded for normal (awake)
operation. On the evaluation board, jumper J15 is provided
for controlling the sleep pin. Remove the solder jumper from
J15 for normal operation and replace it for sleep mode.
Power Supply(s) and Ground(s)
The user can operate from either a single supply or from
dual supplies. The supplies can be at different voltages. It is
important to note that the digital inputs cannot switch more
than 0.3V above the digital supply voltage. The evaluation
board contains two power supply connections, (analog)
AVDD and (digital) DVDD, each with their own ground wire.
Dual ground and power planes is the recommended
configuration, with the ground planes connected at a single
point (J7 on the evaluation board). Error on the board: the
labels for DGND and AGND are swapped. The DGND label
is next to the analog ground connection and the AGND label
is next to the digital ground connection.
Digital Inputs
The DAC is designed to accept CMOS inputs. The switching
voltage is approximately 1/2 of the digital power supply
voltage, so reducing the power supply can make the DAC
compatible to smaller levels. The digital inputs (data and
clock) cannot go +0.3V higher than the digital supply
voltage, else diode ESD protection can begin to turn on and
performance could be degraded. The clock source can be a
sine wave, with some degradation in performance possible.
The recommended clock is a square wave.
Application Note 9855
The timing between the clock and the data will effect spectral
performance and functionality. Minimum setup and hold times
are specified in the datasheet to represent the point at which
the DAC begins to lose bits. Optimal setup and hold times
vary with the clock rate to output frequency ratio. A general
rule is that the lower the FCLK/FOUT ratio is, the higher the
setup time should be to achieve optimum spectral behavior.
Attach the evaluation board to the power supply(s). Connect
the bits from the data generator to the evaluation board,
preferably by using a male, 64 or 96-pin VME (Versa Module
Eurocard) connector that mates with the evaluation board.
Connect the clock source to the evaluation board, also
preferably through the VME connector. Failure to make clean
and short connections to the data input lines and clock
source will result in a decrease in spectral performance.
Getting Started
Using a coaxial cable with the proper SMA connector, attach
the output of the converter, IOUT, to the measurement
equipment that will be evaluating the converter’s
performance. Make sure that the jumpers are in their proper
placement. Consult the ‘Voltage Reference’ section and the
‘Sleep’ section of this document for a definition of the
jumpers’ functionality.
A summary of the external supplies, equipment, and signal
sources needed to operate the board is given below:
1. +5V to +3V supply for HI5x60 DAC.
2. Pattern Generator.
3. Square wave clock source (usually part of the Pattern
Generator).
4. Spectrum Analyzer or Oscilloscope for viewing the output
of the converter.
HP-SMA TEST BOARD
(INTERSIL MADE)
CLK
CLK
FEMALE 64 PIN VME CONNECTOR
16 BITS AVAILABLE
MALE 96 PIN VME CONNECTOR
HI5828 EVALUATION BOARD
UP TO
14 BITS
1/2 HI5828
DUAL DAC
CLOCK
1/2 HI5828
DUAL DAC
UP TO
14 BITS
+5V TO +3V
POWER
SUPPLY
50Ω
SMA
CABLE
HEWLETT PACKARD HP80000
PATTERN GENERATOR
SPECTRUM ANALYZER
FIGURE 2. INTERSIL HI5828 EVALUATION SYSTEM SETUP BLOCK DIAGRAM
3-3
Application Note 9855
Appendix A Description of Architecture
The segmented current source architecture has the ability to
improve the converter’s performance by reducing the amount
of current that is switching at any one time. In a segmented
current source arrangement, transitions such as midscale
become one in which you simply have an additional
intermediate current source turning on and several minor
ones turning off. In the case of the HI5760 10-Bit DAC, there
are 31 intermediate current segments that represent the 5
MSBs and five, binary-weighted current sources representing
each of the five LSBs. See the Functional Block Diagram in
the datasheet for a visual representation. To relate the
midscale transition example to the HI5760, consider the
following: The code 0111111111 would be represented by 15
intermediate current segments and each of the 5 LSB current
sources all turned on. To transition to code 1000000000 would
simply require turning off the 5 LSB current sources and
turning on the next intermediate current segment, bringing the
total amount of current switching at this ‘major’ code transition
equal to the same amount switching at 30 other code
transition points in the code ramp from 0 to 1023, so that the
total glitch energy is distributed more evenly. The HI5828 uses
this technique but with a 5 MSB/7 LSB split.
HI5828 Pin Descriptions
PIN NO.
NAME
11, 19, 26
AGND
Analog Ground.
13, 24
AVDD
Analog Supply (+3V to +5V).
28
CLK
Clock Input. The master and slave latches shown in the functional block diagram are simple D-latches.
Input data to the DAC passes through the “master” latches when the clock is low and is latched into the
“master” latches when the clock is high. Data presented to the “slave” latch inputs passes through when
the clock is high and is latched into the “slave” latches when the clock is low. This master-slave
arrangement comprises an edge-triggered flip-flop, with the DAC being updated on the rising clock edge.
27
DGND
Connect to Digital Ground.
10
DVDD
Digital Supply (+3V to +5V).
20
FSADJ
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current = 32 x VFSADJ/RSET. Where VFSADJ is the voltage at this pin. VFSADJ tracks the voltage on the
REFIO pin (refer to the functional block diagram); which is typically 1.2V if the internal reference is used.
14, 23
ICOMP1, QCOMP1
Compensation Pin for Use in Reducing Bandwidth/Noise. Each pin should be individually decoupled to
AVDD with a 0.1µF capacitor. To minimize crosstalk, the part was designed so that these pins must be
connected externally, ideally directly under the device packaging. The voltage on these pins is used to
drive the gates of the PMOS devices that make up the current cells. Only the ICOMP1 pin is driven and
therefore QCOMP1 needs to be connected to ICOMP1, but de-coupled separately to minimize crosstalk.
12, 25
ICOMP2, QCOMP2
Compensation Pin for Internal Bias Generation. Each pin should be individually decoupled to AGND with
a 0.1µF capacitor. The voltage generated at these pins represents the voltage used to supply power to
the switch drivers (refer to the functional block diagram) which is 2.0V nominal. This arrangement helps
to minimize clock feedthrough to the current cell transistors for reduced glitch energy and improved
spectral performance.
43-48, 1-6,
29-40
DESCRIPTION
ID11-ID0, QD11-QD0 Digital Data Input Ports. Bit 11 is Most Significant Bit (MSB) and bit 0 is the Least Significant Bit (LSB).
15, 22
IOUTA, QOUTA
Current Outputs of the Device. Full scale output current is achieved when all input bits are set to binary 1.
16, 21
IOUTB, QOUTB
Complementary Current Outputs of the Device. Full scale output current is achieved on the
complementary outputs when all input bits are set to binary 0.
7, 8, 41, 42
NC
17
REFIO
Reference voltage input if Internal reference is disabled. Use 0.1µF cap to ground when internal reference
is enabled.
18
REFLO
Reference Low Select. To enable the internal reference, connect REFLO to analog ground. To disable
the internal reference circuitry this pin should be connected to AVDD.
9
SLEEP
Control Pin for Power-Down Mode. Sleep Mode is active high; connect to ground for Normal Mode. Sleep
pin has internal 20µA (nominal) active pull-down current.
No Connection.
3-4
Application Note 9855
Appendix C Circuit Board Layout
FIGURE 3. PRIMARY SIDE (VIEWED FROM THE TOP)
FIGURE 4. GROUND LAYER (2) (VIEWED THROUGH THE BOARD FROM THE TOP)
3-5
Application Note 9855
Appendix C Circuit Board Layout
(Continued)
FIGURE 5. POWER LAYER (3) (VIEWED THROUGH THE BOARD FROM THE TOP)
FIGURE 6. SECONDARY SIDE (VIEWED THROUGH THE BOARD FROM THE TOP)
3-6
Application Note 9855
Power Supply Input Circuit
L2
10µH
J3
DVDD1
+
+
C5
10µF
(NOT
USED)
C7
0.1µF
C6
10µF
0Ω
DIGITAL POWER PLANE
PIN 10
OF THE HI5828
C8 (NOT
1µF USED)
DIGITAL GROUND PLANE
PIN 27
OF THE HI5828
DGND1
J4
0Ω
J7
J27
0Ω
L1
10µH
0Ω
AVDD1
+
+
(NOT C1
USED) 10µF
C3
0.1µF
C2
10µF
J8
C4 (NOT
1µF USED)
0Ω
ANALOG POWER PLANE
PINS 13, 24
OF THE HI5828
ANALOG GROUND PLANE
PINS 11, 19, 26
OF THE HI5828
AGND1
NOTE: DVDD and AVDD can be tied together for single supply operation. AGND1 and DGND1 are tied together at a single point. See text for further
explanation.
Ground Symbol Definition
VME (Versa Module Eurocard) Ground
Connections
= ANALOG GROUND (AGND1)
= DIGITAL GROUND (DGND1)
A8
J42-8
A9
Digital Input Jumper Connections
Q13
Q12
Q11
Q10
Q9
Q8
Q7
J11
J12
J16
J17
0Ω
0Ω
0Ω
0Ω
J19
0Ω
J20
0Ω
J24
0Ω
I13
Q6
I12
Q5
I11
Q4
I10
Q3
I9
Q2
J25
J26
J28
Q1
Q0
I7
0Ω
A10
I6
J29
J32
I3
0Ω
0Ω
J42-12
A13
0Ω
0Ω
J42-11
A12
0Ω
I2
J31
J42-10
A11
I5
I4
J30
I8
0Ω
J42-9
I1
J42-13
A27
J42-27
C32
J42-96
C23
I0
J42-87
C18
NOTE: These solder jumpers (J11, J12, J16....) are present so that
the data channels can be connected together for driving both
channels with one pattern generator.
J42-82
C3
J42-67
Clock Input Circuit
VME CONNECTOR
R7
J42-77
CLK
C13
0Ω
R22
50Ω
J34
J33
SMA
0Ω
EXT_CLK
3-7
HI5828
CLK
PIN 28
Application Note 9855
Digital Input - Q Channel
VME Connections
Q13
MSB
J42-23
0Ω
A23
J42-88
J42-89
A28
J42-93
A29
J42-94
C30
LSB
J42-30
A30
R41
50Ω
R40
50Ω
R39
50Ω
R38
Q10
Q10
Q9
Q9
0Ω
Q9
Q8
R79
Q8
0Ω
Q8
50Ω
Q7
Q7
0Ω
50Ω
Q7
Q6
0Ω
Q6
50Ω
Q5
Q5
0Ω
Q5
R75
Q4
0Ω
Q4
Q3
0Ω
Q3
Q3
R26
R73
Q2
50Ω
R71
0Ω
PIN 36 OF U3 (HI5828)
PIN 37 OF U3 (HI5828)
PIN 38 OF U3 (HI5828)
PIN 39 OF U3 (HI5828)
Q2
R24
Q1
R72
0Ω
PIN 35 OF U3 (HI5828)
PIN 40 OF U3 (HI5828)
Q2
0Ω
PIN 34 OF U3 (HI5828)
R28
R74
50Ω
PIN 33 OF U3 (HI5828)
R30
Q4
50Ω
PIN 32 OF U3 (HI5828)
R32
R76
50Ω
PIN 31 OF U3 (HI5828)
R34
R77
Q6
PIN 30 OF U3 (HI5828)
R36
R78
C29
J42-29
Q11
R80
C28
J42-28
Q10
0Ω
C27
J42-92
50Ω
R81
A26
J42-91
Q12
Q11
Q11
0Ω
C26
J42-26
Q12
R82
A25
J42-90
Q12
0Ω
C25
J42-25
Q13
PIN 29 OF U3 (HI5828)
R42
R83
C24
J42-24
A24
Q13
50Ω
PIN 41 OF U3 (HI5828)
Q1
Q0
Q1
Q0
50Ω
R21
Q0
50Ω
PIN 42 OF U3 (HI5828)
R19
R70
NOTE: The 50Ω terminations are recommended if the DAC’S performance is not as expected, especially for CLOCK > 50MSPS.
3-8
Application Note 9855
Digital Input - I Channel
VME Connections
I13
MSB
J42-78
0Ω
C14
J42-14
0Ω
I9
J42-19
0Ω
I8
J42-85
C21
I11
R31
50Ω
R29
I10
I10
I9
I9
I8
I8
50Ω
I7
I7
I7
0Ω
I6
I6
0Ω
I5
I5
I5
0Ω
I4
I4
I4
0Ω
I3
I3
I3
R16
R87
0Ω
PIN 1 OF U3 (HI5828)
PIN 2 OF U3 (HI5828)
PIN 3 OF U3 (HI5828)
PIN 4 OF U3 (HI5828)
PIN 5 OF U3 (HI5828)
I2
PIN 6 OF U3 (HI5828)
I2
I2
50Ω
R14
I1
R86
0Ω
PIN 48 OF U3 (HI5828)
R18
R88
50Ω
PIN 47 OF U3 (HI5828)
R20
R89
50Ω
PIN 46 OF U3 (HI5828)
R23
R90
50Ω
PIN 45 OF U3 (HI5828)
R25
I6
50Ω
PIN 44 OF U3 (HI5828)
R27
R91
A20
LSB
50Ω
I11
50Ω
0Ω
C20
J42-20
R33
R92
A19
J42-84
50Ω
R93
A18
J42-83
C19
I10
0Ω
A17
J42-18
R35
R94
C17
J42-17
I11
0Ω
A16
J42-81
50Ω
R95
C16
J42-16
I12
I12
I12
R96
A15
J42-80
I13
0Ω
C15
J42-15
I13
PIN 43 OF U3 (HI5828)
R37
R97
A14
J42-79
50Ω
PIN 7 OF U3 (HI5828)
I1
I1
50Ω
R12
I0
R85
0Ω
I0
I0
50Ω
PIN 8 OF U3 (HI5828)
R9
R84
NOTE: The 50Ω terminations are recommended if the DAC’S performance is not as expected, especially for CLOCK > 50MSPS.
3-9
Application Note 9855
DAC Connections
SEE I-CHANNEL CIRCUIT
C43
1µF
J22
0Ω
EXT REF
J18
EXT
REF
(OPTIONAL)
SMA
3
4
5
38
QD3
QD1
QD2
QD0
37
2
0
1
NC
NC
39
13
42
ID11
12
43
ID10
45
44
41
40
C19
INT REF
0Ω
R43
2kΩ
J23
C39
0.1µF
34
8
9
7
33
32
10
31
11
30
12
13
29
28
SEE CLOCK CIRCUIT
27
DGND1
AGND1
26
25
0.1µF
0.1µF
AVDD1
CW: DEC
CCW: INC
AGND1
6
C46
R15
J21
0Ω
36
35
24
23
QCOMP1
AVDD
AGND
QCOMP2
SEE
OUTPUT
CIRCUIT
SEE
OUTPUT
CIRCUIT
AVDD1
C45
0.1µF
QOUTA
0.1µF
C23
QOUTB
AGND
ICOMP2
0.1µF
C20
NOT
USED
ID8
CLK
DGND
DVDD
13
14
C44
1µF
NOT
USED
QD11
SLEEP
22
C41
0.1µF
12
NC
FSADJ
11
AGND1
QD10
AGND
10
NC
20
21
8
9
QD8
QD9
U3
HI5828
19
7
ID1
ID0
REFIO
REFLO
1
0
QD7
ID2
18
6
QD5
QD6
IOUTB
J15
0Ω
2
ID4
ID3
AVDD
DVDD1
3
4
5
QD4
16
17
3
5
4
ID5
ICOMP1
IOUTA
6
15
1
2
7
ID9
9
10
11
46
ID6
ID7
48
47
8
SEE Q-CHANNEL CIRCUIT
NOT
USED
C40
1µF
C42
0.1µF
R17
1.18kΩ
R13
210Ω
R11
110kΩ
NOTES:
1. ICOMP1 and QCOMP1 MUST be connected together externally. Also, the 0.1µF capacitors (C19 and C20) are recommended, but if the layout
allows, a single capacitor placed directly between the ICOMP1 and QCOMP1 pins could serve both.
2. As with the COMP1 pins, a single 0.1µF capacitor could serve to decouple both of the AVDD pins (13 and 24) if placed directly between them.
Else, it is recommended that each AVDD pin have its own capacitor to analog ground.
3-10
Application Note 9855
Differential-to-Single Ended Transformer Outputs, I and Q
T2
J10 (SMA)
V OUT = (2 x I IOUTFS x R EQ)
PIN 15 OF HI5828 (U3), IOUTA
J2 (SMA)
100Ω
PIN 16 OF HI5828 (U3), IOUTB
R4
J9 (SMA)
R5
50Ω
R2
R3
50Ω
0Ω
REQ = THE EQUIVALENT IMPEDANCE
SEEN AT EACH DAC OUTPUT (~12.5Ω HERE)
50Ω
R2 NOT USED
J5
T1
J13 (SMA)
V OUT = (2 x I QOUTFS x R EQ)
PIN 22 OF HI5828 (U3), QOUTA
J1 (SMA)
100Ω
PIN 21 OF HI5828 (U3), QOUTB
R8
J14 (SMA)
R6
50Ω
R10
50Ω
R1
J6
0Ω
50Ω
R1 NOT USED
J5, J6 ALLOW TRANSFORMER CENTER TAP TO BE GROUNDED.
THIS BIASES THE DAC’S OUTPUT TO 0VDC.
Appendix D Evaluation Board Bill Of Materials
REFERENCE DESIGNATOR
QTY
DESCRIPTION
U3
1
HI5828IN, Intersil Dual 12-bit D/A Converter, 48 Pin LQFP
C2, 6
2
10µF, Tantalum Chip Cap, SMD, 10%, 10V
C3, 7, 19, 20, 23, 39, 42, 44-46
10
0.1µF, Ceramic Chip Cap, 0805, 10%, 50V
C4, 8, 40, 41, 43 (Not Populated)
0
1µF, Ceramic Chip Cap, 0805, +80-20%, 16V
R9, 12, 14, 16, 18-42 (Not Populated)
0
50Ω, Chip Resistor, 1210, 5%, 1/4W
R7, 70-97 (R70, 71, 84, 85 Not Populated)
29
0Ω, Chip Resistor, 0805, 1/8W
R4, 8
2
100Ω, Chip Resistor, 0805, 1/8W
R3, 5, 6, 10 (R1, 2 Not Populated)
4
49.9Ω, Chip Resistor, 0805, 1/8W
R15 (Not Populated)
0
25kΩ, Potentiometer Res, 3296W, 1/4W, 10%
R43
1
1.91kΩ, Chip Resistor, 0805, 1/8W
J3, 8
2
1x2 Header
Header Jumper
2
1x2 Header Jumper
T1, 2
2
Mini-Circuits, T1-1T KK81, Z1:Z2 ratio of 1:1
J42
1
96-Pin Eurocard, Right Angle, Female
J1, 2, 9, 10, 13, 14 (J33 Not Populated)
6
SMA Straight Jack, PCB Mount
L1, L2
2
0Ω, Chip Resistor, 1206, 1/8W, 5%
J11, 12, 16, 17, 19, 20, 24-26, 28-32 (Not Populated)
14
Solder Jumpers (Connects I and Q input bits together for driving
with the same pattern)
Mechanical Clamp (Not Populated)
0
DUT Clamp
Plastic Standoffs
4
3/4”
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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