HI5x60EVAL1 User’s Manual TM Application Note July 1999 AN9853 Description Features The HI5x60EVAL1 evaluation board provides a quick and easy method for evaluating the HI5860/5960 (12- or 14-bit), 125MSPS high speed DACs. The board is configured so that the converter outputs differential current into a transformer circuit to form an output voltage. The amount of current out of the DAC is determined by an external resistor and either an internal or external reference voltage. The CMOS digital inputs have optional external termination resistors. The evaluation board includes a VME digital interface that is compatible with all previous Intersil D/A evaluation boards. • 125MSPS 12- or 14-Bit CMOS DAC • Also Can Be Used to Evaluate the 8- and 10-Bit Versions, the HI5660 and HI5760 • Transformer-Coupled or Single-Ended SMA Outputs • Easily Selectable Internal or External Reference Ordering Information TEMP. RANGE (oC) PACKAGE PART NUMBER NUMBER OF BITS CLOCK SPEED HI5860SOICEVAL1 25 SOIC 12 125MHz HI5960SOICEVAL1 25 SOIC 14 125MHz Functional Block Diagram DCOM PLANE DVDD PLANE AVDD PLANE ACOM PLANE IOUTA SMA4 14 BITS VME 64 OR 96 PIN (B ROW NOT USED) XFMR DAC IOUT SMA3 IOUTB SMA2 CLOCK CLK SMA6 T1 REF SELECT J3 AVDD J2 SLEEP EXTERNAL REFERENCE (OPTIONAL) SMA1 3-1 J1 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 Application Note 9853 Functional Descriptions Voltage Reference The HI5860/5960 has an internal 1.2V voltage reference with a ±40ppm/oC drift coefficient over the industrial temperature range. The REFLO pin (16) selects the reference. Access to pin 16 is provided through the center pin of Jumper J3. This jumper is labeled INT and EXT for internal or external reference. The REFIO pin (17) provides access to the internal voltage reference, or can be overdriven if the user wishes to use an external source for the reference. The internal reference was not designed to drive an external load. Notice that a 0.1µF capacitor is placed as close as possible to the REFIO pin. This capacitor is necessary for ensuring a noise free reference voltage. If the user wishes to use an external reference voltage, jumper J1 must be in place and an external voltage reference provided via SMA1, labeled ‘EXT REF’. The recommended limits of the external reference are between 15mV and 1.2V. Performance of the converter can be expected to decline as the reference voltage is reduced due to the reduction in LSB current size. If the user wishes to amplitude modulate the DAC, the REFIO pin can be overdriven with a waveform. The input multiplying bandwidth of the REFIO input is approximately 1.4MHz when driving a 100mV signal into the REFIO pin, biased at 0.6VDC. The 3dB BW reduces as this amplitude is increased. It is necessary that the multiplying signal be DC offset so that the minimum and maximum peaks are positive and below 1.2V. For the external reference option, Jumper J3 must be changed so that pin 16 of the DAC is tied to the supply voltage, which is the EXT side of J3. The output current of the converter, IOUTA and IOUTB, is a function of the voltage reference used and the value of RSET (or R2) on the schematic. Output Current The output current of the device is set by choosing RSET and VFSADJ such that the resultant of the following equation is less than 20mA: IOUT = 32 x VFSADJ/RSET. REFIO (PIN 17) and FSADJ (PIN 18) of the DAC are the inputs to an operational amplifier. The voltage at the FSADJ pin (VFSADJ) will be approximately equal to the voltage at the REFIO pin, which will either be the value of the internal or external reference. For example, using the internal reference of (nominal) 1.2V and an RSET value of 1.91kΩ results in an IOUT of approximately 20mA (maximum allowed). Choose the output loading so that the Output Voltage Compliance Range is not violated (-0.3 to 1.25V). If an external reference is chosen, it should not exceed +1.2V. The output can be configured to drive a load resistor, a transformer, an operational amplifier, or any other type of output configuration so long as the output voltage compliance range and the maximum output current are not violated. 3-2 Transformer Output The evaluation board is configured with a transformer output configuration, shown in Figure 1. This configuration was chosen because it provides: even harmonic performance improvement due to the differential signaling; ~12.5Ω REQ loading to each output of the DAC; drive impedance of 50Ω for matching with a spectrum analyzer; and 2x voltage gain. The output of this configuration will be biased at zero volts and have an amplitude of ~500mV (VOUT) when the DAC is configured to drive IOUTFS of 20mA. HI5x60 VOUT = (2 x IOUTFS x REQ)V 50Ω PIN 21 IOUTB 100Ω PIN 22 IOUTA 50Ω 50Ω SPECTRUM ANALYZER’S INPUT IMPEDANCE FIGURE 1. Sleep The converter can be put into ‘sleep’ mode by connecting pin 15 of the DAC to either of the converter’s supply voltages. The sleep pin has an active pulldown current, so the pin can be left disconnected or be grounded for normal (awake) operation. On the evaluation board, jumper J2 is provided for controlling the sleep pin. Remove the jumper from J2 for normal operation and replace it for sleep mode. Power Supply(s) and Ground(s) The user can operate from either a single supply or from dual supplies. The supplies can be at different voltages. It is important to note that the digital inputs cannot switch more than 0.3V above the digital supply voltage. The evaluation board contains two power supply connections, (analog) AVDD1 and (digital) DVDD1, each with their own ground wire. Dual ground and power planes is the recommended configuration, with the ground planes connected at a single point near the DAC. Digital Inputs The DAC is designed to accept CMOS inputs. The switching voltage is approximately 1/2 of the digital power supply voltage, so reducing the power supply can make the DAC compatible to smaller levels. The digital inputs (data and clock) cannot go +0.3V higher than the digital supply voltage, else diode ESD protection can begin to turn on and performance could be degraded. The clock source can be a sine wave, with some degradation in performance. The recommended clock is a square wave. The timing between the clock and the data will affect spectral performance and functionality. Minimum setup and hold times are specified in the datasheet to represent the point at which the DAC begins to lose bits. Optimal setup and hold Application Note 9853 times vary with the clock rate to output frequency ratio. A general rule is that the lower the FCLK/FOUT ratio is, the higher the setup time should be to achieve optimum spectral behavior. Attach the evaluation board to the power supply(s). Connect the bits from the data generator to the evaluation board, preferably by using a male, 64 or 96-pin VME (Versa Module Eurocard) connector that mates with the evaluation board. Connect the clock source to the evaluation board, also preferably through the VME connector. Failure to make clean and short connections to the data input lines and clock source will result in a decrease in spectral performance. Getting Started A summary of the external supplies, equipment, and signal sources needed to operate the board is given below: Using a coaxial cable with the proper SMA connector, attach the output of the converter, IOUT, to the measurement equipment that will be evaluating the converter’s performance. Make sure that the jumpers are in their proper placement. Consult the ‘Voltage Reference’ section and the ‘Sleep’ section of this document for a definition of the jumpers’ functionality. 1. +5V to +3V supply for HI5x60 DAC. 2. Pattern Generator. 3. Square wave clock source (usually part of the Pattern Generator). 4. Spectrum Analyzer or Oscilloscope for viewing the output of the converter. HP-SMA TEST BOARD (INTERSIL MADE) CLK CLK FEMALE 64 PIN VME CONNECTOR 16 BITS AVAILABLE MALE 96 PIN VME CONNECTOR HI5X60 EVALUATION BOARD 14 BITS CLOCK HI5X60 DAC +5V TO +3V POWER SUPPLY 50Ω SMA CABLE HEWLETT PACKARD HP80000 PATTERN GENERATOR SPECTRUM ANALYZER FIGURE 2. INTERSIL HI5x60 EVALUATION SYSTEM SETUP BLOCK DIAGRAM 3-3 Application Note 9853 Appendix A Description of Architecture The segmented current source architecture has the ability to improve the converter’s performance by reducing the amount of current that is switching at any one time. In traditional architectures, major transition points required the converter to switch on or off large amounts of current. In a traditional 10-bit R/2R ladder design, for example, the midscale transition required approximately equal amounts of currents switching on and off. In a segmented current source arrangement, transitions such as midscale become one in which you simply have an additional intermediate current source turning on and several minor ones turning off. In the case of the HI5760, there are 31 intermediate current segments that represent the 5 MSBs and five, binary- weighted current sources representing each of the five LSBs. See the Functional Block Diagram in the datasheet for a visual representation. To relate the midscale transition example to the HI5760, consider the following: The code 0111111111 would be represented by 15 intermediate current segments and each of the 5 LSB current sources all turned on. To transition to code 1000000000 would simply require turning off the 5 LSB current sources and turning on the next intermediate current segment, bringing the total amount of current switching at this ‘major’ code transition equal to the same amount switching at 30 other code transition points in the code ramp from 0 to 1023, so that the total glitch energy is distributed more evenly. Appendix B Pin Descriptions PIN NO. PIN NAME PIN DESCRIPTION 1-14 D13 (MSB) Through D0 (LSB) For the 14-bit, HI5960, these are digital data bit-13, (most significant bit) through digital data bit-0, (least significant bit). Pins 13 and 14 are NC for the 12-bit, HI5860. 15 SLEEP Control Pin for Power-Down Mode. Sleep mode is active high; Connect to ground for normal mode. Sleep pin has internal 20µA active pull-down current. 16 REFLO Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference. 17 REFIO Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is enabled. Use 0.1µF cap to ground unless overdriving with a waveform. 18 FSADJ Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full scale output current (IOUTFS) = 32 x VFSADJ/RSET, (maximum IOUTFS = 20mA). 19 COMP1 For use in reducing noise. Recommended: Connect 0.1µF from COMP1 to AVDD . 20, 25 ACOM Analog Ground. 21 IOUTB The complementary current output of the device. Full scale output current is achieved when all input bits are set to binary 0. 22 IOUTA Current output of the device. Full scale output current is achieved when all input bits are set to binary 1. 23 COMP2 Connect to ACOM through a 0.1µF capacitor. 24 AVDD Analog supply (+3V to +5V). 26 DCOM Digital ground. 27 DVDD Digital supply (+3V to +5V). 28 CLK Input for clock. Positive edge of clock latches data. 3-4 Application Note 9853 Appendix C Circuit Board Layout FIGURE 3. BOTTOM (LAYER 4, VIEWED FROM BOTTOM) FIGURE 4. GROUND (LAYER 3, VIEWED FROM BOTTOM) 3-5 Application Note 9853 Appendix C Circuit Board Layout (Continued) FIGURE 5. POWER (LAYER 2, VIEWED FROM BOTTOM) FIGURE 6. TOP SIDE (LAYER 1, VIEWED FROM BOTTOM) 3-6 Appendix D Schematic SMA1 EXT REF (OPTIONAL) NOTE: JUMPERS SHOWN IN SHIPPED MODE: J2: SLEEP IS UNINSTALLED. J3: INTERNAL REFERENCE IS ENABLED. J1: EXTERNAL REFERENCE IS UNINSTALLED. VME CONNECTOR (96 PIN) A8 LSB P1-8 A30 0Ω 0Ω R31 A11 A28 A12 R4 11 0Ω R32 10 C28 A13 C27 A27 P1-27 A26 C32 C26 C23 R33 0Ω P1-87 A25 C18 0Ω C25 C3 P1-67 A24 0Ω P1-88 MSB P1-77 8 50Ω R13 R20 50Ω R17 5 50Ω R10 4 50Ω R18 6 0Ω 5 R7 0Ω 4 R36 3 0Ω D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 2 R37 0Ω 1 50Ω 50Ω R19 C 50Ω R30 C CLK C9 10µF AVDD1 R39 0Ω R29 0Ω NOTE: BOARD IS NOT SHIPPED WITH POTENTIOMETER R1 20kΩ R1 2kΩ 0.1µF C8 10µF 0.1µF SMA2 C3 T1 1:1 0Ω R24 SMA3 IOUT 100Ω R27 0Ω SMA4 C5 0.1µF E5 DVDD C7 0.1µF PLANE FB1 10µH R28 50Ω C2 DIGITAL GROUND PLANE + NOTE: ALL OTHER PINS ON THE 64 PIN, VME CONNECTOR ARE DISCONNECTED. (ROW B WAS NOT USED) SMA6 EXTRA SMA5 R2 DCOM1 C 2 J1 C1 FB2 10µH R12 1 1 0.1µF 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DVDD1 R9 R38 2 R11 2 0Ω 2 C 3 50Ω R8 0Ω P1-23 C13 CLK R21 J2 1 1 3 U1 SLEEP REFLO REFIO FSADJ COMP1 ACOM IOUTB IOUTA COMP2 AVDD ACOM DCOM DVDD CLOCK + A23 50Ω 6 R35 P1-24 C24 9 7 50Ω R6 P1-89 14 13 12 11 10 9 8 7 6 5 4 3 2 1 7 P1-25 P1-82 R14 8 R34 P1-90 50Ω (RGND) 0Ω GROUND CONNECT 9 P1-26 P1-96 R22 10 0Ω P1-91 50Ω 11 R5 P1-92 P1-13 R15 PROTO E3 AREA E2 J3 C6 0.1µF ACOM1 ANALOG GROUND PLANE R26 R25 50Ω C4 0.1µF R1 (20kΩ POT, 3296W) R26 (100Ω, 0805) R25, 28 (50Ω, 0805) R10-23, 30 (50Ω, 1206) R3-9, 24, 27, 29, 31-39, RGND (0Ω, 0805) T1 (1:1 TRANSFORMER, KK81) R2 (2kΩ, 0805) C1-5, 6, 7 (0.1µF, 0805) C8, 9 (10µF, CASE B) FB1, 2 (10µH, FERRITE BEAD) SMA1-6 (STRAIGHT JACK, PCB MOUNT) P1 (64 PIN VME CONNECTOR) E4 J1, 3 (1X2 HEADERS) AVDD J2 (1X3 HEADER) PLANE U1 (HI5x60IB) Application Note 9853 P1-28 P1-12 12 50Ω 12 0Ω P1-93 P1-11 R23 TP1 ANALOG GROUND 2X1 JUMPERS 0Ω 13 50Ω TP2 DIGITAL GROUND NOTE: EXTRA SMA5 AND PROTO ARE FOR OVERDRIVING COMP1 (NOT NECESSARY) 3X1 JUMPERS C29 R16 13 P1-29 P1-10 50Ω 2X1 JUMPERS 3-7 P1-94 A29 14 R3 P1-9 A10 14 P1-30 C30 A9 NOTE: 50Ω TERMINATION RESISTORS ARE NOT SHIPPED WITH BOARD E1 Application Note 9853 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. 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