No. AN9329 Application Note September 1993 Using the HI1176/HI1171 Evaluation Board Introduction TABLE 1. SUPPLY VOLTAGE The HI1176 (8-bit, 20MSPS, ADC) and the HI1171 (8-bit, 40MHz, DAC) evaluation board is composed of a main board common to either type, to which is added a sub board specific to each part. Each sub board is connected to the main board through a socket. The main board has an input interface, a clock buffer, and a latch. ITEM MIN TYP MAX UNIT +5V - - 150 mA -5V - - 20 mA Each of the sub boards is mounted with an HI1176 and HI1171 respectively. TABLE 2. ANALOG OUTPUT (HI1171) Features ITEM • 8-Bit Resolution Analog Output MIN TYP MAX UNIT 0.5 2.0 2.1 V • 20MHz Conversion Rate • CMOS Digital Input Level Functional Block Diagram VOUT 8 VREF VIN ADC SOCKET 8 ANALOG INPUT INTERFACE DATA LATCH DAC SOCKET ANALOG PROTOTYPE AREA DIGITAL PROTOTYPE AREA 4 CLOCK BUFFER OSC ANALOG PROTOTYPE AREA SW GND +5V -5V CLOCK OE SEL SYNC CLE BLK THE HI1176JCQ AND HI1171JCB ADC/DAC EVALUATION BOARD CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 1 Application Note 9329 TABLE 3. OUTPUT FORMAT (HI1176) ANALOG INPUT VOLTAGE STEP VRT 0 • • • • • • • • • 127 TABLE 3. OUTPUT FORMAT (HI1176) (Continued) DIGITAL OUTPUT CODE MSB 1 ANALOG INPUT VOLTAGE STEP LSB 1 1 1 1 1 1 1 • • • 1 0 0 0 0 0 0 0 • • • 128 • • • • • • VRB 255 DIGITAL OUTPUT CODE MSB 0 1 1 0 0 0 14 SYNC R 130K C 1000pF NC 17 16 15 13 SEL 14 13 12 11 10 12 CLK 9 VRT 18 17 8 11 DVDD VRTS 19 18 7 10 D7 AVDD 20 19 6 9 D6 D5 AVDD 21 VIN 22 AVSS 23 5 8 21 4 7 D4 20 C3 0.1 HI1176JCQ C5 22 3 6 D3 AVSS 24 23 2 5 D2 VRBS 25 24 1 4 D1 3 D0 2 DVSS 1 OE VRB 26 25 26 27 28 29 30 31 32 C2 0.1 VREF 27 C1 0.01 CLE 28 NC 13 13 12 NC 14 14 11 11 10 CLK C4 12 NC DVSS AVSS 15 15 10 AVSS 16 16 9 9 BLK IREF 17 17 8 8 D7 VREF 18 18 7 7 D6 D5 C2 HI1171JCB 19 6 6 20 5 5 D4 IO 21 21 4 4 D3 IO 22 22 3 3 D2 NC 23 23 2 2 D1 DVDD 24 24 1 1 D0 AVDD 19 AVDD 20 C3 C1 FIGURE 1. CMOS ADC/DAC PERIPHERAL CIRCUIT BOARDS (Sub Boards) 2 1 1 1 1 1 0 0 0 0 • • • PW 15 NC 16 LSB 0 Application Note 9329 Adjustment Method 1. VREF adjustment (VR1, VR2) - The A/D converter reference voltage. VRB is adjusted by VR1 and VRT is adjusted by VR2. When self bias is used, there is no need for adjustment. Reference voltage is set to self bias mode at delivery. ANALOG INPUT TPW0 EXTERNAL CLOCK 2. Clamp reference mode voltage adjustment (VR3) - Clamp reference voltage is set by VR3. TPW1 AD CLOCK tPD (A/D) 3. DAC output full scale adjustment (VR4) - Full scale voltage of the D/A converter output is adjusted to approximately 2.0V at shipment. tDD LATCH OUTPUT 4. Sync (clamp) pulse interface (VR5) - This adjustment enables interface with the signal generator. At shipment, this adjustment is performed to obtain a threshold of approximately 2.5V to an H sync of 0V to 5V. tS tH DA CLOCK tPD (D/A) 5. OE, SEL, Sync, BLK, CLE, Sync INT - The following pins are set on the main board: OE, SEL, Sync, CLE, Sync INT (HI1176) and BLK (HI1171). For the pins function, refer to the specifications. The difference between Sync pin and Sync INT pin is that you input a pulse above 3.5Vp-p to Sync INT pin. The pulse threshold is set through VR5. For input through Sync pin, pulse is input at TTL or CMOS level. In this case cut the line between the Sync pin and Sync INT pin. DA OUTPUT Notes on Operation 1. Reference voltage - Shorting VRT and VRTS, VRB and VRBS will activate the self bias function that generates VRT = 2.6V and VRB = 0.5V. On the evaluation board either self-bias or the external reference voltage can be selected depending on SW2 and SW3. At shipment from the factory, reference voltage is in self bias mode. To provide external reference voltage, adjust the dynamic range (VRT - VRB) to above 1.8VP-P . The PCB is shipped with the main board pins set as follows. • OE Low (A/D Output ON) • SEL Low (Pulse generated with Sync falling edge as trigger) • Sync Line junction with Sync INT pin • CLE Low (Clamp function ON) 1. provided from an external signal generator • BLK Low (Blanking OFF) 2. using the crystal oscillator (built-in clock driver). 2. Clock input - There are two modes for the evaluation board's clock input. 6. Clamp pulse input method - One method is to directly input the clamp pulse. Another method is to use the built-in multivibrator. The method used selected by using SW1. To use the built-in monostable multivibrator, it is necessary to mount the HI1176 sub board. R and C set the pulse width (ex. R = 130K, C = 100P, TPW = 2.75µs). One of the two modes is selected using the switch SW4 on the evaluation board. 3. The 2 latch ICs, 74S174, are not absolutely necessary for the evaluation of the ADC and the DAC. Operation will still be normal if the ADCs output is directly input to the DAC. However, since the ADCs output is usually converted by a DAC after some signal processing, the 74S174s were mounted to provide a signal processing example. TABLE 4. TIMING CHART ITEM SYMBOL MIN TYP MAX UNIT Clock High Time TPW1 25 - - ns Clock Low Time TPW0 25 - - ns Clock Delay TDC - - 24 ns tPD (A/D) - 18 30 ns Data Delay (Latch) tDD - - 17 ns Setup Time tS 10 - - ns Hold Time tH 2 - - ns tPD (D/A) - 10 - ns Data Delay A/D Data Delay D/A 4. Setting CLE High will disable the clamp function. The DC portion of the input signal will be blocked by C2. The ADC side of C2 will settle to about 1/2 (VRT + VRB). If it is desired to DC couple the input to the ADC, remove R2 and short C2. Q3 can also be used as a buffer. 5. Clamp pulse latch - On the evaluation board, the clamp is latched with the ADC sampling CLK and is then input to either the PW pin or Sync pin. A slight beat may be generated as vertical sag according to the relation between sampling frequency and clamp frequency. If there are no problems with VSAG, latch is not necessary. 6. Prototype Areas - There is a group of throughholes on the analog input, output, and logic. These can be used when mounting additonal circuits on the evaluation board. The connector hole on the DAC board is used to mount the test chassis and the mount jack. 3 DVSS DVDD 0.01µ OUTPUT GAIN ADJUST 13 NC NC 12 14 NC DVSS 11 VR4 20K 15 AVSS CLK 10 10 16 AVSS BLK 9 11 17 IREF D7 8 12 18 VREF D6 7 13 19 AVDD D5 6 14 3 20 AVDD D4 5 15 2 21 IO D3 4 16 DVDD CLEAR 1 22 IO D2 3 23 NC D1 2 24 DVDD D0 1 R8 3.3K VRB ADJUST C5 0.1µ VRT ADJUST AVDD R6 510Ω (R) Q2 R5 510Ω VIDEO INPUT 4 C3 0.01µ R2 75Ω R1 100K C4 0.01µ SW3 CLAMP ADJUST VR3 200K 9 CLK SW1 5 4 DVSS 8 7 11 6 15 PW SYNC 14 12 16 NC SEL 13 13 17 NC CLK 12 14 3 18 VRT DVDD 11 15 2 19 VRTS D7 10 20 AVDD D6 9 21 AVDD D5 8 22 VIN D4 7 23 AVSS D3 6 24 AVSS D2 5 25 VRBS D1 4 26 VRB D0 3 27 VREF DVSS 2 28 CLE OE 1 47µ/10 + L1 100mH 0.01µ 74S174 (LATCH) 5 4 16 DVDD CLEAR 1 7 0.01µ 8 DVSS 7 9 6 5 74504 OR 11 4 74HC04 (INV BUFFER) 12 3 DVDD DVSS DVSS 6 0.01µ 13 2 14 DVDD 1 OSC OUT 14 SW4 10 + 47µ -5V +5V GND AVDD DVDD + C1 470µ R3 C2 10µ 75Ω + 6 74S174 (LATCH) 0.01µ AVSS Q3 7 10 VOUT SW2 DVSS 8 Application Note 9329 VR1 2K R4 VR2 510Ω 2K Q1 R7 200K 9 CLK RIN = 75Ω SYNC OSC SWITCH EXT/INT BLK OE SEL CEL R9 75 EXTERNAL CLOCK INPUT SYNC INT 47µ VR5 20K R10 75 Application Note 9329 Evaluation Board COMPONENT SIDE SOLDER SIDE All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 5