DATASHEET

HI3338
®
Data Sheet
July 2004
FN4134.3
8-Bit, CMOS R2R D/A Converter
Features
The HI3338 family are CMOS high speed R2R voltage
output digital-to-analog converters. They can operate from a
single +5V supply, at video speeds, and can produce
“rail-to-rail” output swings. Internal level shifters and a pin for
an optional second supply provide for an output range below
digital ground.
• CMOS Low Power (Typ) . . . . . . . . . . . . . . . . . . . . .100mW
• R2R Output, Segmented for Low “Glitch”
• CMOS/TTL Compatible Inputs
• Fast Settling (Typ) . . . . . . . . . . . . . . . . . . 20ns to 1/2 LSB
• Feedthrough Latch for Clocked or Unclocked Use
The data complement control allows the inversion of input
data while the latch enable control provides either
feedthrough or latched operation. Both ends of the R2R
ladder network are available externally and may be
modulated for gain or offset adjustments. In addition, “glitch”
energy has been kept very low by segmenting and
thermometer encoding of the upper 3 bits.
The HI3338 is manufactured to give low dynamic power
dissipation, low output capacitance, and inherent latch-up
resistance.
PART NUMBER
• Data Complement Control
• High Update Rate (Typ) . . . . . . . . . . . . . . . . . . . . . 50MHz
• Unipolar or Bipolar Operation
• Linearity (INL)
- HI3338KIB . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.75 LSB
• Pb-free Available
Applications
Ordering Information
TEMP.
RANGE (°C)
• Accuracy (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB
PACKAGE
PKG.
DWG. #
• TV/Video Display
• High Speed Oscilloscope Display
HI3338KIB
-40 to 85
16 Ld SOIC
M16.3
• Digital Waveform Generator
HI3338KIBZ
(Note)
-40 to 85
16 Ld SOIC
(Pb-free)
M16.3
• Direct Digital Frequency Synthesis
• Wireless Communication
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
1
Pinout
HI3338 (SOIC)
TOP VIEW
D7
1
16 VDD
D6
2
15 LE
D5
3
14 COMP
D4
4
13 VREF+
D3
5
12 VOUT
D2
6
11 VREF -
D1
7
10 VEE
VSS
8
9 D0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright Harris Corporation 1997. Copyright Intersil Americas Inc. 2003, 2004. All Rights Reserved
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HI3338
Functional Diagram
16
13
VDD
VREF +
8R
15
LE
8R
12
VOUT
8R
3-BIT
TO 7-LINE
THERMOMETER
ENCODER
14
COMP
D7
8R
4R
R
1
4R
D6
D5
D4
D3
D2
D1
D0
VSS
2
LEVEL
SHIFTERS
FEEDTHROUGH
LATCHES
3
2R
2R
4
5
2R
6
2R
R
R
R
R
7
2R
9
8
2R
R
R
2R
11
VREF 10
R ≅ 160Ω
Die Characteristics
DIE DIMENSIONS:
2,740µm x 3,310µm x 530 ±50µm
METALLIZATION:
Type: Al with 0.8% Si
Thickness: 11kÅ ±1kÅ
GLASSIVATION:
Type: 3% PSG
Thickness: 13kÅ ±2.6kÅ
2
VEE
HI3338
Absolute Maximum Ratings
Thermal Information
DC Supply-Voltage Range . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +8V
(VDD - VSS or VDD - VEE , Whichever Is Greater)
Input Voltage Range
Digital Inputs (LE, COMP D0 - D7). . . . VSS - 0.5V to VDD + 0.5V
Analog Pins (VREF+, VREF -, VOUT) . . . .VDD - 8V to VDD + 0.5V
DC Input Current
Digital Inputs (LE, COMP, D0 - D7) . . . . . . . . . . . . . . . . . . ±20mA
Recommended Supply Voltage Range . . . . . . . . . . . . . 4.5V to 7.5V
Thermal Resistance (Typical)
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range, TSTG . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(Lead Tips Only)
Operating Conditions
HI3338KIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
TA = 25oC, VDD = 5V, VREF+ = 4.608V, VSS = VEE = VREF - = GND, LE clocked at 20MHz, RL ≥ 1MΩ,
Unless Otherwise Specified
Electrical Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
8
-
-
Bits
ACCURACY
Resolution
Integral Linearity Error
See Figure 4
-
-
±0.75
LSB
Differential Linearity Error
See Figure 4
-
-
±0.5
LSB
Gain Error
Input Code = FFHEX , See Figure 3
-
-
±0.5
LSB
Offset Error
Input Code = 00HEX , See Figure 3
-
-
±0.25
LSB
DIGITAL INPUT TIMING
Update Rate
To Maintain 1/2 LSB Settling
DC
50
-
MHz
Update Rate
VREF - = VEE = -2.5V, VREF+ = +2.5V
DC
20
-
MHz
Set Up Time tSU1
For Low Glitch
-
-2
-
ns
Set Up Time tSU2
For Data Store
-
8
-
ns
Hold Time tH
For Data Store
-
5
-
ns
Latch Pulse Width tW
For Data Store
-
5
-
ns
Latch Pulse Width tW
VREF - = VEE = -2.5V, VREF+ = +2.5V
-
25
-
ns
OUTPUT PARAMETERS
RL Adjusted for 1VP-P Output
Output Delay tD1
From LE Edge
-
25
-
ns
Output Delay tD2
From Data Changing
-
22
-
ns
Rise Time tr
10% to 90% of Output
-
4
-
ns
Settling Time tS
10% to Settling to 1/2 LSB
-
20
-
ns
Output Impedance
VREF+ = 6V, VDD = 6V
120
160
200
Ω
-
150
-
pV-s
-
250
-
pV-s
Glitch Area
Glitch Area
VREF - = VEE = -2.5V, VREF+ = +2.5V
REFERENCE VOLTAGE
VREF+ Range
(+) Full Scale (Note 1)
VREF - + 3
-
VDD
V
VREF - Range
(-) Full Scale (Note 1)
VEE
-
VREF+ - 3
V
VREF+ Input Current
VREF+ = 6V, VDD = 6V
-
40
50
mA
3
HI3338
TA = 25oC, VDD = 5V, VREF+ = 4.608V, VSS = VEE = VREF - = GND, LE clocked at 20MHz, RL ≥ 1MΩ,
Unless Otherwise Specified (Continued)
Electrical Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
LE = Low, D0 - D7 = High
-
100
220
µA
LE = Low, D0 - D7 = Low
-
-
100
µA
Dynamic IDD or IEE
VOUT = 10MHz, 0V to 5V Square Wave
-
20
-
mA
Dynamic IDD or IEE
VOUT = 10MHz, ±2.5V Square Wave
-
25
-
mA
VDD Rejection
50kHz Sine Wave Applied
-
3
-
mV/V
VEE Rejection
50kHz Sine Wave Applied
-
1
-
mV/V
SUPPLY VOLTAGE
Static IDD or IEE
DIGITAL INPUTS
D0 - D7, LE, COMP
High Level Input Voltage
Note 1
2
-
-
V
Low Level Input Voltage
Note 1
-
-
0.8
V
Leakage Current
-
±1
±5
µA
Capacitance
-
5
-
pF
-
200
-
ppm/×oC
TEMPERATURE COEFFICIENTS
Output Impedance
NOTE:
1. Parameter not tested, but guaranteed by design or characterization.
Timing Diagrams
INPUT
DATA
INPUT DATA
tSU2
tSU1
tW
LATCH
ENABLE
LATCHED
DATA
FEEDTHROUGH
tH
LATCH
ENABLE
tD1
LATCHED
tD2
OUTPUT
VOLTAGE
tS
tr
1/ LSB
2
90%
10%
1/ LSB
2
FIGURE 1. DATA TO LATCH ENABLE TIMING
4
FIGURE 2. DATA AND LATCH ENABLE TO OUTPUT TIMING
HI3338
Latch Operation
Pin Descriptions
PIN
NAME
DESCRIPTION
1
D7
2
D6
Input
3
D5
Data
4
D4
Bits
5
D3
(High = True)
6
D2
7
D1
8
VSS
Digital Ground
9
D0
Least Significant Bit. Input Data Bit
10
VEE
Analog Ground
11
VREF -
Reference Voltage Negative Input
12
VOUT
Analog Output
13
VREF+ Reference Voltage Positive Input
14
COMP
15
LE
16
VDD
Most Significant Bit
Data Complement Control input. Active High
Latch Enable Input. Active Low
Digital Power Supply, +5V
Digital Signal Path
The digital inputs (LE, COMP, and D0 - D7) are of TTL
compatible HCT High Speed CMOS design: the loading is
essentially capacitive and the logic threshold is typically
1.5V.
The 8 data bits, D0 (weighted 20) through D7 (weighted 27),
are applied to Exclusive OR gates (see Functional Diagram).
The COMP (data complement) control provides the second
input to the gates: if COMP is high, the data bits will be
inverted as they pass through.
Data is fed from input to output while LE is low: LE should be
tied low for non-clocked operation.
Non-clocked operation or changing data while LE is low is
not recommended for applications requiring low output
“glitch” energy: there is no guarantee of the simultaneous
changing of input data or the equal propagation delay of all
bits through the converter. Several parameters are given if
the converter is to be used in either of these modes: tD2
gives the delay from the input changing to the output
changing (10%), while tSU2 and tH give the set up and hold
times (referred to LE rising edge) needed to latch data. See
Figures 1 and 2.
Clocked operation is needed for low “glitch” energy use. Data
must meet the given tSU1 set up time to the LE falling edge,
and the tH hold time from the LE rising edge. The delay to
the output changing, tD1 , is now referred to the LE falling
edge.
There is no need for a square wave LE clock; LE must only
meet the minimum tW pulse width for successful latch
operation. Generally, output timing (desired accuracy of
settling) sets the upper limit of usable clock frequency.
Output Structure
The latches feed data to a row of high current CMOS drivers,
which in turn feed a modified R2R ladder network.
The “N” channel (pull down) transistor of each driver plus
the bottom “2R” resistor are returned to VREF - this is the
(-) full-scale reference. The “P” channel (pull up) transistor
of each driver is returned to VREF+, the (+) full-scale
reference.
In unipolar operation, VREF- would typically be returned to
analog ground, but may be raised above ground (see
specifications). There is substantial code dependent current
that flows from VREF+ to VREF - (see VREF+ input current in
specifications), so VREF - should have a low impedance path
to ground.
The input data and the LE (latch enable) signals are next
applied to a level shifter. The inputs, operating between the
levels of VDD and VSS , are shifted to operate between VDD
and VEE . VEE optionally at ground or at a negative voltage,
will be discussed under bipolar operation. All further logic
elements except the output drivers operate from the VDD
and VEE supplies.
In bipolar operation, VREF - would be returned to a negative
voltage (the maximum voltage rating to VDD must be
observed). VEE , which supplies the gate potential for the
output drivers, must be returned to a point at least as
negative as VREF -. Note that the maximum clocking speed
decreases when the bipolar mode is used.
The upper 3 bits of data, D5 through D7, are input to a 3-to-7
line bar graph encoder. The encoder outputs and D0 through
D4 are applied to a feedthrough latch, which is controlled by
LE (latch enable).
The ideal 8-bit D/A would have an output equal to VREF with an input code of 00HEX (zero scale output), and an
output equal to 255/256 of VREF+ (referred to VREF -) with
an input code of FFHEX (full scale output). The difference
between the ideal and actual values of these two parameters
are the OFFSET and GAIN errors, respectively; see
Figure 3.
5
Static Characteristics
HI3338
If the code into an 8-bit D/A is changed by 1 count, the
output should change by 1/255 (full-scale output-zero scale
output). A deviation from this step size is a differential
linearity error, see Figure 4. Note that the error is expressed
in fractions of the ideal step size (usually called an LSB).
Also note that if the (-) differential linearity error is less (in
absolute numbers) than 1 LSB, the device is monotonic.
(The output will always increase for increasing code or
decrease for decreasing code).
If the code into an 8-bit D/A is at any value, say “N”, the
output voltage should be N/255 of the full-scale output
(referred to the zero-scale output). Any deviation from that
output is an integral linearity error, usually expressed in
LSBs. See Figure 4.
OUTPUT VOLTAGE AS A FRACTION OF VREF+ - VREF -
Note that OFFSET and GAIN errors do not affect integral
linearity, as the linearity is referenced to actual zero and full
scale outputs, not ideal. Absolute accuracy would have to
also take these errors into account.
GAIN ERROR (SHOWN -)
255/256
= IDEAL TRANSFER CURVE
= ACTUAL TRANSFER CURVE
254/256
253/256
2/256
1/256
0
00
01
Keeping the full-scale range (VREF+ - VREF -) as high as
possible gives the best linearity and lowest “glitch” energy
(referred to 1V). This provides the best “P” and “N” channel
gate drives (hence saturation resistance) and propagation
delays. The VREF+ (and VREF - if bipolar) terminal should be
well bypassed as near the chip as possible.
“Glitch” energy is defined as a spurious voltage that occurs
as the output is changed from one voltage to another. In a
binary input converter, it is usually highest at the most
significant bit transition (7FHEX to 80HEX for an 8-bit device),
and can be measured by displaying the output as the input
code alternates around that point. The “glitch” energy is the
area between the actual output display and an ideal one LSB
step voltage (subtracting negative area from positive), at
either the positive or negative-going step. It is usually
expressed in pV-s.
The HI3338 uses a modified R2R ladder, where the 3 most
significant bits drive a bar graph decoder and 7 equally
weighted resistors. This makes the “glitch” energy at each 1/8
scale transition (1FHEX to 20HEX , 3FHEX to 40HEX , etc.)
essentially equal, and far less than the MSB transition would
otherwise display.
For the purpose of comparison to other converters, the
output should be resistively divided to 1V full scale. Figure 5
shows a typical hook-up for checking “glitch” energy or
settling time.
OFFSET
ERROR
(SHOWN +)
3/256
Dynamic Characteristics
02
03
FD
FE
FF
INPUT CODE IN HEXADECIMAL (COMP = LOW)
FIGURE 3. D/A OFFSET AND GAIN ERROR
STRAIGHT LINE
FROM “0” SCALE
TO FULL SCALE
VOLTAGE
= IDEAL TRANSFER CURVE
= ACTUAL TRANSFER CURVE
The settling time of the A/D is mainly a function of the output
resistance (approximately 160Ω in parallel with the load
resistance) and the load plus internal chip capacitance. Both
“glitch” energy and settling time measurements require very
good circuit and probe grounding: a probe tip connector such
as Tektronix part number 131-0258-00 is recommended.
TABLE 1. OUTPUT VOLTAGE vs INPUT CODE AND VREF
VREF+
VREF STEP SIZE
2.50V
5.00V 4.608V 2.56V
5.12V
-2.56V -2.50V
0
0
0
0.0200V 0.0195V 0.0180V 0.0200V 0.0195V
Input Code
111111112 = FFHEX 5.1000V 4.9805V 4.5900V 2.5400V 2.4805V
111111102 = FEHEX 5.0800 4.9610 4.5720 2.5200 2.4610
OUTPUT VOLTAGE
•
•
•
INTEGRAL LINEARITY
ERROR (SHOWN -)
A
B
C
0
00
A = IDEAL STEP SIZE (1/255 OF FULL
SCALE -“0” SCALE VOLTAGE)
B - A = +DIFFERENTIAL LINEARITY ERROR
C - A = -DIFFERENTIAL LINEARITY ERROR
INPUT CODE
FIGURE 4. D/A INTEGRAL AND DIFFERENTIAL LINEARITY
6
100000012 = 81HEX 2.5800
100000002 = 80HEX 2.5600
011111112 = 7FHEX 2.5400
2.5195
2.5000
2.4805
2.3220 0.0200 0.0195
2.3040 0.0000 0.0000
2.2860 - 0.0200 -0.0195
0.0195
0.0000
0.0180
0.0000
•
•
•
000000012 = 01HEX
000000002 = 00HEX
0.0200
0.0000
-2.5400 -2.4805
-2.5600 -2.5000
HI3338
HI3338
+5V
15 LE
CLOCK
+2.5V
-2.5V
1-7, 9
D0 - D7
8 DATA BITS
VOUT
16
+5V
VREF+
VDD
R1
12
REMOTE
VOUT
13
+
PROBE TIP
OR BNC
CONNECTOR
+
14
8
VREF -
COMP
VSS
VEE
R3
R2
11
10
+
DIGITAL
GROUND
ANALOG
GROUND
FUNCTION
CONNECTOR
R1
R2
R3
VOUT(P-P)
Probe Tip
82Ω
62Ω
N/C
1V
Match 93Ω Cable
BNC
75
160
93
1V
Match 75Ω Cable
BNC
18
130
75
1V
Match 50Ω Cable
BNC
Short
75
50
0.79V
Oscilloscope Display
NOTES:
2. VOUT(P-P) is approximate, and will vary as ROUT of D/A varies.
3. All drawn capacitors are 0.1µF multilayer ceramic/4.7µF tantalum.
4. Dashed connections are for unipolar operation. Solid connection are for bipolar operation.
FIGURE 5. HI3338 DYNAMIC TEST CIRCUIT
7
HI3338
+6V
4.7µF TAN
+
HI3338
15
CLOCK
VOUT 12
16
+
4.7µF
TAN
0.1µF
CER.
14
8
VDD
+3.00V AT 25mA
VREF+
COMP VREF VSS
5pF
7, 8
D0 - D7
+5V
UP TO 5 OUTPUT LINES
FOR R = 75Ω, 3 LINES
FOR R = 50Ω
LE
1-7, 9
8 DATA
BITS
0.1µF
CER.
0.1µF
CER.
13
14
392Ω
1%
3
R
9
VOUT1
11
+
6
CA3450
R
VOUT = ± 1.5VPEAK
11
VEE 10
+
4.7µF
TAN
4, 5, 12, 13
10kΩ
1kΩ
R
392Ω
1%
0.1µF CER.
VOUTN
R
+
NOTES:
1. Both VREF+ pin and 392Ω resistor should be bypassed within
1/ inch.
4
ADJUST
OFFSET
-6V
4.7µF
TAN
2. Keep nodal capacitance at CA3450 pin 3 as low as possible.
3. VOUT Range = ±3V at CA3450.
FIGURE 6. HI3338 AND CA3450 FOR DRIVING MULTIPLE COAXIAL LINES
Applications
OPERATING
The output of the HI3338 can be resistively divided to match
a doubly terminated 50Ω or 75Ω line, although peak-to-peak
swings of less than 1V may result. The output magnitude will
also vary with the converter's output impedance. Figure 5
shows such an application. Note that because of the HCT
input structure, the HI3338 could be operated up to +7.5V
VDD and VREF+ supplies and still accept 0V to 5V CMOS
input voltages.
OPERATING VOLTAGE
If larger voltage swings or better accuracy is desired, a high
speed output buffer, such as the HA-5033, HA-2542, or
CA3450, can be employed. Figure 6 shows a typical
application, with the output capable of driving ±2V into
multiple 50Ω terminated lines.
Operating and Handling Considerations
HANDLING
All inputs and outputs of CMOS devices have a network for
electrostatic protection during handling. Recommended
handling practices for CMOS devices are described in
AN6525. “Guide to Better Handling and Operation of CMOS
Integrated Circuits.”
8
During operation near the maximum supply voltage limit,
care should be taken to avoid or suppress power supply
turn-on and turn-off transients, power supply ripple, or
ground noise; any of these conditions must not cause the
absolute maximum ratings to be exceeded.
INPUT SIGNALS
To prevent damage to the input protection circuit, input
signals should never be greater than VDD nor less than VSS .
Input currents must not exceed 20mA even when the power
supply is off.
UNUSED INPUTS
A connection must be provided at every input terminal. All
unused input terminals must be connected to either VCC or
GND, whichever is appropriate.
HI3338
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
N
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010) M
H
B M
INCHES
E
-B1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.3977
0.4133
10.10
10.50
3
E
0.2914
0.2992
7.40
7.60
4
e
µα
B S
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
16
0o
16
8o
0o
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
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