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1-88
HI5721
®
10-Bit, 125MSPS, High Speed D/A
Converter
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 125MSPS
Part Number Information
TEMP.
RANGE (oC)
FN3949.8
Features
The HI5721 is a 10-bit, 125MSPS, high speed D/A
converter. The converter incorporates a 10-bit, input data
register with quadrature data logic capability and current
outputs. The HI5721 features low glitch energy and excellent
frequency domain specifications.
PART
NUMBER
March 2003
• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .700mW
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . 1.5 LSB
• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . .1.5pV•s
• TTL/CMOS Compatible Inputs
• Improved Hold Time. . . . . . . . . . . . . . . . . . . . . . . . . 0.5ns
PKG.
NO.
PACKAGE
HI5721BIP
-40 to 85
28 Ld PDIP
E28.6
HI5721BIB
-40 to 85
28 Ld SOIC (W)
M28.3
• Excellent Spurious Free Dynamic Range
• Improved Second Source for the AD9721
Applications
HI5721-EVP
25
Evaluation Board (PDIP)
• Wireless Communications
HI5721-EVS
25
Evaluation Board (SOIC)
• Direct Digital Frequency Synthesis
• Signal Reconstruction
• HDTV
• Test Equipment
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
Pinout
HI5721
(PDIP, SOIC)
TOP VIEW
D9 (MSB) 1
D8 2
27 DVEE
D7 3
26 CTRL AMP IN
D6 4
25 REF OUT
D5 5
24 CTRL AMP OUT
D4 6
23 REF IN
D3 7
22 AVEE
D2 8
21 IOUT
D1 9
20 IOUT
D0 (LSB) 10
19 ARTN
CLOCK 11
18 AGND
NC 12
17 RSET
INVERT 13
16 DVEE
VCC 14
1
28 DGND
15 DGND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI5721
Typical Applications Circuit
+5V
HI5721
0.01µF
VCC (14)
D9
D9 (MSB) (1)
D8
D8 (2)
D7
D7 (3)
D6
D6 (4)
(23) REF IN
0.1µF
(24) CTRL AMP OUT
-5.2V (AVEE)
(26) CTRL AMP IN
D5
D5 (5)
D4
D4 (6)
(25) REF OUT
D3
D3 (7)
(20) IOUT
D2
D2 (8)
D1
D1 (9)
D0
D0 (LSB) (10)
D/A OUT
64Ω
64Ω
(21) IOUT
(17) RSET
CLK (11)
1960Ω
INVERT (13)
50Ω
(19) ARTN
DGND (15, 28)
(18) AGND
DVEE (16, 27)
(22) AVEE
0.01µF
0.01µF
0.1µF
0.1µF
- 5.2V (AVEE)
- 5.2V (DVEE)
Functional Block Diagram
QUADRATURE
LOGIC
(LSB) D0
D1
D2
6 LSBs
CURRENT
CELLS
D3
R2R
NETWORK
DATA
BUFFER/
LEVEL
SHIFTER
D4
D5
SLAVE
REGISTER
ARTN
D6
D7
UPPER
4-BIT
DECODER
D8
15
15
227Ω
227Ω
15
SWITCHED
CURRENT
CELLS
IOUT
(MSB) D9
IOUT
INVERT
REF IN
CLK
VOLTAGE
REFERENCE
+
-
AVEE
AGND
DVEE
2
DGND
VCC
REF OUT
RSET
CTRL AMP IN
25Ω
CTRL AMP
OUT
HI5721
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage VCC to DGND . . . . . . . . . . . . . . . . . . . +5.5V
Negative Digital Supply Voltage DVEE to DGND . . . . . . . . . . -5.5V
Negative Analog Supply Voltage AVEE to AGND, ARTN . . . . -5.5V
Digital Input Voltages (D9-D0, CLK, INVERT) . . . . . . . VCC to -0.5 V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . . .500µA
Control Amplifier Input Voltage Range. . . . . . . . . . . . AGND to -4.0V
Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . ±2.5mA
Reference Input Voltage Range. . . . . . . . . . . . . . . . . -3.7 V to AVEE
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Thermal Resistance (Typical, Note 1)
θJA(oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Power Dissipation
55
70
HI5721BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .750mW
Maximum Junction Temperature
HI5721BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVEE , DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, CTRL AMP IN = REF OUT,
TA = 25oC for All Typical Values
HI5721BI
TA = -40oC TO 85oC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
10
-
-
Bits
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
(Note 4) (“Best Fit” Straight Line)
-
±0.5
±1.5
LSB
Differential Linearity Error, DNL
(Note 4)
-
±0.5
±1.0
LSB
Offset Error, IOS
(Note 4)
-
16
75
µA
Full Scale Gain Error, FSE
(Notes 2, 4)
-
2
10
%
Offset Drift Coefficient
(Note 3)
-
0.1
-
µA/oC
-
-20.48
-
mA
(Note 3)
-1.5
-
+3.0
V
Throughput Rate
(Note 3)
125.0
-
-
MSPS
Output Voltage Full Scale Step Settling Time, tSETT FS
To ±0.5 LSB Error Band RL = 50Ω (Note 3)
-
4.5
-
ns
Output Voltage Small Step Settling Time, tSETT SM
100mV Step to ±0.5 LSB Error Band, RL = 50Ω
(Note 3)
-
3.5
-
ns
Singlet Glitch Area, GE (Peak Glitch)
RL = 50Ω (Note 3)
-
3.5
-
pV•s
-
1.5
-
pV•s
Full Scale Output Current, IFS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Doublet Glitch Area, (Net Glitch)
Output Slew Rate
RL = 50Ω , DAC Operating in Latched Mode
(Note 3)
-
1,000
-
V/µs
Output Rise Time
RL = 50Ω , DAC Operating in Latched Mode
(Note 3)
-
675
-
ps
Output Fall Time
RL = 50Ω , DAC Operating in Latched Mode
(Note 3)
-
470
-
ps
3
HI5721
Electrical Specifications
AVEE , DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, CTRL AMP IN = REF OUT,
TA = 25oC for All Typical Values (Continued)
HI5721BI
TA = -40oC TO 85oC
PARAMETER
Spurious Free Dynamic Range, SFDR to Nyquist
Spurious Free Dynamic Range, SFDR Within a
Window
Signal to Noise Ratio (SNR) to Nyquist
(Ignoring the First 5 Harmonics)
Signal to Noise Ratio + Distortion (SINAD) to Nyquist
Total Harmonic Distortion (THD) to Nyquist
Intermodulation Distortion (IMD) to Nyquist
4
MIN
TYP
MAX
UNITS
fCLK = 125 MSPS, fOUT = 2.02MHz, 62.5MHz
Span (Notes 3, 5)
-
-59
-
dBc
fCLK = 125 MSPS, fOUT = 25MHz, 62.5MHz Span
(Notes 3, 5)
-
-53
-
dBc
fCLK = 100 MSPS, fOUT = 2.02MHz, 50MHz Span
(Notes 3, 5)
-
-59
-
dBc
fCLK = 100 MSPS, fOUT = 25MHz, 50MHz Span
(Notes 3, 5)
-
-51
-
dBc
fCLK = 125 MSPS, fOUT = 2.02MHz, 2MHz Span
(Notes 3, 5)
-
-75
-
dBc
fCLK = 125 MSPS, fOUT = 25MHz, 2MHz Span
(Notes 3, 5)
-
-70
-
dBc
fCLK = 100 MSPS, fOUT = 2.02MHz, 2MHz Span
(Notes 3, 5)
-
-75
-
dBc
fCLK = 100 MSPS, fOUT = 25MHz, 2MHz Span
(Notes 3, 5)
-
-72
-
dBc
fCLK = 125 MSPS, fOUT = 2.02MHz,
(Notes 3, 5)
-
54
-
dB
fCLK = 125 MSPS, fOUT = 25MHz
(Notes 3, 5)
-
51.5
-
dB
fCLK = 100 MSPS, fOUT = 2.02MHz,
(Notes 3, 5)
-
54.5
-
dB
fCLK = 100 MSPS, fOUT = 25MHz
(Notes 3, 5)
-
50.3
-
dB
fCLK = 125 MSPS, fOUT = 2.02MHz,
(Notes 3, 5)
-
52.4
-
dB
fCLK = 125 MSPS, fOUT = 25MHz
(Notes 3, 5)
-
49.2
-
dB
fCLK = 100 MSPS, fOUT = 2.02MHz,
(Notes 3, 5)
-
52.7
-
dB
fCLK = 100 MSPS, fOUT = 25MHz
(Notes 3, 5)
-
47.6
-
dB
fCLK = 125 MSPS, fOUT = 2.02MHz,
(Notes 3, 5)
-
-57.8
-
dBc
fCLK = 125 MSPS, fOUT = 25MHz
(Notes 3, 5)
-
-53.3
-
dBc
fCLK = 100 MSPS, fOUT = 2.02MHz,
(Notes 3, 5)
-
-57.9
-
dBc
fCLK = 100 MSPS, fOUT = 25MHz
(Notes 3, 5)
-
-51
-
dBc
fCLK = 125 MSPS, fOUT1 = 800kHz,
fOUT2 = 900kHz (Notes 3, 5)
-
57.3
-
dB
fCLK = 100 MSPS, fOUT1 = 800kHz,
fOUT2 = 900kHz (Notes 3, 5)
-
57.2
-
dB
TEST CONDITIONS
HI5721
Electrical Specifications
AVEE , DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, CTRL AMP IN = REF OUT,
TA = 25oC for All Typical Values (Continued)
HI5721BI
TA = -40oC TO 85oC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE/CONTROL AMPLIFIER
Internal Reference Voltage, REF OUT
(Note 4)
-1.15
-1.25
-1.35
V
Internal Reference Voltage Drift
(Note 3)
-
100
-
µV/oC
Internal Reference Output Current Sink/Source
Capability
(Note 3)
-50
-
+500
µA
Amplifier Input Impedance
(Note 3)
-
10
-
MΩ
Amplifier Large Signal Bandwidth
4.0VP-P Sine Wave Input, to Slew Rate Limited
(Note 3)
-
1
-
MHz
Amplifier Small Signal Bandwidth
1.0VP-P Sine Wave Input, to -3dB Loss (Note 3)
-
10
-
MHz
Reference Input Impedance
(Note 3)
-
4.6
-
kΩ
Reference Input Multiplying Bandwidth
RL = 50Ω , 100mV Sine Wave, to -3dB Loss at
IOUT (Note 3)
-
75
-
MHz
DIGITAL INPUTS (D9-D0, CLK, INVERT)
Input Logic High Voltage, VIH
(Note 4)
2.0
-
-
V
Input Logic Low Voltage, VIL
(Note 4)
-
-
0.8
V
Input Logic Current, IIH
(Note 4)
-
-
400
µA
Input Logic Current, IIL
(Note 4)
-
-
700
µA
Digital Input Capacitance, CIN
(Note 3)
-
3.0
-
pF
TIMING CHARACTERISTICS
Data Setup Time, tSU
See Figure 3 (Note 3)
2.0
-
-
ns
Data Hold Time, tHLD
See Figure 3 (Note 3)
0.5
-
-
ns
Propagation Delay Time, tPD
See Figure 3 (Note 3)
-
4.5
-
ns
CLK Pulse Width, tPW1 , tPW2
See Figure 3 (Note 3)
1.0
0.85
-
ns
POWER SUPPLY CHARACTERISITICS
IDVEE
(Note 4)
-
100
110
mA
IAVEE
(Note 4)
-
-
15
mA
VCC
(Note 4)
-
14
25
mA
Power Dissipation
(Note 4)
-
700
775
mW
Power Supply Rejection Ratio
VCC ±5%, VEE ±5%
-
50
-
µA/V
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 640µA). Ideally the
ratio should be 32.
3. Parameter guaranteed by design or characterization and not production tested.
4. All devices are 100% tested at 25oC. 100% productions tested at temperature extremes for military temperature devices, sample tested for
industrial temperature devices.
5. Spectral measurements made without external filtering.
5
HI5721
Timing Diagrams
50%
CLK
GLITCH AREA = 1/2 (H x W)
V
D9-D0
HEIGHT (H)
1/ LSB ERROR BAND
2
IOUT
t(ps)
WIDTH (W)
tSETT
tPD
FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM
tPW1
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
tPW2
50%
CLK
tSU
tSU
tHLD
tSU
tHLD
tHLD
D9-D0
tPD
tSETT
IOUT
tPD
tSETT
tPD
tSETT
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
6
HI5721
Typical Performance Curves
+0.5
1.0
0.4
0.2
LSB
LSB
0.5
0
0
-0.2
-0.5
-0.4
-1.0
-0.5
0
200
400
600
800
1023
0
200
400
FIGURE 4. INTEGRAL NON-LINERARITY “BEST FIT”
STRAIGHT LINE
10dB/
-10
RL -10.0dBm
10dB/
-10
-30
-40
-40
-50
-50
-60
SFDR = -55.8dBc
HI-5721
fCLK = 125 MSPS
fOUT = 2 MHz
-20
dB
dB
-30
1023
†ATTEN 20dB
HI-5721
fCLK = 125 MSPS
fOUT = 25 MHZ
-20
800
FIGURE 5. DIFFERENTIAL NON-LINEARITY
∆MKR -54.16dB
25.2MHz
†ATTEN 20dB
RL -10.0dBm
600
DATA CODE
DATA CODE
-60
-70
-70
-80
-80
-90
-90
-100
-100
-110
-110
START 0Hz
†RBW 3.0kHz
†VBW 1kHz
STOP 62.50MHz
SWP 53.0s
START 0Hz
†RBW 3.0kHz
FIGURE 6. SPURIOUS FREE DYNAMIC RANGE TO NYQUIST
25MHz FUNDAMENTAL
STOP 62.50MHz
SWP 53.0s
†VBW 1.0kHz
FIGURE 7. SPURIOUS FREE DYNAMIC RANGE TO NYQUIST
2MHz FUNDAMENTAL
60
0.0
59
f1 = 800kHz
f2 = 900kHz
-20
58
57
800kHz
900kHz
fCLK = 125 MSPS
56
55
dBc
dB
-40
-60
54
53
fCLK = 100 MSPS
52
-80
51
50
-100
49
48
-110
0
2
4
FREQUENCY (MHz)
FIGURE 8. INTERMODULATION DISTORTION
7
6
2
4
6
8
10
12 14 16
fOUT (MHz)
18
20
22
24
26
FIGURE 9. SPURIOUS FREE DYNAMIC RANGE (TO NYQUIST)
vs OUTPUT FREQUENCY
HI5721
Typical Performance Curves
(Continued)
78
58
77
57
76
56
fCLK = 125 MSPS
75
55
73
54
72
53
dB
dBc
74
71
70
fCLK = 100 MSPS
fCLK = 100 MSPS
50
68
49
67
66
48
65
47
2
4
6
8
10
12 14 16
fOUT (MHz)
18
20
22
24
26
FIGURE 10. SPURIOUS FREE DYNAMIC RANGE
(±1MHz WINDOW) vs FREQUENCY
2
4
6
8
10
12 14 16
fOUT (MHz)
18
20
22
24
26
FIGURE 11. SIGNAL TO NOISE RATIO vs OUTPUT FREQUENCY
58
56
55
57
54
56
53
55
52
fCLK = 125 MSPS
54
dBc
51
dB
52
51
69
fCLK = 125 MSPS
50
53
fCLK = 100 MSPS
52
49
fCLK = 100 MSPS
48
51
47
50
46
49
45
48
44
2
4
6
8
10
12 14 16
fOUT (MHz)
18
20
22
24
2
26
FIGURE 12. SIGNAL TO NOISE + DISTORTION vs OUTPUT
FREQUENCY
-2.5
56
-2.6
54
-2.7
52
-2.8
50
-2.9
48
-3.0
46
-3.1
44
-3.2
40
-3.4
38
-3.5
36
-3.6
34
-3.7
32
-20
0
20
40
60
80
TEMPERATURE (oC)
FIGURE 14. GAIN ERROR vs TEMPERATURE
8
100
6
8
10
12 14 16
fOUT (MHz)
18
20
22
24
26
42
-3.3
-3.8
-40
4
FIGURE 13. TOTAL HARMONIC DISTORTION vs OUTPUT
FREQUENCY
µA
ERROR (%)
fCLK = 125 MSPS
30
-50 -40 -30 -20 -10
0
10
20
30
40
50
60
70
TEMPERATURE (oC)
FIGURE 15. OFFSET ERROR vs TEMPERATURE
80
90
HI5721
-1.20
-1.21
-1.22
-1.23
-1.24
-1.25
-1.26
-1.27
-1.28
-1.29
-1.30
-1.31
-1.32
-1.33
-1.34
-1.35
-40
(Continued)
0.80
0.75
0.70
-50µA LOAD
100µA LOAD
(W)
(V)
Typical Performance Curves
NO LOAD
0.65
0.60
0.55
-20
0
20
40
60
80
0.50
-50 -40 -30 -20 -10
100
TEMPERATURE (oC)
0 10 20 30 40 50 60 70 80 90
TEMPERATURE (oC)
NOTE: Clock Frequency does not alter power dissipation.
FIGURE 16. REFERENCE VOLTAGE vs TEMPERATURE
FIGURE 17. POWER DISSIPATION vs TEMPERATURE
Pin Descriptions
PIN NO.
PIN NAME
PIN DESCRIPTION
1-10
D0 (LSB)
through D9
(MSB)
11
CLK
Data Clock pin 100kHz to 125 MSPS.
12
NC
No Connect.
13
INVERT
14
VCC
15, 28
DGND
Digital Ground.
16, 27
DVEE
-5.2V Logic Supply.
17
RSET
External resistor to set the full scale output current. IFS = 32 x (CTRL AMP IN/RSET). Typically 1960Ω .
18
AGND
Analog Ground supply current return pin.
19
ARTN
Analog Signal Return for the R/2R ladder.
20
IOUT
Current Output pin.
21
IOUT
Complementary Current Output pin.
22
AVEE
-5.2V Analog Supply.
23
REF IN
Reference Input pin. Typically connected to CTRL AMP OUT and a 0.1µF capacitor should be connected to
AVEE to bypass the reference voltage. Provides a reference for the current switching network.
24
CTRL AMP
OUT
Control Amplifier Output. Used to convert the internal reference or an external signal to the precision reference
current.
25
REF OUT
26
CTRL AMP IN
Digital Data Bit 0, the Least Significant Bit through Digital Data Bit 9, the Most Significant Bit.
Data Invert control for bits D0 (LSB) through D8. D9 (MSB) is not affected.
Digital Logic Supply +5V.
Internal Reference Output. Output of the internal -1.25V (typical) bandgap voltage reference.
9
Control Amplifier Input. High impedance, inverting input of the reference control/buffer amplifier.
HI5721
Detailed Description
The HI5721 is a 10-bit, current out D/A converter. The DAC
can convert at 125 MSPS and runs on +5V and -5.2V
supplies. The architecture is an R/2R and segmented
switching current cell arrangement to reduce glitch and
maintain 10-bit linearity without laser trimming. The HI5721
achieves its low power and high speed performance from an
advanced BiCMOS process. The HI5721 consumes 700mW
(typical) and has an improved hold time of only 0.5ns
(typical). The HI5721 is an excellent converter to be used for
communications applications and high performance video
systems.
To terminate the clock line a shunt terminator to ground is the
most effective type at a 125 MSPS clock rate. A typical value
for termination can be determined by the equation:
RT = ZO ,
for the termination resistor. For a controlled impedance
board with a ZO of 50Ω , the RT = 50Ω . Shunt termination is
best used at the receiving end of the transmission line or as
close to the HI5721 CLK pin as possible.
HI5721
DAC
ZO = 50Ω
Digital Inputs
CLK
RT = 50Ω
The HI5721 is a TTL/CMOS compatible D/A. The inputs can
be inverted using the INVERT pin. When INVERT is LOW
(‘0’) the input quadrature logic simply passes the data
through unchanged.
When INVERT is HIGH (‘1’) bits D0 (LSB) through D8 are
inverted. D9 is not inverted and can be considered a sign bit
when enabling this quadrature compatible mode. The
INVERT function can simplify the requirements for large sine
wave lookup tables in a Numerically Controlled Oscillator.
The NCO used in a DDS application would only have to
store or generate 90 degrees of information and then use the
INVERT control to control the sign of the output waveform.
Data Buffer/Level Shifters
Data inputs D0 (LSB) through D9 (MSB) are internally
translated from TTL to ECL. The internal latch and switching
current source controls are implemented in ECL technology to
maintain high switching speeds and low noise characteristics.
Decoder/Driver
The architecture employs a split R/2R and Segmented
Current source arrangement. Bits D0 (LSB) through D5
directly drive a typical R/2R network to create the binary
weighted current sources. Bits D6 through D9 (MSB) pass
through a “thermometer” encoder that converters the
incoming data into 15 individual segmented current source
enables. The split architecture helps to improve glitch while
maintaining 10-bit linearity without laser trimming. The worst
case glitch is more constant across the entire output transfer
function.
Clocks and Termination
The internal 10-bit register is updated on the rising edge of the
clock. Since the HI5721 clock rate can run to 125 MSPS, to
minimize reflections and clock noise into the part proper
termination should be used. In PCB layout clock runs should be
kept short and have a minimum of loads. To guarantee
consistent results from board to board, controlled impedance
PCBs should be used with a characteristic line impedance ZO
of 50Ω .
10
FIGURE 18. AC TERMINATION OF THE HI5721 CLOCK LINE
Rise and Fall times and propagation delay of the line will be
affected by the Shunt Terminator. The terminator can be
connected to DGND.
Noise Reduction
To reduce power supply noise, separate analog and digital
power supplies should be used with 0.1µF and 0.01µF
ceramic capacitors placed as close to the body of the
HI5721 as possible on the analog (AVEE) and digital (DVEE)
supplies. The analog and digital ground returns should be
connected together back at the device to ensure proper
operation on power up. The VCC power pin should be
decoupled with a 0.1µF capacitor.
Reference
The internal reference in the HI5721 is a -1.25V (typical)
bandgap voltage reference with a 100µV/oC temperature
drift (typical). The internal reference should be buffered by
the Control Amplifier to provide adequate drive for the
segmented current cells and the R/2R resistor ladder.
Reference Out (REF OUT) should be connected to the
Control Amplifier Input (CTRL AMP IN). The Control
Amplifier Output (CTRL AMP OUT) should be used to drive
the Reference Input (REF IN) and a 0.1µF capacitor to
analog V- (AVEE). This improves settling time by decoupling
switching noise from the analog output of the HI5721.
The Full Scale Output Current is controlled by the CTRL
AMP IN pin and the set resistor (RSET). The ratio is:
IOUT (Full Scale) = (VCTRL AMP IN/RSET) x 32.
Multiplying Capability
The HI5721 can operate in two different multiplying
configurations. First, using the CTRL AMP IN input pin, a
-0.6V to -1.2V signal can be applied with a bandwidth up to
1MHz. To increase the multiplying bandwidth, the 0.1µF
capacitor connected from REF IN to AVEE can be reduced.
HI5721
HI5721
20
TABLE 1. INPUT CODING vs CURRENT OUTPUT
RSET
INPUT CODE (D9-D0)
RSET
19
-0.6 TO -1.2V
1MHz (MAX)
CTRL AMP IN
RT
18
18Ω
17
CTRL AMP
OUT
REF IN
FIGURE 19. LOW FREQUENCY MULTIPLYING CIRCUIT
If higher multiplying frequencies are desired, the reference
input can be directly driven. The analog signal range is -3.3V
to -4.25V. The multiplying signal must be capacitively
coupled into REF IN onto a DC bias between -3.3V to -4.25V
(-3.8V typically).
HI5721
2nF
50Ω
383Ω
17
REF IN
≅ -3.8V
120Ω
AVEE
FIGURE 20. WIDEBAND MULTIPLYING CIRCUIT
Outputs
The outputs IOUT and IOUT are complementary current
outputs. Current is steered to either IOUT or IOUT in
proportion to the digital input code. The sum of the two
currents is always equal to the full scale current minus one
LSB. The current output can be converted to a voltage by
using a load resistor. Both current outputs should have the
same load resistor (64Ω typically). By using a 64Ω load on
the output, a 50Ω effective output resistance (ROUT) is
achieved due to the 227Ω (±15%) parallel resistance seen
looking back into the output. This is the nominal value of the
R2R ladder of the DAC. The 50Ω output is needed for
matching the output with a 50Ω line. The load resistor should
be chosen so that the effective output resistance (ROUT)
matches the line resistance. The output voltage is:
VOUT = IOUT x ROUT .
IOUT is defined in the reference section. The compliance
range of the output is from -1.5V to 3V, with a 1VP-P voltage
swing allowed within this range. However, if it is desired that
the output be offset above zero volts, it is necessary that pin
19 (ARTN) be connected to the same voltage as the load
resistor, not to exceed 3V.
11
Glitch
IOUT (mA)
IOUT (mA)
11 1111 1111
-20.48
0
10 0000 0000
-10.24
-10.24
00 0000 0000
0
-20.48
The output glitch of the HI5721 is measured by summing the
area under the switching transients after an update of the
DAC. Glitch is caused by the time skew between bits of the
incoming digital data. Typically the switching time of digital
inputs are asymmetrical meaning that the turn off time is
faster than the turn on time (TTL designs). Unequal delay
paths through the device can also cause one current source
to change before another. To minimize this the Intersil
HI5721 employes an internal register, just prior to the current
sources, that is updated on the clock edge. Lastly the worst
case glitch usually happens at the major transition i.e.,
01 1111 1111 to 10 0000 0000. But in the HI5721 the glitch
is moved to the 00 0001 1111 to 11 1110 0000 transition.
This is achieved by the split R/2R segmented current source
architecture. This decreases the amount of current switching
at any one time and makes the glitch practically constant
over the entire output range. By making the glitch a constant
size over the entire output range this effectively integrates
this error out of the end application.
In measuring the output glitch of the HI5721 the output is
terminated into a 64Ω load. The glitch is measured at the
major carrys throughout the DAC’s output range.
The glitch energy is calculated by measuring the area under
the voltage-time curve. Figure 21 shows the area considered
as glitch when changing the DAC output. Units are typically
specified in picoVolt • seconds (pV • s).
HI5721
125MHz
LOW PASS
FILTER
(20) IOUT
SCOPE
64Ω
FIGURE 21. GLITCH TEST CIRCUIT
50Ω
HI5721
R2
20K
-5V
PIN 25
(HI5721)
R1
20K
a (mV)
GLITCH ENERGY = (a x t)/2
U1
2 4 8
6
3 +
1
R3
7 HA2705 1K
+5V
50
t (ns)
BIPOLAR
OUTPUT
R6 (±2.0V)
50
+5V
FIGURE 22. GLITCH ENERGY
FIGURE 24. BIPOLAR OUTPUT CONFIGURATION
Applications
(DDS) applications. Figure 26 shows how to interface an
HI5721 to the HSP45102.
Voltage Conversion of the Output
To convert the output current of the D/A converter to a
voltage, an amplifier should be used as shown in Figure 23
below. The DAC needs a 50Ω termination resistor on the
IOUT pin to ensure proper settling. The HFA1110 has an
internal feedback resistor to compensate for high frequency
operation.
This high level block diagram is that of a basic PSK
modulator. In this example the encoder generates the PSK
waveform by driving the Phase Modulation Inputs (P1, P0) of
the HSP45102. The P1-0 inputs impart a phase shift to the
carrier wave as defined in Table 2.
TABLE 2. PHASE MODULATION INPUT CODING
+5V
2
1
HFA1110
HI5721
DAC
IOUT
240
-5V
U2
2 4 8
6
3 +
1
7 HFA1100
R5
PIN 20
(HI5721)
R4
20
4
50Ω
8
-
+
6
5
50Ω
P1
P0
PHASE SHIFT
(DEGREES)
0
0
0
0
1
90
1
0
270
1
1
180
-5.2V
FIGURE 23. HIGH SPEED CURRENT TO VOLTAGE CONVERSION
Bipolar Applications
To convert the output to a bipolar ±2.0V output swing the
following applications circuit is recommended. The
Reference can only provide 100µA of drive, so it must be
buffered to create the bipolar offset current needed to
generate -2.0V output with all bits ‘off’. The output current
must be converted to a voltage and then gained up and
offset to produce the proper swing. Care must be taken to
compensate for the output voltage swing and error.
Interfacing to the HSP45106 NCO-16
The HSP45106 is a 16-bit output, Numerically-Controlled
Oscillator (NCO). The HSP45106 can be used to generate
various modulation schemes for Direct Digital Synthesis
(DDS) applications. Figure 25 shows how to interface an
HI5721 to the HSP45106.
Interfacing to the HSP45102 NCO-12
The HSP45102 is a 12-bit output Numerically Controlled
Oscillator (NCO). The HSP45102 can be used to generate
various modulation schemes for Direct Digital Synthesis
12
The 10 MSBs of the HSP45102 drive the 10-bit HI5721 DAC
which converts the NCO output into an analog waveform.
The output filter connected to the DAC can be tailored to
remove unwanted spurs for the desired carrier frequency.
The controller is used to load the desired center frequency
and control the HSP45102. The HI5721 coupled with the
HSP45102 make an inexpensive PSK modulator with
Spurious Free operation down to -76dBc.
HI5721
U2
33 MSPS
CLK
BASEBAND
BIT
STREAM
K9
C11
B11
ENCODER
C10
A11
F10
F9
F11
H11
G11
G9
J11
G10
D10
VCC
CONTROLLER
J10
K11
B8
A8
B6
B7
A7
C7
C6
A6
A5
C5
A4
B4
A3
A2
B3
A1
B10
B9
A10
E11
E9
VCC H10
K2
J2
V
CC
CLK
MOD2
MOD1
MOD0
PMSEL DACSTRB#
ENPOREG#
ENOFREG#
ENCFREG#
ENPHAC#
ENTIREG#
INHOFR#
INITPAC#
INITTAC#
TEST
PARSER#
BINFMT#
C15_MSB
C4
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
A2
A1
A0
CS#
WR#
PACI#
FILTER
U1
SIN15
SIN14
SIN13
SIN12
SIN11
SIN10
SIN9
SIN8
SIN7
SIN6
SIN5
SIN4
SIN3
SIN2
SIN1
SIN0
COS15
COS14
COS13
COS12
COS11
COS10
COS9
COS8
COS7
COS6
COS5
COS4
COS3
COS2
COS1
COS0
TICO#
L1
K3
L2
L3
L4
J5
K5
L5
K6
J6
J7
L7
L6
L8
K8
L9
L10
C2
B1
C1
D1
E3
E2
E1
F2
F3
G3
G1
G2
H1
H2
J1
K1
VCC
14
DVDD
IOUT
1
2
3
4
5
6
7
8
9
10
D9 (MSB)
D8
IOUT/
D7
D6
D5
D4
REF IN
D3
D2
C AMP OUT
D1
D0 (LSB)
C AMP IN
11
CLK
REF OUT
13
INVERT
R4
50
RSET
28
DVSS
15
DVSS
-5.2V_D
TO RF
UP-CONVERT
STAGE
R1
20
64
R1
21
64
23
24
+
C2
1.0µF
C1
0.01µF
-5.2V_A
-5.2V_A
26
25
R1
17
1960
ARET
19
AVSS 18
27 DV
EE
16
DVEE
AVEE
22
-5.2V_A
HI5721
L1
-5.2V_D
-5.2V_A
10µH
L2
10µH
B2
OES#
OEC#
HSP45106
FIGURE 25. PSK MODULATOR USING THE HI5721 AND THE HSP45106 12-BIT NCO
Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Differential Linearity Error, DNL, is the measure of the
step size output deviation from code to code. Ideally the step
size should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
Feedthru is the measure of the undesirable switching noise
coupled to the output.
Output Voltage Full Scale Settling Time, is the time
required from the 50% point on the clock input for a full scale
step to settle within an 1/2 LSB error band.
13
Output Voltage Small Scale Settling Time, is the time
required from the 50% point on the clock input for a 100mV
step to settle within an 1/2 LSB error band. This is used by
applications reconstructing highly correlated signals such as
sine waves with more than 5 points per cycle.
Glitch Area, GE, is the switching transient appearing on the
output during a code transition. It is measured as the area
under the curve and expressed as a Volt-Time specification.
Differential Gain, ∆AV , is the gain error from an ideal sine
wave with a normalized amplitude.
Differential Phase, ∆Φ , is the phase error from and ideal
sine wave.
HI5721
FILTER
U2
VCC
U1
BASEBAND
BIT
STREAM
40 MSPS
I CLK
ENCODER
Q
16
19
20
18
17
12
9
CONTROL
BUS
CLK
P1
P0
LOAD#
TXFR#
ENPHAC#
SEL_L/M#
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
6
5
4
3
2
1
28
27
26
25
24
23
13
10
11
IOUT
D9 (MSB)
D8
IOUT/
D7
D6
D5
D4
REF IN
D3
D2
C AMP OUT
D1
D0 (LSB)
C AMP IN
11
CLK
REF OUT
13
INVERT
SCLK
R4
50
SD
28
15
SFTEN#
MSB/LSB#
HSP45102
DVDD
1
2
3
4
5
6
7
8
9
10
CONTROLLER
14
14
-5.2V_D
RSET
20
R1
64
21
R1
64
23
24
+
C2
1.0µF
C1
0.01µF
-5.2V_A
-5.2V_A
26
25
17
DVSS
DVSS
TO RF
UP-CONVERT
STAGE
R1
1960
ARET
19
AVSS 18
27 DV
EE
16
DVEE
AVEE
22
-5.2V_A
HI5721
L1
-5.2V_D
10µH
L2
-5.2V_A
10µH
FIGURE 26. PSK MODULATOR USING THE HI5721 AND THE HSP45102 12-BIT NCO
Signal to Noise Ratio, SNR, is the ratio of a fundamental to
the noise floor of the analog output. The first 5 harmonics
are ignored, and an output filter of 1/2 the clock frequency is
used to eliminate alias products.
Total Harmonic Distortion, THD, is the ratio of the DAC
output fundamental to the RMS sum of the harmonics. The
first 5 harmonics are included, and an output filter of 1/2 the
clock frequency is used to eliminate alias products.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from a fundamental to the largest harmonically or
non-harmonically related spur. A sine wave is loaded into
the D/A and the output filtered at 1/2 the clock frequency to
eliminate noise from clocking alias terms.
Intermodulation Distortion, IMD is the measure of the sum
and difference products produced when a two tone input is
driven into the D/A. The distortion products created will arise
at sum and difference frequencies of the two tones. IMD is
20 log (RMS of sum and difference distortion products)
IMD = -----------------------------------------------------------------------------------------------------------------------------------------------( RMS amplitude of the fundamental )
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
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