DATASHEET

ISL22316WM
Single Digitally Controlled Potentiometer (XDCP™)
Data Sheet
November 11, 2011
FN6622.1
Low Noise, Low Power I2C® Bus, 128 Taps
Features
The ISL22316WMUEP integrates a single digitally controlled
potentiometer (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.
• Specifications per DSCC VID V62/08603-01XB
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. The potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up, the device recalls the contents of the
DCP’s IVR to the WR.
The DCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments and
signal processing.
Device Information
The specifications for an Enhanced Product (EP) device are
defined in a Vendor Item Drawing (VID), which is controlled
by the Defense Logistics Agency (DLA). “Hot-links” to the
applicable VID and other supporting application information
are provided on our website.
• Full Mil-Temp Electrical Performance from -55°C to +125°C
• Controlled Baseline with One Wafer Fabrication Site and
One Assembly/Test Site
• Full Homogeneous Lot Processing in Wafer Fab
• No Combination of Wafer Fabrication Lots in Assembly
• Full Traceability Through Assembly and Test by
Date/Trace Code Assignment
• Enhanced Process Change Notification
• Enhanced Obsolescence Management
• Eliminates Need for Up-Screening a COTS Component
• 128 Resistor Taps
• I2C Serial Interface
- Two Address Pins, Up To Four Devices/Bus
• Non-volatile Storage of Wiper Position
• Wiper Resistance: 70Ω Typical @ 3.3V
• Shutdown Mode
• Shutdown Current 5µA Max
• Power Supply: 2.7V to 5.5V
• 10kΩ Total Resistance
Pinout
SCL
1
10
VCC
SDA
2
9
RH
A1
3
8
RW
• High Reliability
- Endurance: 1,000,000 Data Changes Per Bit Per
Register
- Register Data Retention:
- 10 years @ T ≤ +125°C
- 15 years @ T ≤ +90°C
- 50 years @ T ≤ +55°C
A0
4
7
RL
• 10 Ld MSOP
SHDN
5
6
GND
ISL22316WMUEP
(10 LD MSOP)
TOP VIEW
Ordering Information
VENDOR PART NUMBER
(Notes 1, 2)
ISL22316WMUEP
VENDOR ITEM DRAWING PART MARKING
V62/08603-01XB
2316M
RESISTANCE OPTION
(kΩ)
10
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
-55 to +125 10 Ld MSOP M10.118
NOTES:
1. Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. Devices must be procured to the VENDOR PART NUMBER.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007, 2011. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL22316WM
Block Diagram
VCC
SCL
SDA
I2C
INTERFACE
A0
A1
POWER-UP
INTERFACE,
CONTROL
AND
STATUS
LOGIC
RH
WR
RW
RL
NON-VOLATILE
REGISTERS
SHDN
GND
Pin Descriptions
MSOP PIN
SYMBOL
DESCRIPTION
1
SCL
Open drain I2C interface clock input
2
SDA
Open drain Serial data I/O for the I2C interface
3
A1
Device address input for the I2C interface
4
A0
Device address input for the I2C interface
5
SHDN
6
GND
7
RL
“Low” terminal of DCP
8
RW
“Wiper” terminal of DCP
9
RH
“High” terminal of DCP
10
VCC
2
Shutdown active low input
Device ground pin
Power supply pin
FN6622.1
November 11, 2011
ISL22316WM
Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
E
INCHES
SYMBOL
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X θ
0.25
(0.010)
R1
R
GAUGE
PLANE
A
SEATING
PLANE -C-
A2
A1
b
-He
D
0.10 (0.004)
4X θ
L
SEATING
PLANE
C
-A0.20 (0.008)
C
C
a
SIDE VIEW
CL
E1
0.20 (0.008)
C D
-B-
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.007
0.011
0.18
0.27
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
e
L1
MIN
0.020 BSC
0.50 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
L1
0.037 REF
0.95 REF
-
N
10
10
7
R
0.003
-
0.07
-
-
R1
0.003
-
0.07
-
-
θ
5o
15o
5o
15o
-
α
0o
6o
0o
6o
-
END VIEW
Rev. 0 12/02
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B -
to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
3
FN6622.1
November 11, 2011
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