158KB

KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
INTRODUCTION
100 QFP
The KS0108B is a LCD driver LSl with 64 channel output
for dot matrix liquid crystal graphic display system. This
device consists of the display RAM, 64 bit data latch 64 bit
drivers and decoder logics. It has the internal display RAM
for storing the display data transferred from a 8 bit micro
controller and generates the dot matrix Iiquid crystal driving signals corresponding to stored data.The KS0108B
composed of the liquid crystal display system in combination with the KS0107B (64 common driver)
FEATURES
• Dot matrix LCD segment driver with 64 channel output
• Input and Output signal
- Input: 8 bit parallel display data
Control signal from MPU
Splitted bias voltage (V1R, V1L, V2R, V2L,
V3R. V3L, V4R, V4L)
- Output: 64 channel waveform for LCD driving.
• Display data is stored in display data RAM from MPU.
• Interface RAM
- Capacity: 512 bytes (4096 bits)
- RAM bit data: RAM bit data = 1:ON
RAM bit data- = 0:OFF
• Applicable LCD duty: 1/32~1/64
• LCD driving voltage: 8V~17V(VDD-VEE)
• Power supply voltage: + 5V±10%
Driver
COMMON
KS0107B
SEGMENT
Other KS0108B
• High voltage CMOS process.
• 100QFP and bare chip available.
Controller
MPU
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
BLOCK DIAGRAM
DB<0:7>
CLK1 CLK2
CS1B
CS2B
INPUT REGISTER
CS3
OUTPUT REGISTER
I/O
BUFFER
R/W
RS
E
8
RSTB
8
DISPLAY
ON/OFF
INSTRUCTION
DECODER
BUSY
1
6
3
ADC
Y-COUNTER
6
X-DECODER
Y-DECODER
6
64
64
DISPLAY DATA RAM
512¡¿8=4096 bits
8
PAGE SELECTOR
6
Z DECODER
FRM
DISPLAY START LINE REGISTER
CL
8
64
DATA LATCH
64
V0L
V0R
V2L
V2R
LCD DRIVER
V3L
V3R
V5L
V5R
M
S64
S63
S2
S1
DB2 81
DB3 82
DB4 83
DB5 84
DB6 85
DB7 86
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
S22
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
S43
87
S21
S44
NC
S20
S45
88
S19
S46
89
S18
S47
NC
S17
S48
NC
S16
S49
30
KS0108B
S15
S50
CS3 90
S14
S51
CS2B
S13
S52
91
14
S12
S53
CS1B
13
S11
S54
92
12
S10
S55
93
11
S9
S56
R/W 94
10
S8
S57
RSTB
9
S7
S58
95
8
S6
S59
RS
7
S5
S60
96
6
S4
S61
CL
5
S3
S62
CLK2 97
4
S2
S63
CLK1 98
3
S1
S64
99
2
V EE1
V EE2
E
FRM 100
1
V0L
V0R
V5L
V5R
V2L
V2R
V3L
V3R
V SS
V DD
DB0
M
DB1
ADC
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
KS0108B
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Fig.2. 100QFP Top
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
View
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
PIN DESCIPTION
PIN (NO)
3
78
73, 8
SYMBOL
VDD
VSS
VEE1.2
INPUT/OUTPUT
DESCRIPTION
Power
For internal logic circuit (+5V±10%)
GND (0V)
For LCD driver circuit
VSS=0V, VDD=5V¡¾10% VDD-VEE=8V~17V
VEE1 and VEE2 is connected by the same voltage.
Power
Bias supply voltage terminals to drive the LCD.
74, 7
76, 5
77, 4
75, 6
V0L, V0R
V2L, V2R
V3L, V3R
V5L, V5R
92
91
90
2
1
CS1B
CS2B
CS3
M
ADC
Input
100
FRM
Input
99
E
Input
98
97
CLK1
CLK2
Input
96
CL
Input
95
RS
Input
94
R/W
Input
79~86
DB0~DB7
Input/Output
Select Level
V0L(R), V5L(R)
Input
Input
Non-Select Level
V2L(R), V3L(R)
Chip selection
In order to interface data for input or output
The terminals have to be CS1B=L, CS2B=L, and CS3=H.
Alternating signal input for LCD driving.
Address control signal of Y address counter.
ADC=H→DB<0:7>=0→Y0→S1
DB<0:7>=63→Y63→S64
ADC=L→DB<0:7>=0→Y63→S64
DB<0:7>=63→Y0→S1
Synchronous control signal.
Presets the 6-bit Z counter and syncronizes the common signal with the
frame signal when the frame signal becomes high.
Enable signal.
write mode (R/W=L) → data of DB<0:7> is latched at
the falling edge of E.
read mode (R/W=H) → DB<0:7> appears the reading
data while E is at high level.
2 phase clock signal for internal operation.
Used to execute operations for input/output of display
RAM data and others.
Display synchronous signal.
Display data is latched at rising time of the CL signal and increments the
Z-address counter at the CL falling time.
Data or Instruction.
RS=H→DB<0:7> : Display RAM Data
RS=L→DB<0:7> : Instruction Data
Read or Write.
R/W=H → Data appears at DB<0:7> and can be read
by the CPU while E=H, CS1B=L, CS2B=L
and CS3=H.
R/W=L ¡æDisplay data DB<0:7> can be written at falling of E
when CS1B=L, CS2B=L and CS3=H.
Data bus.
There state I/O common terminal.
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
PIN DESCRIPTION(continued)
PIN (NO)
72~9
NAME
S1~S64
INPUT/OUTPUT
DESCRIPTION
Output
LCD Segment driver output.
Display RAM data 1:ON
Display RAM data 0:OFF
(Relation of display RAM data & M)
M
L
H
93
RSTB
87~89
NC
Input
DATA
L
H
L
H
Output Level
V2
V0
V3
V5
Reset signal.
When RSTB=L,
(1) ON/OFF register becomes set by 0. (display off)
(2) Display start line register becomes set by 0
(Z-address 0 set, display from line 0)
After releasing reset, this condition can be changed only by instruction.
No connection.(open)
MAXIMUM ABSOLUTE LIMIT
Characteristic
Operating Voltage
Supply Voltage
Driver Supply Voltage
Symbol
VDD
VEE
VB
VLCD
T OPR
T STG
Value
-0.3~+7.0
VDD-19.0~VDD+0.3
-0.3~VDD+0.3
VEE-0.3~VDD+0.3
-30~+85
-55~+125
Unit
V
V
V
V
°C
°C
Operating Temperature
Storage Temperature
*1. Based on VSS=0V.
*2. Applies the same supply voltage to VEE1 and VEE2. VLCD=VDD-VEE.
*3. Applies to M, FRM, CL, RSTB, ADC, CLK1, CLK2, CS1B, CS2B, CS3, E, R/W, RS and DB0~DB7.
*4. Applies V0L(R), V2L(R), V3L(R) and V5L(R).
Voltage level: VDD≥V0L=VOR≥V2L=V2R≥V3L=V3R≥V5L=V5R≥VEE.
Note
*1
*4
*1,3
*2
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
ELECTRICAL CHARACTERISTICS
DC Characteristics(VDD=4.5~5.5V, VSS=0V, VDD-VEE=8~17V, Ta=-30~+85°C)
Characteristic
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Three-state(OFF) Input Current
Driver Input Leakage Current
Operating Current
On Resistance
Symbol
VIH1
VIH2
VIL1
VIL2
VOH
VOL
ILKG
ITSL
IDIL
IDD1
IDD2
RON
Condition
IOH=-200µA
IOL=1.6mA
VIN=VSS~VDD
VIN=VSS~VDD
VIN=VEE~VDD
During Display
During Access
Access Cycle=1MHz
VDD-VEE=15V
¡¾ILOAD =0.1mA
Min
0.7VDD
2.0
0
0
2.4
-1.0
-5.0
-2.0
-
Typ
-
Max
VDD
VDD
0.3VDD
0.8
0.4
1.0
5.0
2.0
100
500
Unit
V
V
V
V
V
V
µA
µA
µA
µA
µA
Note
*1
*2
*1
*2
*3
*3
*4
*5
*6
*7
*7
-
-
7.5
KΩ
*8
*1. CL, FRM, M, RSTB, CLK1, CLK2
2. CS1B, CS2B, CS3, E, R/W, RS, DB0~DB7
3. DB0~DB7
4. Excepted DB0~DB7
5. DB0~DB7 at High lmpedance
6. V0L(R), V2L(R), V3L(R), V5L(R)
7. 1/64 duty, FCLK=250KHZ, Frame Frequency=70HZ, Output: No Load
8. VDD~VEE=15.5V
V0L(R)>V2L(R)=VDD-2/7 (VDD-VEE)>V3L(R)=VEE+2/7(VDD-VEE)>V5L(R)
AC Characteristics(VDD=5V±10%, VSS=0V, Ta=-30°C~+85°C)
(1) Clock Timing
Characteristic
CLK1, CLK2 Cycle Time
CLK1 ‘LOW ’ Level Width
CLK2 ‘LOW ’ Level Width
CLK1 ‘HIGH’ Level Width
CLK2 ‘HIGH’ Level Width
CLK1-CLK2 Phase Difference
CLK2-CLK1 Phase Difference
CLK1, CLK2 Rise Time
CLK1, CLK2 Fall Time
Symbol
tCY
tWL1
tWL2
tWH1
tWH2
tD12
tD21
tR
tF
Min
2.5
625
625
1875
1875
625
625
-
Typ
-
Max
20
150
150
Unit
µS
ns
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
tCY
tWH1
tF
tR
CLK1
0.7VDD
0.3VDD
tWL1
tD12
tD21
0.7VDD
CLK2
0.3VDD
tF
tWH2
tF
tWLL
tCY
Fig 1. External clock waveform
(2) Display Control Timing
Characteristic
FRM Delay Time
M Delay Time
CL ‘LOW ’ Level Width
CL ‘HIGH’ Level Width
Symbol
tDF
tDM
tWL
tWH
Min
-2
-2
35
35
Typ
-
tW L
CL
0.7VDD
tW H
0.3VDD
tD F
tD F
0.7VDD
FRM
0.3VDD
tD M
M
0.7VDD
0.3VDD
Fig 2. Display control signal waveform
Max
+2
+2
-
Unit
us
us
us
us
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
(3) MPU Interface
Chatacteristic
E Cycle
E High Level Width
E Low Level Width
E Rise Time
E Fall Time
Address Set-Up Time
Address Hold Time
Data Set-Up Time
Data Delay Time
Data Hold Time (Write)
Data Hold Time (Read)
Symbol
tC
tWH
tWL
tR
tF
tASU
tAH
tSU
tD
tDHW
tDHR
Min
1000
450
450
140
10
200
10
20
Typ
-
tC
E
2.0V
tWL
0.8V
tWH
tR
R/W
tF
tAH
tASU
tASU
CS1B-CS3,RS
tAH
0.8V
2.0V
tDSU
DB0-7
Fig 3. MPU write timing
tDH
Max
25
25
320
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
tC
E
tWL
tWH
tK
R/W
tF
tASU
tAH
tASU
tAH
CS1B-CS3,RS
tD
DB0-7
Fig 3. MPU write timing
tDH
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
APPLICATION CIRCUIT
1.1/64 duty common driver(KS0107B) interface circuit
Rf
Cf
from MPU
~
RSTB
~
DB7
DB0
E
RS
R/W
CS3
C
CS2B
CR
CS1B
R
VDD
VDD
ADC
V0
VOR,VOL
DIO1
Open
V5
V5R,V5L
DIO2
Open
V1
V1R,V1L
M
V4
VEE
V4R,V4L
FRM
VEE
KS0107B
VDD
VOR,VOL
V0
V5R,V5L
V5
FRM
V2R,V3L
V1
CLK1
CLK1
V3R,V3L
CLK2
CLK2
VEE1, VEE2
V4
VEE
KS0108B
M
CL2
CL2
VSS
S1
VDD
S64
SHL
VSS
FS
MS
PCLK2
CL
COM1
DS2
SEG64
LCD
DS1
VSS
SEG1
COM64
C64
VDD
V0
R1
V1
R1
V2
R2
V3
R1
V4
R1
V5
VEE
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
OPERATING PRINCIPLES & METHODS
1. I/O Buffer
Input buffer controls the status between the enable and disable of chip. Unless the CS1B to CS3 is in active mode, Input or
output of data and instruction does not execute. Therefore internal state is not change. But RSTB and ADC can operate
regardless CS1B-CS3.
2. Input register
Input register is provided to interface with MPU which is different operating frequency. Input register stores the data temporarily before writing it into display RAM.
When CS1B to CS3 are in the active mode, R/W and RS select the input register. The data from MPU is written into input
register. Then Writing it into display RAM. Data latched for falling of the E signal and write automatically into the display data
RAM by internal operation.
3. Output register
Output register stores the data temporarily from display data RAM when CS1B, CS2B, CS3 is in active mode and R/W and
RS=H, stored data in display data RAM is latched in output register. When CS1B to CS3 is in active mode and R/W=H, RS=L,
status data (busy check) can read out.
To read the contents of display data RAM, twice access of read instruction is needed. In first access, data in display data RAM
is latched into output register. In second access, MPU can read data which is latched. That is, to read the data in display data
RAM, it needs dummy read. But status read is not needed dummy read.
RS
L
H
R/W
L
H
L
H
Function
Instruction
Status read (busy check)
Data write (from input register to display data RAM)
Data read (from display data RAM to output register)
4. Reset
Reset can be initialized system by setting RSTB terminal at low level when turning power on, receiving instruction from MPU.
When RSTB becomes low, following procedure is occured.
1. Display off
2. Display start line register become set by 0.(Z-address 0)
While RSTB is low, any instruction except status read can be accepted. Reset status appers at DB4. After DB4 is low, any
instruction can be accepted.
The Conditions of power supply at initial power up are shown in table 1.
Table 1. Power Supply Initial Conditions
Item
Symbol
Reset Time
tRS
Rise Time
tR
VDD
Min
1.0
-
Typ
-
Max
200
Unit
us
ns
4.5[V]
tRS
tR
RSTB
0.7VDD
0.3VDD
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
5. Busy flag
Busy flag indicates that KS0108B is operating or no operating. When busy flag is high, KS0108B is in internal operating.
When busy flag is low, KS0108B can accept the data or instruction.
DB7 indicates busy flag of the KS0108B.
6. Display On/Off Flip-Flop
The display on/off flip-flop makes on/off the liquid crystal display. When flip-flop is reset (logical low), selective voltage or
non selective voltage appears on segment output terminals. When flip-flop is set (logic high), non selective voltage appears on
segment output terminals regardless of display RAM data.
The display on/off flip-flop can changes status by instruction. The display data at all segment disappear while RSTB is low.
The status of the flip-flop is output to DB5 by status read instruction.
The display on/off flip-flop synchronized by CL signal.
7. X Page Register
X page register designates page of the internal display data RAM.
It has not count function. An address is set by instruction.
8. Y address counter
Y address counter designates address of the internal display data RAM. An address is set by instruction and is increased
by 1 automatically by read or write operations of display data.
9. Display Data RAM
Display data RAM stores a display data for liquid crystal display. To express on state dot matrix of liquid crystal display, write
data 1. The other way, off state writes 0.
Display data RAM address and segment output can be controlled by ADC signal.
ADC=H¢¡ DB<0:7>=0 - Y-address 0 - A0 - S1
DB<0:7>=63 - Y-address 63 - A63 - S64
ADC=L¢¡ DB<0:7>=0 ~ Y-address 63 - A63 - S64
DB<0:7>=63 ~ A0 - S1
ADC terminal connect the VDD or VSS.
10. Display Start Line Register
The display start line register indicates of display data RAM to display top line of liquid crystal display.
Bit data (DB<0:5>) of the display start line set instruction is latched in display start line register. Latched data is transferred
to the Z address counter while FRM is high, presetting the Z address counter.
It is used for scrolling of the liquid crystal display screen.
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
DISPLAY CONTROL INSTRUCTION
The display control instructions control the internal state of the KS0108B. Instruction is received from MPU to KS0108B for the
display control. The following table shows various instructions.
Instruction
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Function
Display ON/OFF
L
L
L
L
H
H
H
H
H
L/H Controls the display on
or off. Internal status
and display RAM data is
not affected.
L:OFF, H:ON
Set Address
L
L
L
H
Sets the Y address in
Y address (0~63)
the Y address counter.
Set Page
L
L
H
L
H
H
H
Sets the X address at
Page
( X address)
the X address register.
(0~7)
Display Start
L
L
H
H
Indicates the display
Display start line
Line
data RAM displayed at
(0~63)
the top of the screen.
L
L
L
L
Read status.
R
L
O
Status Read
L
H
B
BUSY L: Ready
E
N
U
H: In operation
S
/
S
ON/OFF L: Display ON
E
O
Y
H: Display OFF
T
F
RESET L: Normal
F
H: Reset
Write Display
H
L
Writes data (DB0:7) into
Write Data
Data
display data RAM. After
writing intruction, Y
address is increased by
1 automatically.
Read Display
H
H
Reads data (DB0:7) from
Read Data
Data
display data RAM to the
data bus.
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
2. Timing diagram (1/64 duty)
KS0108B
3.
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
LCD Panel interface application circuit
KS0108B NO. 1
S1
S64
KS0108B NO. 2
S1
S64
KS0108B NO. 8
S1
S64
COM1
KS0107B
(Master)
C1
COM2
COM3
C2
C3
C64
COM64
LCD PANEL
(128x480 dots)
C1
C2
COM65
COM66
C3
COM67
C64
KS0107B
(Master)
COM128
S1
S64
NO.9
KS0108B
S1
S64
NO.10
KS0108B
S1
S64
NO.16
KS0108B
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
PAD DIAGRAM
4
3
2
1
100
99
98
97
96
95
94
93
92
91
90
86
85
84
83
82
81
80
79
78
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
Y
14
67
15
66
16
(0,0)
65
X
17
64
18
63
CHIP SIZE : 4090¡¿4020
19
62
PAD SIZE : 100¡¿100
20
UNIT
61
: ¥ì m
21
60
22
59
23
58
24
57
25
56
* “KS0108B” Marking : easy to find the PAD No.30
26
55
27
54
28
53
29
52
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
KS0108B
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
PAD LOCATION
COORDINATE
PAD
NUMBER
PAD
NAME
PAD
NAME
1845
35
S38
-687
-1845
69
S4
1882
-1275
1845
36
S37
VDD
-1410
1845
37
S36
-562
-1845
70
S3
1882
916
-437
-1845
71
S2
1882
1041
4
V3R
-1882
1809
38
5
V2R
-1882
1684
39
S35
-312
-1845
72
S1
1882
1166
S34
-187
-1845
73
VEE1
1882
6
V5R
-1882
1559
1310
40
S33
-62
-1845
74
V0L
1882
7
V0R
-1882
1435
1434
41
S32
62
-1845
75
V5L
1882
8
VEE2
1559
-1882
1309
42
S31
187
-1845
76
V2L
1882
9
1684
S64
-1882
1165
43
S30
312
-1845
77
V3L
1882
1809
10
S63
-1882
1040
44
S29
437
-1845
78
VSS
1412
1845
11
S62
-1882
915
45
S28
562
-1845
79
DB0
1277
1845
12
S61
-1882
790
46
S27
687
-1845
80
DB1
1142
1845
13
S60
-1882
665
47
S26
812
-1845
81
DB2
1007
1845
14
S59
-1882
540
48
S25
937
-1845
82
DB3
882
1845
15
S58
-1882
415
49
S24
1062
-1845
83
DB4
757
1845
16
S57
-1882
290
50
S23
1187
-1845
84
DB5
632
1845
17
S56
-1882
165
51
S22
1487
-1845
85
DB6
507
1845
18
S55
-1882
40
52
S21
1882
-1379
86
DB7
382
1845
19
S54
-1882
-84
53
S20
1882
-1239
87
NC
20
S53
-1882
-209
54
S19
1882
-1099
88
NC
21
S52
-1882
-334
55
S18
1882
-959
89
22
S51
-1882
-459
56
S17
1882
-834
90
CS3
245
1845
23
S50
-1882
-584
57
S16
1882
-709
91
CS2B
120
1845
24
S49
-1882
-709
58
S15
1882
-584
92
CS1B
-5
1845
25
S48
-1882
-834
59
S14
1882
-459
93
RSTB
-130
1845
26
S47
-1882
-959
60
S13
1882
-334
94
R/W
-255
1845
27
S46
-1882
-1099
61
S12
1882
-209
95
RS
-380
1845
28
S45
-1882
-1239
62
S11
1882
-84
96
CL
-505
1845
29
S44
-1882
-1379
63
S10
1882
41
97
CLK2
-630
1845
30
S43
-1487
-1845
64
S9
1882
166
98
CLK1
-755
1845
31
S42
-1187
-1845
65
S8
1882
291
99
E
-880
1845
32
S41
-1062
-1845
66
S7
1882
416
100
FRM
-1005
1845
33
S40
-937
-1845
67
S6
1882
541
34
S39
-812
-1845
68
S5
1882
666
PAD
NAME
1
ADC
-1140
2
M
3
X
Y
COORDINATE
COORDINATE
PAD
NUMBER
PAD
NUMBER
X
Y
X
Y
791
NC
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