DATASHEET

®
T
UCT
ROD RODUC
P
E
P
T
E
E
L
O
UTSingle Digitally Controlled Potentiometer
OBS UBSTIT 6
1
S
4
E
2
ISL2
SI B L
September 8, 2009
POS Data Sheet
ISL22419
Low Noise, Low Power, SPI® Bus, 128 Taps,
Wiper Only
Features
The ISL22419 integrates a single digitally controlled
potentiometer (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.
• SPI serial interface
(XDCP™)
FN6311.1
• 128 resistor taps
• Non-volatile storage of wiper position
• Wiper resistance: 70Ω typical @ 3.3V
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wiper is controlled by the user through the SPI
serial interface. The potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up the device recalls the content of the
DCP’s IVR to the WR.
• Shutdown mode
• Shutdown current 5µA max
• Power supply: 2.7V to 5.5V
• 50kΩ or 10kΩ total resistance
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T ≤ +55°C
The DCP can be used as a voltage divider in a wide variety
of applications including control, parameter adjustments, AC
measurement and signal processing.
• 8 Lead MSOP
• Pb-free (RoHS compliant)
Pinout
ISL22419
(8 LD MSOP)
TOP VIEW
VCC
SCK
1
8
SDO
2
7
RW
SDI
3
6
SHDN
CS
4
5
GND
Ordering Information
PART
NUMBER
PART
MARKING
RESISTANCE OPTION
(kΩ)
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL22419UFU8Z*
419UZ
50
-40 to +125
8 Ld MSOP
M8.118
ISL22419WFU8Z*
419WZ
10
-40 to +125
8 Ld MSOP
M8.118
*Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL22419
Block Diagram
VCC
SCK
SDO
SPI
INTERFACE
SDI
CS
POWER UP
INTERFACE,
CONTROL
AND
STATUS
LOGIC
WR
RW
NON-VOLATILE
REGISTERS
SHDN
GND
Pin Descriptions
MSOP PIN
SYMBOL
1
SCK
SPI interface clock input
2
SDO
Open Drain Data Output of the SPI serial interface
3
SDI
Data Input of the SPI serial interface
4
CS
Chip Select active low input
5
GND
6
SHDN
7
RW
“Wper” terminal of DCP
8
VCC
Power supply pin
2
DESCRIPTION
Device ground pin
Shutdown active low input
FN6311.1
September 8, 2009
ISL22419
Absolute Maximum Ratings
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any Digital Interface Pin
with Respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Voltage at any DCP pin with Respect to GND . . . . . . . -0.3V to VCC
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Latchup (Note 2) . . . . . . . . . . . . . . . . . . Class II, Level B @+125°C
ESD Rating
HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV
CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
8 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
165
Maximum Junction Temperature (Plastic Package). . . . . . . .+150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
VCC Voltage for DCP Operation . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 3mA
Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
ΝΟΤΕΣ:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -1V for all pins.
Analog Specifications
SYMBOL
RTOTAL
Over recommended operating conditions unless otherwise stated. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested.
PARAMETER
End-to-End Resistance
TEST CONDITIONS
RW
(Note 11)
Wiper Resistance
CW
(Note 11)
Wiper Capacitance
ILkgRW
Leakage on RW Pin
TYP
(Note 3)
MAX
UNIT
W option
10
kΩ
U option
50
kΩ
End-to-End Resistance Tolerance
End-to-End Temperature Coefficient
MIN
-20
+20
%
W option
±50
ppm/°C
(Note 11)
U option
±80
ppm/°C
(Note 11)
VCC = 3.3V @ +25°C,
wiper current = VCC/RTOTAL
70
Ω
25
pF
Voltage at pin from GND to VCC
2
4
µA
-1
1
LSB
(Note 4)
-0.5
0.5
LSB
(Note 4)
VOLTAGE DIVIDER MODE ( measured at RW, unloaded)
INL
(Note 7)
Integral Non-linearity
DNL
(Note 6)
Differential Non-linearity
Monotonic over all tap positions
ZSerror
(Note 5)
Zero-scale Error
W option
0
1
5
LSB
(Note 4)
U option
0
0.5
2
LSB
(Note 4)
W option
-5
-1
0
LSB
(Note 4)
U option
-2
-1
0
LSB
(Note 4)
FSerror
(Note 6)
TCV
(Notes 8, 11)
Full-scale Error
Ratiometric Temperature Coefficient
3
DCP register set to 40 hex
±4
ppm/°C
FN6311.1
September 8, 2009
ISL22419
Operating Specifications Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
SYMBOL
ICC1
ICC2
ISB
ISD
ILkgDig
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 3)
MAX
UNIT
VCC Supply Current (volatile
write/read)
10k DCP, fSPI = 5MHz; (for SPI active, read
and write states)
1
mA
VCC Supply Current (volatile
write/read)
50k DCP, fSPI = 5MHz; (for SPI active, read
and write states)
0.5
mA
VCC Supply Current ( non-volatile
write/read)
10k DCP, fSPI = 5MHz; (for SPI active, read
and write states)
3.2
mA
VCC Supply Current ( non-volatile
write/read)
50k DCP, fSPI = 5MHz; (for SPI active, read
and write states)
2.7
mA
VCC Current (standby)
VCC = +5.5V, 10k DCP, SPI interface in
standby state
850
µA
VCC = +5.5V, 50k DCP, SPI interface in
standby state
160
µA
VCC = +3.6V, 10k DCP, SPI interface in
standby state
550
µA
VCC = +3.6V, 50k DCP, SPI interface in
standby state
100
µA
VCC = +5.5V @ +85°C, SPI interface in
standby state
3
µA
VCC = +5.5V@ +125°C, SPI interface in
standby state
5
µA
VCC = +3.6V @ +85°C, SPI interface in
standby state
2
µA
VCC = +3.6V @ +125°C, SPI interface in
standby state
4
µA
1
µA
VCC Current (shutdown)
Leakage Current, at Pins SHDN, SCK, Voltage at pin from GND to VCC
SDI, SDO and CS
-1
tWRT
(Note 11)
Wiper Response Time
Wiper Response Time after SPI write to WR
register
1.5
µs
tShdnRec
(Note 11)
DCP Recall Time from Shutdown
Mode
From rising edge of SHDN signal to wiper
stored position and RH connection
1.5
µs
SCK rising edge of last bit of ACR data byte
to wiper stored position and RH connection
1.5
µs
Vpor
Power-on Recall Voltage
VCC Ramp
VCC Ramp Rate
tD
Power-up Delay
Minimum VCC at which memory recall occurs
2.0
2.6
V
0.2
V/ms
3
VCC above Vpor, to DCP Initial Value
Register recall completed, and SPI Interface
in standby state
ms
EEPROM SPECIFICATION
EEPROM Endurance
tWC
(Note 9)
EEPROM Retention
Temperature T ≤ +55°C
Non-volatile Write Cycle Time
From rising edge of CS
1,000,000
Cycles
50
Years
12
20
ms
0.3*VCC
V
SERIAL INTERFACE SPECIFICATIONS
VIL
SHDN, SCK, SDI, and CS Input Buffer
LOW Voltage
4
-0.3
FN6311.1
September 8, 2009
ISL22419
Operating Specifications Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested. (Continued)
SYMBOL
PARAMETER
VIH
SHDN, SCK, SDI, and CS Input Buffer
HIGH Voltage
0.7*VCC
Hysteresis
SHDN, SCK, SDI, and CS Input Buffer
Hysteresis
0.05*
VCC
VOL
TEST CONDITIONS
SDO Output Buffer LOW Voltage
IOL = 4mA
Rpu
(Note 10)
SDO Pull-up Resistor Off-chip
Maximum is determined by tRO and tFO with
maximum bus load Cbus = 30pF, fSCK = 5MHz
Cpin
(Note 11)
MIN
TYP
(Note 3)
UNIT
VCC+0.3
V
V
0.4
V
2
kΩ
SHDN, SCK, SDI, SDO and CS Pin
Capacitance
10
pF
fSCK
SPI Frequency
5
MHz
tCYC
SPI Clock Cycle Time
200
ns
tWH
SPI Clock High Time
100
ns
tWL
SPI Clock Low Time
100
ns
tLEAD
Lead Time
250
ns
tLAG
Lag Time
250
ns
tSU
SDI, SCK and CS Input Setup Time
50
ns
tH
SDI, SCK and CS Input Hold Time
50
ns
tRI
SDI, SCK and CS Input Rise Time
10
ns
tFI
SDI, SCK and CS Input Fall Time
10
20
ns
SDO Output Disable Time
0
100
ns
350
ns
tDIS
0
MAX
tV
SDO Output Valid Time
tHO
SDO Output Hold Time
tRO
SDO Output Rise Time
Rpu = 2k, Cbus = 30pF
60
ns
tFO
SDO Output Fall Time
Rpu = 2k, Cbus = 30pF
60
ns
tCS
CS Deselect Time
0
ns
2
µs
NOTES:
3. Typical values are for TA = +25°C and 3.3V supply voltage.
4. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
5. ZS error = V(RW)0/LSB.
6. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting.
7. INL = [V(RW)i – (i • LSB) – V(RW)0]/LSB for i = 1 to 127
Max ( V ( RW ) i ) – Min ( V ( RW ) i )
10 6
8. TC = --------------------------------------------------------------------------------------------- × ----------------- for i = 16 to 127 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper
V
[ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] ⁄ 2 165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.
9. tWC is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle.
10. Rpu is specified for the highest data rate transfer for the device. Higher value pullup can be used at lower data rates.
11. This parameter is not 100% tested.
5
FN6311.1
September 8, 2009
ISL22419
Timing Diagrams
Input Timing
tCS
CS
tCYC
tLEAD
SCK
tSU
tH
...
tWL
tRI
tFI
tWH
...
MSB
SDI
tLAG
LSB
High Impedance
SDO
Output Timing
CS
SCK
tV
tDIS
...
MSB
SDO
SDI
...
tHO
LSB
ADDR
XDCP Timing (for All Load Instructions)
CS
tWC
SCK
SDI
...
MSB
...
tWRT
LSB
VW
SDO
High Impedance
6
FN6311.1
September 8, 2009
ISL22419
Typical Performance Curves
1.4
100
VCC = 3.3V, T = +125°C
1.2
80
1.0
70
60
ISB (µA)
WIPER RESISITANCE (Ω)
90
50
40
30
T = +125°C
0.8
0.6
0.4
T = +25°C
VCC = 3.3V, T = -40°C
VCC = 3.3V, T = +20°C
20
0.2
10
0
2.7
0
0
20
40
60
80
100
120
3.2
3.7
TAP POSITION (DECIMAL)
4.2
4.7
5.2
VCC (V)
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[ I(RW) = VCC/RTOTAL ] FOR 10kΩ (W)
FIGURE 2. STANDBY ICC vs VCC
0.2
0.2
T = +25°C
T = +25°C
VCC = 2.7V
0.1
INL (LSB)
DNL (LSB)
0.1
0
-0.1
VCC = 2.7V
0
-0.1
VCC = 5.5V
VCC = 5.5V
-0.2
-0.2
0
20
40
60
80
100
120
0
20
40
60
80
100
120
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10kΩ (W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10kΩ (W)
1.3
0.0
10k
1.1
-0.3
ZSERROR (LSB)
ZSERROR (LSB)
0.9
0.7
0.5
VCC = 2.7V
VCC = 5.5V
0.3
VCC = 2.7V
-0.6
-0.9
10k
0.1
-0.3
-40
-1.2
50k
-0.1
-20
0
20
40
60
80
100
TEMPERATURE (°C)
FIGURE 5. ZSERROR vs TEMPERATURE
7
VCC = 5.5V
50k
120
-1.5
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (ºC)
FIGURE 6. ZSERROR vs TEMPERATURE
FN6311.1
September 8, 2009
ISL22419
Typical Performance Curves
(Continued)
105
90
0.5
75
TCv (ppm/°C)
END TO END RTOTAL CHANGE (%)
1.0
0.0
-0.5
60
45
50k
30
10k
15
-1.0
-40
0
-20
0
20
40
60
80
100
TEMPERATURE (ºC)
FIGURE 7. END TO END RTOTAL % CHANGE vs
TEMPERATURE
120
16
36
56
76
96
TAP POSITION (DECIMAL)
FIGURE 8. TC FOR VOLTAGE DIVIDER MODE IN ppm
SCL
SIGNAL AT WIPER
(WIPER UNLOADED)
SIGNAL AT WIPER
(WIPER UNLOADED MOVEMENT
FROM 7Fh TO 00h)
WIPER MID POINT MOVEMENT
FROM 3Fh TO 40h
FIGURE 9. MIDSCALE GLITCH, CODE 80h TO 7Fh
8
FIGURE 10. LARGE SIGNAL SETTLING TIME
FN6311.1
September 8, 2009
ISL22419
Pin Description
Potentiometer Pins
RW
RW is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR register.
SHDN
The SHDN pin forces the resistor to end-to-end open circuit
condition and shorts RW to GND. When SHDN is returned to
logic high, the previous latch settings put RW at the same
resistance setting prior to shutdown. This pin is logically
AND with SHDN bit in ACR register. SPI interface is still
available in shutdown mode and all registers are accessible.
This pin must remain HIGH for normal operation.
RW
FIGURE 11. DCP CONNECTION IN SHUTDOWN MODE
Bus Interface Pins
SERIAL CLOCK (SCK)
This is the serial clock input of the SPI serial interface.
SERIAL DATA OUTPUT (SDO)
The SDO is an open drain serial data output pin. During a
read cycle, the data bits are shifted out at the falling edge of
the serial clock SCK, while the CS input is low.
SDO requires an external pull-up resistor for proper
operation.
SERIAL DATA INPUT (SDI)
The SDI is the serial data input pin for the SPI interface. It
receives device address, operation code, wiper address and
data from the SPI external host device. The data bits are
shifted in at the rising edge of the serial clock SCK, while the
CS input is low.
CHIP SELECT (CS)
CS LOW enables the ISL22419, placing it in the active
power mode. A HIGH to LOW transition on CS is required
prior to the start of any operation after power up. When CS is
HIGH, the ISL22419 is deselected and the SDO pin is at
high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state.
SPI serial interface providing direct communication between
host and potentiometer and memory. The resistor array is
comprised of individual resistors connected in series. At
either end of the array and between each resistor is an
electronic switch that transfers the potential at that point to
the wiper.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
When the device is powered down, the last value stored in
IVR will be maintained in the non-volatile memory. When
power is restored, the contents of the IVR is recalled and
loaded into the WR to set the wiper to the initial value.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer and internally connected to VCC and GND.
The RW pin of the DCP is connected to intermediate nodes,
and is equivalent to the wiper terminal of a mechanical
potentiometer. The position of the wiper terminal within the
DCP is controlled by an 7-bit volatile Wiper Register (WR).
When the WR of a DCP contains all zeroes (WR[6:0]: 00h),
its wiper terminal (RW) is closest to GND. When the WR
register of a DCP contains all ones (WR[6:0]: 7Fh), its wiper
terminal (RW) is closest to VCC. As the value of the WR
increases from all zeroes (0) to all ones (127 decimal), the
wiper moves monotonically from the position closest to GND
to the closest to VCC.
While the ISL22419 is being powered up, the WR is reset to
40h (64 decimal), which locates RW roughly at the center
between GND and VCC. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the WR will be reload with the value stored in a
non-volatile Initial Value Register (IVR).
The WR and IVR can be read or written to directly using the
SPI serial interface as described in the following sections.
Memory Description
The ISL22419 contains one non-volatile 7-bit register, known
as the Initial Value Register (IVR), volatile 7-bit Wiper
Register (WR), and volatile 8-bit Access Control Register
(ACR). The memory map of ISL22419 is on Table 1. The
non-volatile register (IVR) at address 0, contains initial wiper
position and volatile register (WR) contains current wiper
position.
TABLE 1. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
2
—
ACR
1
Principles of Operation
0
Reserved
IVR
WR
The ISL22419 is an integrated circuit incorporating one DCP
with its associated registers, non-volatile memory and the
9
FN6311.1
September 8, 2009
ISL22419
The non-volatile IVR and volatile WR registers are
accessible with the same address.
TABLE 4. IDENTIFICATION BYTE FORMAT
The Access Control Register (ACR) contains information
and control bits described below in Table 2.
The VOL bit (ACR[7]) determines whether the access is to
wiper registers WR or initial value registers IVR.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT #
7
BIT NAME VOL
6
5
4
3
2
1
0
SHDN
WIP
0
0
0
0
0
If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note, value
is written to IVR register also is written to the WR. The
default value of this bit is 0.
0
1
0
1
0
0
0
(MSB)
0
(LSB)
The next byte sent to the ISL22419 contains the instruction
and register pointer information. The four MSBs are the
instruction and two LSBs are register address (see Table 5).
TABLE 5. IDENTIFICATION BYTE FORMAT
7
6
5
4
3
2
1
0
I3
I2
I1
I0
0
0
R1
R0
There are only two valid instruction sets:
The SHDN bit (ACR[6]) disables or enables Shutdown mode.
This bit is logically AND with SHDN pin. When this bit is 0, DCP
is in Shutdown mode. Default value of SHDN bit is 1.
1011(binary) - is a Read operation
The WIP bit (ACR[5]) is read only bit. It indicates that nonvolatile write operation is in progress. The WIP bit can be
read repeatedly after a non-volatile write to determine if the
write has been completed. It is impossible to write to the WR
or ACR while WIP bit is 1.
There are only two registers address possible for this DCP. If
the R1, R0 bits are zero, then the read or write is to either
the IVR or the WR register (depends of VOL bit at ACR). If
the R1 bit is 1and R0 bit is 0, then the operation is on the
ACR.
Shutdown Mode
Write Operation
The device can be put in Shutdown mode either by pulling the
SHDN pin to GND or setting the SHDN bit in the ACR register
to 0. The truth table for Shutdown mode is in Table 3.
A Write operation to the ISL22419 is a three-byte operation.
It requires first, the CS transition from HIGH to LOW, then a
valid Identification Byte, then a valid instruction byte followed
by Data Byte is sent to SDI pin. The host terminates the write
operation by pulling the CS pin from LOW to HIGH. For a
write to address 0 (WR), the byte at address 2 (ACR[7])
determines if the Data Byte is to be written to volatile or both
volatile and non-volatile registers. Refer to “Memory
Description” on page 9 and Figure 12.
TABLE 3.
SHDN pin
SHDN bit
Mode
High
1
Normal operation
Low
1
Shutdown
High
0
Shutdown
Low
0
Shutdown
1100(binary) - is a Write operation
The internal non-volatile write cycle starts after rising edge of
CS and takes up to 20ms.
SPI Serial Interface
Read Operation
The ISL22419 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with
data clocked in on the rising edge of SCK, and clocked out
on the falling edge of SCK. CS must be LOW during
communication with the ISL22419. SCK and CS lines are
controlled by the host or master. The ISL22419 operates
only as a slave device.
A read operation to the ISL22419 is a three byte operation. It
requires first, the CS transition from HIGH to LOW, then a
valid Identification Byte, then a valid instruction byte followed
by “dummy” Data Byte is sent to SDI pin. The SPI host reads
the data from SDO pin on falling edge of SCK. The host
terminates the read operation by pulling the CS pin from
LOW to HIGH (see Figure 13).
All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.
In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.
Protocol Conventions
The first byte sent to the ISL22419 from the SPI host is the
Identification Byte. A valid Identification Byte contains 0101
as the four MSBs, with the following four bits set to 0.
10
FN6311.1
September 8, 2009
ISL22419
CS
SCK
SDI
0
1
0
1
0
0
0
0
0
I3
I2
I1
I0
0
0
R1 R0
0
D6 D5 D4
D3
D2
D1 D0
D3
D2
D1 D0
FIGURE 12. THREE BYTE WRITE SEQUENCE
CS
SCK
SDI
Don’t Care
0
1
0
1
0
0
0
0
0
I3
I2
I1
I0
0
0
R1 R0
SDO
0
D6 D5 D4
FIGURE 13. THREE BYTE READ SEQUENCE
Applications Information
Communicating with ISL22419
Communication with ISL22419 proceeds using SPI interface
through the ACR (address 11b), IVR (address 00b) and WR
(address 00b) registers.
The typical application diagram is shown in Figure 14. For
proper operation adding 0.1µF decoupling ceramic capacitor
to VCC is recommended. The capacitor value may vary
based on expected noise frequency of the design.
The wiper of the potentiometer is controlled by the WR
register. Writes and reads can be made directly to this
register to control and monitor the wiper position without any
non-volatile memory changes. This is done by setting MSB
bit (ACR[7]) at address 11b to 1.
The non-volatile IVR stores the power up value of the wiper.
IVR is accessible when MSB bit (ACR[7]) at address 11b is
set to 0. Writing a new value to the IVR register will set a
new power up position for the wiper. Also, writing to this
register will load the same value into the WR as the IVR.
Reading from the IVR will not change the WR, if its contents
are different.
11
FN6311.1
September 8, 2009
ISL22419
Examples:
A. Writing to the IVR:
This sequence will write a new value (77h) to the IVR(non-volatile):
Set the ACR (Addr 02h) for NV write (40h)
Send the ID byte, Instruction Byte, then the Data byte
0 1 0 1 0 0 0 0 1 1 0 0 0 0 1
0
0 1 0 0
(Sent to SDI)
0
0
0
0
Set the IVR (Addr 00h) to 77h
Send the ID byte, Instruction Byte, then the Data byte
0 1 0 1 0 0 0 0 1 1 0 0 0 0 0
0
0 1 1 1
(Sent to SDI)
0
1
1
1
0
1 1 0 0
(Sent to SDI)
0
0
0
0
x
x
x
B. Reading from the WR:
This sequence will read the value from the WR (volatile):
Write to ACR first to access the WR
Send the ID byte, Instruction Byte, then the Data byte
0 1 0 1 0 0 0 0 1 1 0 0 0 0 1
Read the data from WR (Addr 00h)
Send the ID byte, Instruction Byte, then Read the Data byte
0 1 0 1 0 0 0 0 1 0 1 1 0 0 0 0 x x x x x
(Out on SDO)
VCC
VCC
0.1µF
Rpu
VCC
SHDN
0.1µF
SCK
SDO
SDI
RW
VOUT
CS
R2
ISL22419
R1
FIGURE 14. TYPICAL APPLICATION DIAGRAM FOR IMPLEMENTING ADJUSTABLE VOLTAGE REFERANCE
12
FN6311.1
September 8, 2009
ISL22419
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X θ
0.25
(0.010)
R1
R
GAUGE
PLANE
SEATING
PLANE -CA
4X θ
A2
A1
b
-H-
0.10 (0.004)
L1
SEATING
PLANE
C
0.20 (0.008)
C
C
a
CL
E1
0.20 (0.008)
C D
MAX
MIN
MAX
NOTES
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.010
0.014
0.25
0.36
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.026 BSC
0.65 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
0.037 REF
N
-A-
SIDE VIEW
MIN
A
L1
e
D
SYMBOL
e
L
MILLIMETERS
0.95 REF
8
R
0.003
R1
0
α
-
8
-
0.07
0.003
-
5o
15o
0o
6o
7
-
-
0.07
-
-
5o
15o
-
0o
6o
-B-
Rev. 2 01/03
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN6311.1
September 8, 2009
Similar pages