DATASHEET

IGNS
EW DES
N
R
O
F
ENT:
NDED
C OMM E
PLACEM
N OT R E MME N D E D R E
Single
0 Digitally Controlled
RECO
ISL9581
Data Sheet
ISL95811
Potentiometer (XDCP™)
October 6, 2008
FN6759.1
I2C Bus, 256 Taps, 5 Bytes General
Purpose Memory, Low Noise, Low Power
Features
The ISL95811 integrates a digitally controlled potentiometer
(XDCP) and non-volatile memory on a monolithic CMOS
integrated circuit.
• I2C Serial Interface
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wiper is controlled by the user through the I2C
bus interface. The potentiometer has an associated volatile
Wiper Register (WR) and a non-volatile Initial Value Register
(IVR), that can be directly written to and read by the user.
The content of the WR controls the position of the wiper. At
power-up the device recalls the contents of the DCP’s IVR to
the WR.
• Non-volatile Storage of Wiper Position
The DCP can be used as three-terminal potentiometer or as
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments and signal
processing.
• 256 Resistor Taps - 0.4% Resolution
• 5 General Purpose Non-Volatile Bytes
• Write Protection
• Wiper Resistance: 70 Typical @ VCC = 3.3V
• Standby Current 10µA Max
• Power Supply: 2.7V to 5.5V
• 50k, 10k Total Resistance
• High Reliability
- Endurance: 1,000,000 Data Changes per Bit per
Register
- Register Data Retention: 50 Years @ T  +55°C
• 8 Ld MSOP and 8 Ld TDFN Packaging
• Pb-Free (RoHS compliant)
Pinouts
ISL95811
(8 LD TDFN)
TOP VIEW
ISL95811
(8 LD MSOP)
TOP VIEW
WP
1
8
VCC
SCL
2
7
RH
SDA
3
6
RL
GND
4
5
RW
WP 1
8 VCC
SCL 2
7 RH
SDA 3
6 RL
GND 4
5 RW
Ordering Information
PART NUMBER
(Note)
ISL95811WFUZ
PART
MARKING
5811W
RTOTAL
(k)
TEMP.
RANGE
(°C)
10
-40 to +125
PACKAGE
(Pb-Free)
8 Ld MSOP
PKG.
DWG. #
MDP0043
ISL95811WFUZ-T*
5811W
10
-40 to +125
8 Ld MSOP
MDP0043
ISL95811WFUZ-TK*
5811W
10
-40 to +125
8 Ld MSOP
MDP0043
ISL95811WFRTZ
811W
10
-40 to +125
8 Ld 3x3 TDFN
L8.3x3A
ISL95811WFRTZ-TK*
811W
10
-40 to +125
8 Ld 3x3 TDFN
L8.3x3A
ISL95811UFUZ
5811U
50
-40 to +125
8 Ld MSOP
MDP0043
ISL95811UFUZ-T*
5811U
50
-40 to +125
8 Ld MSOP
MDP0043
ISL95811UFUZ-TK*
5811U
50
-40 to +125
8 Ld MSOP
MDP0043
ISL95811UFRTZ
811U
50
-40 to +125
8 Ld 3x3 TDFN
L8.3x3A
ISL95811UFRTZ-TK*
811U
50
-40 to +125
8 Ld 3x3 TDFN
L8.3x3A
*Please refer to TB347 for details on reel specifications
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Corporation. Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL95811
Block Diagram
VCC
RH
SDA
WIPER
REGISTER
I2C AND
SCL
RW
CONTROL
NON-VOLATILE
WP
REGISTER
RL
GND
Pin Descriptions
MSOP
PIN NUMBER
TDFN
PIN NUMBER
SYMBOL
DESCRIPTION
1
1
WP
Hardware write protection. Active low. Prevents any “Write” operation of the
I2C interface.
2
2
SCL
I2C interface input clock
3
3
SDA
Open Drain Serial Data I/O for the I2C interface
4
4
GND
Ground
5
5
RW
“Wiper” terminal of the DCP
6
6
RL
“Low” terminal of the DCP
7
7
RH
“High” terminal of the DCP
8
8
VCC
Power supply
EPAD*
Exposed Die Pad internally connected to GND
*NOTE: PCB thermal land for QFN/TDFN EPAD should be connected to GND plane or left floating. For more information refer to
http://www.intersil.com/data/tb/TB389.pdf.
2
FN6759.1
October 6, 2008
ISL95811
Absolute Maximum Ratings
Thermal Information
Voltage at any Digital Interface Pin
with respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Voltage at any DCP Pin with respect to GND . . . . . . . . . .0V to VCC
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
8 Ld TDFN (Notes 1, 2). . . . . . . . . . . .
52
9
8 Ld MSOP (Note 1) . . . . . . . . . . . . . .
160
N/A
Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Latchup (Note 3) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW
Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
3. Jedec Class II pulse conditions and failure criterion used. Level B exceptions is using a max positive pulse of 6.5V on the WP pin.
Analog Specifications
SYMBOL
RTOTAL
Over recommended operating conditions unless otherwise stated.
PARAMETER
RH to RL Resistance
MIN
(Note 18)
TEST CONDITIONS
RTOTAL = (VRH - VRL)/IDCP
k
U option
50
k
-20
VCC = 3.3V @ +25°C
Wiper current = VCC/RTOTAL
RWnoise
(Note 16)
Noise Level
Wiper at the middle scale, 1kHz 1VRMS
input to RH pin
CH/CL/CW
(Note 16)
Potentiometer Capacitance
Leakage on DCP Pins
UNIT
10
Wiper Resistance
ILkgDCP
MAX
(Note 18)
W option
RH to RL Resistance Tolerance
RW
TYP
(Note 4)
70
Voltage at pin from GND to VCC
+20
%
200

-110
dBV
10/10/25
pF
0.1
1
µA
-1
1
LSB
(Note 5)
W option
-0.75
0.75
U option
-0.5
0.5
LSB
(Note 5)
VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded)
INL (Note 9)
Integral Non-Linearity
DCP register set between 1 hex and FFhex.
Monotonic over all tap positions.
W and U options
DNL (Note 8)
Differential Non-Linearity
DCP register set between 1 hex
and FF hex. Monotonic over all
tap positions
ZSerror (Note 6) Zero-Scale Error
FSerror (Note 7) Full-Scale Error
TCV
(Note 10, 16)
fCUTOFF
(Note 16)
W option
0
1
5
U option
0
0.5
2
W option
-5
-1
0
U option
-2
-0.5
0
Ratiometric Temperature
Coefficient
DCP Register set to 80 hex
3dB Cut-Off Frequency
Wiper at the middle scale
3
LSB
(Note 5)
LSB
(Note 5)
±4
ppm/°C
W option
1250
kHz
U option
250
kHz
FN6759.1
October 6, 2008
ISL95811
Analog Specifications
SYMBOL
Over recommended operating conditions unless otherwise stated. (Continued)
PARAMETER
MIN
(Note 18)
TEST CONDITIONS
TYP
(Note 4)
MAX
(Note 18)
UNIT
RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)
RINL (Note 14)
Integral Non-Linearity
RDNL (Note 13) Differential Non-Linearity
Roffset (Note 12) Offset
TCR
(Note 15, 16)
Resistance Temperature
Coefficient
DCP register set between 1 hex
and FF hex. Monotonic over all
tap positions.
W option
-3
3
MI
(Note 11)
U option
-1
1
MI
(Note 11)
DCP register set between 1 hex
and FF hex. Monotonic over all
tap positions
W option
-0.75
0.75
MI
(Note 11)
U option
-0.5
0.5
MI
(Note 11)
W option
0
1
5
MI
(Note 11)
U option
0
0.5
2
MI
(Note 11)
DCP register set between 20 hex and FF
hex
±45
ppm/°C
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 18) (Note 4) (Note 18) UNITS
ICC1
VCC Supply Current
(Volatile Write/Read)
fSCL = 400kHz; SDA = Open; (for I2C, Active,
Read and Volatile Write States only)
100
µA
ICC2
VCC Supply Current
(Non-volatile Write)
fSCL = 400kHz; SDA = Open; (for I2C, Active,
Non-volatile Write State only)
2
mA
ISB
VCC Current (Standby)
VCC = +5.5V, I2C Interface in Standby State
10
µA
VCC = +3.6V, I2C Interface in Standby State
5
µA
1
µA
1
µs
2.6
V
ILkgDig
Leakage Current, at Pins SDA, SCL, Voltage at pin from GND to VCC
and WP Pins
tDCP
DCP Wiper Response Time
SCL falling edge of last bit of DCP Data
Byte to wiper change
Vpor
Power-On Recall Voltage
Minimum VCC at which memory recall occurs
VCCRamp
VCC Ramp Rate
tD
Power-Up Delay
-1
1.8
0.2
V/ms
3
VCC above VPOR, to DCP Initial Value Register
recall completed, and I2C Interface in standby
state
ms
EEPROM SPECIFICATIONS
EEPROM Endurance
EEPROM Retention
Temperature 55°C
1,000,000
Cycles
50
Years
SERIAL INTERFACE SPECIFICATIONS
VIL
WP, SDA, and SCL Input Buffer LOW
Voltage
VIH
WP, SDA, and SCL Input Buffer
HIGH Voltage
Hysteresis (Note 16) SDA and SCL Input Buffer Hysteresis
VOL
Cpin (Note 16)
SDA Output Buffer LOW Voltage,
Sinking 4mA
WP, SDA, and SCL Pin Capacitance
4
-0.3
0.3*VCC
V
0.7*VCC
VCC +
0.3
V
0.05*VCC
0
V
0.4
V
10
pF
FN6759.1
October 6, 2008
ISL95811
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
fSCL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 18) (Note 4) (Note 18) UNITS
SCL Frequency
400
kHz
tIN
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
50
ns
tAA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of VCC window.
900
ns
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC during
the following START condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
crossing 70% of VCC.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC to
SCL falling edge crossing 70% of VCC.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VCC to
SDA entering the 30% to 70% of VCC window.
0
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VCC.
600
ns
tHD:STO
STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge. Both
or Volatile Only Write
crossing 70% of VCC.
600
ns
tHD:STO:NV
STOP Condition Hold Time for Non- From SDA rising edge to SCL falling edge. Both
Volatile Write
crossing 70% of VCC.
2
µs
Output Data Hold Time
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window.
0
ns
tR (Note 16)
SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1 * Cb
250
ns
tF (Note 16)
SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
ns
Cb (Note 16)
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu (Note 16)
SDA and SCL Bus Pull-Up Resistor Maximum is determined by tR and tF.
Off-Chip
For Cb = 400pF, max is about 2k~2.5k.
For Cb = 40pF, max is about 15k~20k
tWC (Note 17)
Non-Volatile Write Cycle Time
tDH
1
k
12
20
ms
tSU:WP
WP Setup Time
Before START condition
600
ns
tHD:WP
WP Hold Time
After STOP condition
600
ns
NOTES:
4. Typical values are for TA = +25°C and 3.3V supply voltage.
5. LSB: [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
6. ZS error = V(RW)0/LSB.
7. FS error = [V(RW)255 – VCC]/LSB.
8. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting.
5
FN6759.1
October 6, 2008
ISL95811
NOTES: (continued)
9. INL = [V(RW)i – (i • LSB – V(RW)0)]/LSB for i = 1 to 255.
Max  V  RW  i  – Min  V  RW  i 
10 6
10. TC V = ----------------------------------------------------------------------------------------------  --------------------- for i = 16 to 240 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper
 Max  V  RW  i  + Min  V  RW  i    2 +165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.
11. MI = |R255 – R0|/255. R255 and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively.
Roffset = R0/MI, when measuring between RW and RL.
12. Roffset = R255/MI, when measuring between RW and RH.
13. RDNL = (Ri – Ri-1)/MI, for i = 16 to 255.
14. RINL = [Ri – (MI • i) – R0]/MI, for i = 16 to 255.
6
 Max  Ri  – Min  Ri  
10
15. TC R = ----------------------------------------------------------------  --------------------- for i = 32 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is
 Max  Ri  + Min  Ri    2 +165°C the minimum value of the resistance over the temperature range.
16. Limits established by characterization and are not production tested.
17. tWC is the time from a valid STOP condition at the end of a Write sequence of a I2C serial interface Write operation, to the end of the self-timed
internal non-volatile write cycle. The Acknowledge Polling method can be used to determine the end of the non-volatile write cycle.
18. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
SDA vs SCL Timing
tHIGH
tF
SCL
tLOW
tR
tWC
tSU:DAT
tSU:STA
SDA
(INPUT TIMING)
tHD:DAT
tHD:STA
tSU:STO
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
WP Pin Timing
STOP
START
SCL
tHD:STO
tHD:STO:NV
CLK 1
SDA IN
tSU:WP
tHD:WP
WP
6
FN6759.1
October 6, 2008
ISL95811
Typical Performance Curves
1.60
T = -40°C
120
T = +25°C
T = +125°C
STANDBY ICC (µA)
WIPER RESISTANCE ()
140
VCC = 2.7V
100
80
60
40
T = +125°C
1.20
0.80
0.40
T = +25°C
20
T = -40°C
0
0
50
T = +25°C
T = +125°C
VCC = 5.5V
100
150
200
TAP POSITION (DECIMAL)
0.00
2.7
250
VCC = 2.7V
VCC = 2.7V
T = +25°C
T = +25°C
0.25
INL (LSB)
0.25
DNL (LSB)
5.2
0.50
0.50
0
0
VCC = 5.5V
-0.25
-0.25
VCC = 5.5V
0
50
100
150
200
TAP POSITION (DECIMAL)
-0.50
250
0.50
50
100
150
200
TAP POSITION (DECIMAL)
2.0
T = +25°C
VCC = 2.7V
1.5
RINL (MI)
0.25
0
-0.25
50
100
150
TAP POSITION (DECIMAL)
200
250
FIGURE 5. RDNL vs TAP POSITION IN RHEOSTAT MODE
FOR 10k (W)
7
250
T = +25°C
VCC = 2.7V
1.0
0.5
0
VCC = 5.5V
-0.50
0
0
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k (W)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k (W)
RDNL (MI)
3.7
4.2
4.7
SUPPLY VOLTAGE (V)
FIGURE 2. STANDBY ICC vs VCC
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[I(RW) = VCC/RTOTAL] FOR 10k (W)
-0.50
3.2
T = -40°C
-0.5
0
VCC = 5.5V
50
100
150
200
TAP POSITION (DECIMAL)
250
FIGURE 6. RINL vs TAP POSITION IN RHEOSTAT MODE FOR
10k (W)
FN6759.1
October 6, 2008
ISL95811
Typical Performance Curves
(Continued)
0
1.6
VCC = 2.7V
FULL SCALE ERROR (LSB)
ZERO SCALE ERROR (LSB)
2.0
1.2
0.8
VCC = 5.5V
0.4
0
-40
0
40
TEMPERATURE (°C)
80
-1.0
-1.5
VCC = 2.7V
-2.0
-40
120
FIGURE 7. ZSerror vs TEMPERATURE
T = +25°C
0.25
INL (LSB)
DNL (LSB)
0
50
0
-0.25
VCC = 5.5V
100
150
200
TAP POSITION (DECIMAL)
-0.50
0
250
FIGURE 9. DNL vs TAP POSITION IN RHEOSTAT MODE FOR
50k (U)
VCC = 5.5V
50
100
150
200
TAP POSITION (DECIMAL)
250
FIGURE 10. INL vs TAP POSITION IN RHEOSTAT MODE FOR
50k (U)
0.2
0.5
VCC = 2.7V
T = +25°C
0.4
0.1
T = +25°C
VCC = 2.7V
0.3
RINL (MI)
RDNL (MI)
120
T = +25°C
VCC = 2.7V
0.1
0
0.2
0.1
0
-0.1
VCC = 5.5V
-0.2
0
40
80
TEMPERATURE (°C)
0.50
VCC = 2.7V
-0.2
0
0
FIGURE 8. FSerror vs TEMPERATURE
0.2
-0.1
VCC = 5.5V
-0.5
50
VCC = 5.5V
-0.1
100
150
200
TAP POSITION (DECIMAL)
250
FIGURE 11. RDNL vs TAP POSITION IN RHEOSTAT MODE
FOR 50k (U)
8
-0.2
0
50
100
150
200
TAP POSITION (DECIMAL)
250
FIGURE 12. RINL vs TAP POSITION IN RHEOSTAT MODE FOR
50k (U)
FN6759.1
October 6, 2008
ISL95811
Typical Performance Curves
(Continued)
250
250
T = -40°C TO +125°C
T = -40°C TO +125°C
VCC = 2.7V
TCv (ppm/°C)
TCr (ppm/°C)
200
VCC = 2.7V
200
150
100
150
100
VCC = 5.5V
50
50
VCC = 5.5V
0
15
65
115
165
TAP POSITION (DECIMAL)
0
15
215
0.8
0.6
VCC = 2.7V
0.4
0.2
0.0
-0.2
40
VCC = 5.5V
0
40
80
TEMPERATURE (°C)
120
FIGURE 15. END-TO-END RTOTAL % CHANGE vs
TEMPERATURE, 10k (W)
115
165
TAP POSITION (DECIMAL)
215
FIGURE 14. TCv FOR VOLTAGE DIVIDER MODE 10k (W) IN
ppm
END-TO-END RTOTAL CHANGE (%)
END-TO-END RTOTAL CHANGE (%)
FIGURE 13. TCr FOR RHEOSTAT MODE 10k (W) IN ppm
65
1.0
VCC = 2.7V
0.5
0.0
VCC = 5.5V
-0.5
-1.0
-40
0
40
80
TEMPERATURE (°C)
120
FIGURE 16. END-TO-END RTOTAL % CHANGE vs
TEMPERATURE, 50k (U)
address and data from an I2C external master device at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock.
Pin Description
Potentiometers Pins
RH AND RL
The high (RH) and low (RL) terminals of the ISL95811 are
equivalent to the fixed terminals of a mechanical
potentiometer. RH and RL are referenced to the relative
position of the wiper and not the voltage potential on the
terminals. With WR set to 255 decimal, the wiper will be
closest to RH, and with the WR set to 0, the wiper is closest
to RL.
RW
RW is the wiper terminal, and it is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR register.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for I2C
interface. It receives device address, operation code, wiper
9
SDA requires an external pull-up resistor, since it is an open
drain input/output.
SERIAL CLOCK (SCL)
This input is the serial clock of the I2C serial interface. SCL
requires an external pull-up resistor.
WRITE PROTECT (WP)
When this pin is kept LOW, the data is written to the device
will be ignored. This pin protectS the non-volatile memory
from being overwritten.
Principles of Operation
The ISL95811 is an integrated circuit incorporating one DCP
with its associated registers, non-volatile memory and an I2C
serial interface providing direct communication between a
host and the potentiometer and memory. The resistor array
is comprised of individual resistors connected in series. At
FN6759.1
October 6, 2008
ISL95811
either end of the array and between each resistor is an
electronic switch that transfers the potential at that point to
the wiper.
TABLE 1. MEMORY MAP
ADDRESS
(hex)
NON-VOLATILE
VOLATILE
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
8
NA
ACR
When the device is powered down, the last value stored in
IVR will be maintained in the non-volatile memory. When
power is restored, the contents of the IVR are recalled and
loaded into the WR to set the wiper to the initial value.
6
General Purpose
N/A
5
General Purpose
N/A
4
General Purpose
N/A
3
General Purpose
N/A
2
General Purpose
N/A
1
Device ID (read only)
N/A
0
IVR
WR
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). When the WR of a DCP
contains all zeroes (WR[7:0] = 00h), its wiper terminal (RW)
is closest to its “Low” terminal (RL). When the WR register of
a DCP contains all ones (WR[7:0] = FFh), its wiper terminal
(RW) is closest to its “High” terminal (RH). As the value of
the WR increases from all zeroes (0) to all ones (255
decimal), the wiper moves monotonically from the position
closest to RL to the position closest to RH. At the same time,
the resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.
While the ISL95811 is being powered up, the WR is reset to
80h (128 decimal), which locates RW roughly at the center
between RL and RH. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the WR will be reloaded with the value stored in a
non-volatile Initial Value Register (IVR).
The WR and IVR can be read or written to directly using the
I2C serial interface, as described in the following sections.
Memory Description
The ISL95811 contains one non-volatile 8-bit Initial Value
Register (IVR), five General Purpose non-volatile 8-bit registers
and two volatile 8-bit registers: Wiper Register (WR) and
Access Control Register (ACR). The Memory map of the
ISL95811 is shown in Table 1. The non-volatile register (IVR) at
address 0 contains the initial wiper position and the volatile
register (WR) contains the current wiper position.
7
Reserved
The ISL95811 is pre-programed with 80h in the IVR.
The non-volatile IVR and volatile WR registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described in Table 2.
The VOL bit (ACR[7]) determines whether the access to
wiper registers WR or initial value registers IVR.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT #
7
6
5
4
3
2
1
0
NAME
VOL
0
0
0
0
0
0
0
If VOL bit is 0, the non-volatile IVR register and General
Purpose registers are accessible. If VOL bit is 1, only the
volatile WR is accessible. Note: Value written to the IVR
register is also written to the WR. The default value of this bit
is 0.
The Device ID register is read only and it contains chip
revision information, as shown in Table 3.
TABLE 3. DEVICE ID REGISTER
BIT #
7
6
5
4
3
2
1
0
VALUE
1
0
0
0
0
0
0
0
I2C Serial Interface
The ISL95811 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL95811
operates as a slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
10
FN6759.1
October 6, 2008
ISL95811
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 17). On power-up of the ISL95811, the SDA pin is in
the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL95811 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 17). A START condition is ignored during the
power-up sequence and during internal non-volatile write
cycles.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 17). A STOP condition at the end
of a read operation, or at the end of a write operation to
volatile bytes only places the device in its standby mode. A
STOP condition during a write operation to a non-volatile
byte initiates an internal non-volatile write cycle. The device
enters its standby state when the internal non-volatile write
cycle is completed.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting 8 bits. During the ninth clock cycle, the receiver
pulls the SDA line LOW to acknowledge the reception of the
8 bits of data (see Figure 18).
The ISL95811 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL95811 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
A valid Identification Byte contains 0101000 as the seven
MSBs. The LSB is the Read/Write bit. Its value is “1” for a
Read operation and “0” for a Write operation (see Table 4).
TABLE 4. IDENTIFICATION BYTE FORMAT
0
1
0
1
0
0
(MSB)
0
R/W
(LSB)
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 17. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
HIGH IMPEDANCE
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER
11
FN6759.1
October 6, 2008
ISL95811
WRITE
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
S
T
A
R
T
IDENTIFICATION
BYTE
ADDRESS
BYTE
0 1 0 1 0 0 0 0
SIGNALS FROM
THE ISL95811
S
T
O
P
DATA
BYTE
0 0 0 0
A
C
K
A
C
K
A
C
K
FIGURE 19. BYTE WRITE SEQUENCE
SIGNALS
FROM THE
MASTER
S
T
A
R
T
SIGNAL AT SDA
IDENTIFICATION
BYTE WITH
R/W = 0
ADDRESS
BYTE
0 1 0 1 0 0 0 0
A
C
K
S
T
O
P
A
C
K
0 1 0 1 0 0 0 1
0 0 0 0
A
C
K
SIGNALS FROM
THE SLAVE
S
T
A IDENTIFICATION
R
BYTE WITH
T
R/W = 1
A
C
K
A
C
K
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 20. READ SEQUENCE
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL95811 responds with an ACK. At this time, if the Data
Byte is to be written only to volatile registers, then the device
enters its standby state. If the Data Byte is to be written also
to non-volatile memory, the ISL95811 begins its internal write
cycle to non-volatile memory. During the internal non-volatile
write cycle, the device ignores transitions at the SDA and
SCL pins, and the SDA output is at a high impedance state.
When the internal non-volatile write cycle is completed, the
ISL95811 enters its standby state (see Figure 19).
The byte at address 08h determines if the Data Byte is to be
written to volatile and/or non-volatile memory (see “Memory
Description” on page 10).
Data Protection
The WP pin has to be at logic HIGH to perform any Write
operation to the device. When the WP is active (LOW), the
device ignores Data Bytes of a Write Operation and does not
respond to the Data Bytes with an ACK; rather it goes into
standby state waiting for a new START condition.
received. If the Address Byte is 0 or 8, the Data Byte is
transferred to the Wiper Register (WR) or to the Access
Control Register respectively, at the falling edge of the SCL
pulse that loads the last bit (LSB) of the Data Byte. If the
Address Byte is 0, and the Access Control Register is all
zeros (default), then the STOP condition initiates the internal
write cycle to non-volatile memory.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (see Figure 20). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W bit set to “1”. After each of
the three bytes, the ISL95811 responds with an ACK. The
ISL95811 then transmits the Data Byte and the master then
terminates the read operation (issuing a STOP condition)
following the last bit of the Data Byte.
The byte at address 08h determines if the Data Bytes being
read are from volatile or non-volatile memory (see “Memory
Description” on page 10).
A STOP condition also acts as a protection of non-volatile
memory. A valid Identification Byte, Address Byte, and total
number of SCL pulses act as a protection of both volatile
and non-volatile registers. During a Write sequence, the
Data Byte is loaded into an internal shift register as it is
12
FN6759.1
October 6, 2008
ISL95811
Mini SO Package Family (MSOP)
0.25 M C A B
D
MINI SO PACKAGE FAMILY
(N/2)+1
N
E
MDP0043
A
E1
MILLIMETERS
PIN #1
I.D.
1
B
(N/2)
e
H
C
SEATING
PLANE
0.10 C
N LEADS
0.08 M C A B
b
SYMBOL
MSOP8
MSOP10
TOLERANCE
NOTES
A
1.10
1.10
Max.
-
A1
0.10
0.10
±0.05
-
A2
0.86
0.86
±0.09
-
b
0.33
0.23
+0.07/-0.08
-
c
0.18
0.18
±0.05
-
D
3.00
3.00
±0.10
1, 3
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
8
10
Reference
Rev. D 2/07
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
L
A1
0.25
3° ±3°
DETAIL X
13
FN6759.1
October 6, 2008
ISL95811
Thin Dual Flat No-Lead Plastic Package (TDFN)
L8.3x3A
2X
0.15 C A
A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
MILLIMETERS
2X
0.15 C B
E
SYMBOL
MIN
A
0.70
A1
-
A3
6
INDEX
AREA
b
TOP VIEW
B
0.10 C
//
C
SEATING
PLANE
SIDE VIEW
D2
(DATUM B)
A3
7
-
0.30
0.35
5, 8
2.40
7, 8, 9
1.60
7, 8, 9
-
2.30
-
1.50
-
0.65 BSC
-
k
0.25
-
-
-
L
0.20
0.30
0.40
8
N
8
Nd
4
8
2
3
Rev. 3 11/04
NOTES:
D2/2
1
6
INDEX
AREA
0.08 C
0.80
0.05
3.00 BSC
1.40
e
A
0.02
NOTES
3.00 BSC
2.20
E
E2
0.75
MAX
0.20 REF
0.25
D
D2
NOMINAL
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
NX k
4. All dimensions are in millimeters. Angles are in degrees.
(DATUM A)
E2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
E2/2
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N
N-1
NX b
e
8
5
(Nd-1)Xe
REF.
0.10 M C A B
BOTTOM VIEW
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Compliant to JEDEC MO-WEEC-2 except for the “L” min
dimension.
CL
(A1)
NX (b)
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
L1
5
10 L
e
SECTION "C-C"
TERMINAL TIP
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN6759.1
October 6, 2008
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