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128-Tap DCP, 16kbit EEPROM, and I2C Serial Interface
ISL96017
Features
This device integrates a 128-tap digitally controlled
potentiometer, 16kbit of EEPROM, and a 2-wire I2C serial
interface. The device is powered by a single 3.3V supply. The
potentiometer is available with total resistance of either 10k
or 50k.
• Integrated Digitally Controlled Potentiometer
- 128-Tap Positions
- 10k50k Total Resistance
- Monotonic Over Temperature
- Non-Volatile Wiper Position Storage
- 0 to VDD Terminal Voltage
The memory is organized in 128 pages of 16 bytes each, to
reduce total programming time. All programming signals are
generated on-chip.
The potentiometer is implemented with a combination of
CMOS switches and resistor elements. The position of the
wiper can be stored in non-volatile memory and then be
recalled upon a subsequent power-up. The three terminals of
the potentiometer are available for use as either a variable
resistor or a resistor divider.
• I2C Serial Interface
• 16kbit EEPROM
- 50 Years Retention @  55°C
- 1,000,000 Cycles Endurance
• Single 3.3 ±0.3V Supply
• 3mm x 3mm Thin DFN Package – 0.8mm Max Thickness,
0.65mm Pitch
• Pb-Free (RoHS Compliant)
16kbit
EEPROM
SDA
SCL
POWER-UP,
INTERFACE,
AND
CONTROL
LOGIC
WP
RH
RW
RL
FIGURE 1. BLOCK DIAGRAM
June 8, 2012
FN8243.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005, 2006, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL96017
Pin Configuration
Pin Descriptions
ISL96017
(8 LD TDFN)
TOP VIEW
PIN SYMBOL
RH 1
8 WP
RW 2
7 SCL
RL 3
6 SDA
VDD 4
5 GND
DESCRIPTION
1
RH
“High” terminal of the DCP
2
RW
“Wiper” terminal of the DCP
3
RL
“Low” terminal of the DCP
4
VDD
Power supply
5
GND
Ground
6
SDA
Open drain serial interface data input/output
7
SCL
Open drain serial interface clock input
8
WP
Hardware write protection pin. Active low. Prevents any
“Write” operation to the device.
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
RTOTAL
(k)
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL96017WIRT8Z
96017 WIZ
10
-40 to 85
8 Ld 3x3 TDFN
L8.3x3A
ISL96017UIRT8Z
96017 UIZ
50
-40 to 85
8 Ld 3x3 TDFN
L8.3x3A
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN8243.2
June 8, 2012
ISL96017
Absolute Maximum Ratings
Thermal Information
Storage Temperature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Note: All Voltages with Respect to GND
Voltage at SCL, SDA, WP: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4V
Voltage at RH, RW, RL: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VDD
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4V
Lead Temperature (Soldering, 10s): . . . . . . . . . . . . . . . . . . . . . . . . . .300°C
Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
ESD (MIL-STD-883B, Method 3014). . . . . . . . . . . . . . . . . . . . . . . . . .>2000V
ESD (Machine Model). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >150V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
8 Ld TDFN Package (Notes 3, 4). . . . . . . . .
52
5
Moisture Sensitivity (see Technical Brief TB363). . . . . . . . . .Level 2
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . . 150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
VDD Voltage for DCP Operation . . . . . . . . . . . . . . . . . . . . . . . . . 3.0V to 3.6V
Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 3mA
Power Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mW
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379 for details.
4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Over recommended operating conditions unless otherwise stated. All voltages with respect to GND. Boldface
limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 18) (Note 5) (Note 18)
UNIT
IccdSby
Standby Current at VDD
Serial interface in standby
10
µA
IccdRd
Read Current at VDD
Reading with 400kHz at SCL
1
mA
IccdWr
Write Current at VDD
Writing to EEPROM
5
mA
ILkgDig
Leakage Current at Pins SDA, SCL, and WP
Pin voltage from GND to VDD
-10
10
µA
ILkgDCP
Leakage Current at RH, RW, RL
Pin voltage from GND to VDD
-1
1
µA
VDDRamp
VDD Power-Up Ramp Rate
tDCP
(Note 17)
DCP Wiper Response Time
SCL falling edge of last bit of DCP Data Byte to
wiper change
Power-Up Delay
VDD above 2.6V, to DCP Initial Value Register
recall completed, and I2C Interface in standby
state
tD
CH/CW/CL
(Note 17)
RTotal
RWiper
0.2
1.5
W and U versions, respectively. TA = 25°C.
Measured between RH and RL pins.
RTotal Tolerance
TA = 25°C. Measured between RH and RL
pins.
Wiper Resistance
VDD = 3.3V @ 25°C. Wiper current =
VDD/RTotal
DCP Resolution
µs
3
RH, RW, RL Pin Capacitance
Total Resistance
V/ms
ms
10
pF
10, 50
k
-20
100
20
%
300

7
Bits
DCP IN VOLTAGE DIVIDER MODE (0V at RL, VCC at RH; measured at RW unloaded)
FSerror
(Note 6, 7)
Full-Scale Error
ZSerror
(Note 6, 8)
Zero-Scale Error
3
U option
-2
-1
0
LSB
W option
-5
-1
0
LSB
U option
0
1
2
LSB
W option
0
1
5
LSB
FN8243.2
June 8, 2012
ISL96017
Electrical Specifications
Over recommended operating conditions unless otherwise stated. All voltages with respect to GND. Boldface
limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
TCV
(Note 11, 17)
PARAMETER
Ratiometric Temperature
Coefficient
DNL (Note 6, 9) Differential Non-Linearity
TEST CONDITIONS
MIN
TYP
MAX
(Note 18) (Note 5) (Note 18)
UNIT
±4
ppm/°C
DCP Register between 10 hex and 6F hex
Monotonic over all tap positions
INL (Note 6, 10) Integral Non-Linearity
-0.75
0.75
LSB
-1
1
LSB
0.5
2
MI
1
5
MI
DCP IN RESISTOR MODE (Measurements between RH and RW with RL not connected)
R127 (Note 12) Resistance Offset.
U version - DCP Register set to 7F hex.
Measured between RH and RW pins.
0
W version - DCP Register set to 7F hex.
Measured between RH and RW pins.
TCR
(Note 15,17)
Resistance Temperature Coefficient
RDNL
(Note 12,13)
Resistance Differential Non-Linearity
RINL
(Note 12,14)
Resistance Integral Non-Linearity
±100
ppm/°C
-0.75
0.75
MI
(Note 1)
-1
1
MI
(Note 1)
EEPROM SPECS
EEPROM Endurance
EEPROM Retention
tWC (Note 16)
At 55°C
1,000,000
Cycles
50
Years
Non-Volatile Write Cycle Time
6
12
ms
SERIAL INTERFACE SPECS
VIL
WP, SDA, and SCL Input Buffer LOW Voltage
-0.3
0.3*
VDD
V
VIH
WP, SDA and SCL Input Buffer HIGH Voltage
0.7*
VDD
VDD
+0.3
V
SDA and SCL Input Buffer Hysteresis
0.05*
VDD
Hysteresis
V
VOL
SDA Output Buffer LOW Voltage, Sinking
4mA
Cpin
WP, SDA, and SCL Pin Capacitance
10
pF
fSCL
SCL Frequency
400
kHz
0
0.4
V
tIN
Pulse Width Suppression Time at SDA and
SCL Inputs.
Any pulse narrower than the max spec is
suppressed
50
ns
tAA
SCL Falling Edge to SDA Output Data Valid
SCL falling edge crossing 30% of VDD, until
SDA exits the 30% to 70% of VDD window
900
ns
tBUF
Time the Bus Must be Free Before the Start of SDA crossing 70% of VCC during a STOP
a New Transmission
condition, to SDA crossing 70% of VDD during
the following START condition
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD crossing
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD crossing
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
crossing 70% of VDD
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VDD to
SCL falling edge crossing 70% of VDD
600
ns
4
FN8243.2
June 8, 2012
ISL96017
Electrical Specifications
Over recommended operating conditions unless otherwise stated. All voltages with respect to GND. Boldface
limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 18) (Note 5) (Note 18)
UNIT
100
ns
From SCL rising edge crossing 70% of VDD to
SDA entering the 30% to 70% of VDD window
0
ns
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VDD
600
ns
STOP Condition Hold Time
From SDA rising edge to SCL falling edge. Both
crossing 70% of VDD
600
ns
tDH
Output Data Hold Time
From SCL falling edge crossing 30% of VDD,
until SDA enters the 30% to 70% of VDD
window
0
ns
tR
SDA and SCL Rise Time
From 30% to 70% of VDD
20+
0.1*Cb
250
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
20+
0.1*Cb
250
ns
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
SDA and SCL Bus Pull-Up Resistor Off-Chip
Maximum is determined by tR and tF
For Cb = 400pF, max is about 2~2.5k
For Cb = 40pF, max is about 15~20k
1
tSU:WP
WP Setup Time
Before START condition
600
ns
tHD:WP
WP Hold Time
After STOP condition
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VDD
window, to SCL rising edge crossing 30% of
VDD
tHD:DAT
Input Data Hold Time
tSU:STO
tHD:STO
Rpu
k
NOTES:
5. Typical values are for TA = 25°C and VDD = 3.3V.
6. LSB = (V(RW)127 – V(RW)0)/127. V(RW)127 and V(RW)0 are the voltage at pin RW for the DCP Register set to 7F hex and 00 hex respectively.
7. FSerror = (V(RW)127 – VDD)/LSB
8. ZSerror = V(RW)0/LSB
9. DNL = [(V(RW) i – V(RW) i-1)/LSB] – 1, for i from 1 to 127. i is the DCP Register setting.
10. INL = [V(RW) i – i * LSB – V(RW)0]/LSB, for I = 1 to 127.
6
 Max  V  RW i  – Min  V  RW i  
10
11. TC = ----------------------------------------------------------------------------------------------  ----------------- for i = 16 to 111, and T = -40°C to 85°C
V
 Max  V  RW i  + Min  V  RW i    2 125C
12. MI = (R0 – R127)/127. MI is minimum increment. R0 and R127 are the resistances between RH and RW with the DCP Register set to 00 hex and 7F
hex, respectively.
13. RDNL = (R i – R i-1)/MI – 1, for i from 1 to 111. i is the DCP Register setting.
14. RINL = [R i – (MI * i) – R127]/MI, for i from 1 to 111.
6
 Max  Ri  – Min  Ri  
1  10
15. TC = ---------------------------------------------------------------  ------------------- ; for i = 1 to 111, and T = -40°C to 85°C
R
 Max  Ri  + Min  Ri    2 125C
16. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a valid
STOP condition at the end of a Write sequence of a I2C serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
17. Parameter is not 100% tested.
18. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
5
FN8243.2
June 8, 2012
ISL96017
I2C Timing Diagram
tHIGH
tF
SCL
tLOW
tR
tSU:DAT
tSU:STA
tHD:STA
SDA
(INPUT TIMING)
tHD:DAT
tSU:STO
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
6
FN8243.2
June 8, 2012
ISL96017
Typical Performance Curves
0.15
140
T = 25°C
VDD = 3.6V
VDD = 3.0V
0.1
80
60
VDD = 3.0V
40
0
-0.05
-0.1
-0.15
20
-0.2
0
-0.25
0
20
40
60
80
100
TAP POSITION (DECIMAL)
120
140
T = 25°C
0
20
40
60
80
100
TAP POSITION (DECIMAL)
0.2
0.2
T = 25°C
RDNL (LSB)
0
-0.05
VDD = 3.6V
0.1
VDD = 3.6V
0.05
140
T = 25°C
0.15
0.15
0.1
120
FIGURE 3. DNL vs TAP POSITION FOR 10k (W)
FIGURE 2. WIPER RESISTANCE vs TAP POSITION FOR 10k (W)
0.05
0
-0.05
-0.1
-0.1
-0.15
-0.15
VDD = 3.0V
-0.2
0
20
40
60
80
100
TAP POSITION (DECIMAL)
120
-0.2
140
VDD = 3.0V
0
20
40
60
80
100
TAP POSITION (DECIMAL)
120
140
FIGURE 5. RDNL vs TAP POSITION FOR 10k (W)
FIGURE 4. INL vs TAP POSITION FOR 10k (W)
0.4
T = 25°C
0.3
VDD = 3.0V
0.2
RINL (LSB)
INL (LSB)
VDD = 3.6V
0.05
100
DNL (LSB)
WIPER RESISTANCE ()
120
0.1
0
-0.1
-0.2
-0.3
VDD = 3.6V
0
20
40
60
80
100
TAP POSITION (DECIMAL)
120
140
FIGURE 6. RINL vs TAP POSITION FOR 10kΩ (W)
7
FN8243.2
June 8, 2012
ISL96017
Principles of Operation
This device combines a DCP, 16kbit non-volatile memory, and an
I2C serial interface providing direct communication between a
host and the DCP and memory.
TABLE 1. ISL96017 MEMORY MAP
ADDRESS
DATA BITS
FUNCTION
7FFh
0 D6 D5 D4 D3 D2 D1 D0
IVR, DCP
7FEh
OV
0
0
0
0
DCP Description
7FDh
Reserved
The DCP has 10kor 50knominal total resistance and 128
taps. It is implemented with a combination of resistor elements
and CMOS switches. The physical ends of the DCP, the RH and RL
pins, are equivalent to the fixed terminals of a mechanical
potentiometer. The RW pin is connected to intermediate nodes,
and it is equivalent to the wiper terminal of a mechanical
potentiometer. The position of the wiper terminal within the DCP
is controlled by a 7-bit volatile DCP Register. When the DCP
Register contains all zeroes (00 hex, or “R0”), its wiper terminal,
RW, is closest to its RL terminal. When the DCP Register contains
all ones (7F hex, or “R127”), its wiper terminal is closest to its RH
terminal. As the value of the DCP Register increases from all
zeroes to all ones, the wiper moves monotonically from the
position closest to RL to the closest to RH. Therefore, the
resistance between RH and RW decreases monotonically from
R0 to R127, while the resistance between RW and RL increases
monotonically from R127 to R0.
7FCh
Reserved
While the device is being powered up, the DCP Register is reset
to 40 hex (64 decimal). Soon after the power supply voltage
becomes large enough for reliable non-volatile memory reading,
the device reads the value stored on the non-volatile Initial Value
Register (IVR) and loads it into the DCP Register.
Memory Description
This device contains 2048 non-volatile bytes organized in 128
pages of 16 bytes each. This allows writing 16 bytes on a single
I2C interface operation, followed by a single internal non-volatile
write cycle. The memory is accessed by I2C interface operations
with addresses 000 hex through 7FF hex.
Bytes at addresses 000 hex through 7FB hex are available to the
user as general purpose memory. The byte at address 7FF hex,
IVR, contains the initial value loaded at power-up into the volatile
DCP Register. The byte at address 7FE hex controls the access to
the DCP byte (See “Access to DCP Register and IVR”). Bytes at
addresses 7FC hex and 7FD hex, are reserved, which means that
they should not be written, and their value should be ignored if
they are read (see Table 1).
8
7FBh
0
0
0
Access Control
D7 D6 D5 D4 D3 D2 D1 D0 General Purpose Memory
000h
NOTE: OV = “Only Volatile”. All other bits in register 7FEh must be 0.
Access to DCP Register and IVR
The volatile DCP Register and the non-volatile (IVR) can be read
or written directly using the I2C serial interface, with Address
Byte 07FF hex.
The MSB of the byte at address 7FE hex is called “OnlyVolatile”
and controls the access to the DCP Register and IVR. This bit is
volatile and it’s reset to “0” at power up.
The Data Byte read from memory address 7FF hex, is from the
DCP register when the “OnlyVolatile” bit is “1”, and from the IVR
when this bit is “0”.
The Data Byte of a Write operation to memory address 7FF hex is
written only to the DCP Register when the “OnlyVolatile” bit is “1”,
and it’s written to both the DCP Register and the IVR when this
bit is “0”.
When writing to the “OnlyVolatile” bit at address 7FE hex, the
seven LSBs of the Data Byte must be all zeros.
Writing to address 7FE hex and 7FF hex can be done in two Write
operations, or one Write operation with two Data Bytes.
See next sections for interface protocol description.
FN8243.2
June 8, 2012
ISL96017
I2C Serial Interface
This device supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is a master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, this device operates as a slave device in all
applications. All communication over the I2C interface is
conducted by sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (See Figure 7). On power
up, the SDA pin is in the input mode. All I2C interface operations
must begin with a START condition, which is a HIGH to LOW
transition of SDA while SCL is HIGH. The device continuously
monitors the SDA and SCL lines for the START condition and does
not respond to any command until this condition is met (See
Figure 7). A START condition is ignored during the power up
sequence and during internal non-volatile write cycles. All I2C
interface operations must be terminated by a STOP condition,
which is a LOW to HIGH transition of SDA while SCL is HIGH (See
Figure 7). A STOP condition at the end of a Read operation, or at
the end of a Write operation to volatile bytes only places the
device in its standby mode. A STOP condition during a Write
operation to a non-volatile byte, initiates an internal non-volatile
write cycle. The device enters its standby state when the internal
non-volatile write cycle is completed.
An ACK, Acknowledge, is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data (See
Figure 8). This device responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and once
again after successful receipt of the Address Byte. This device
also responds with an ACK after receiving each Data Byte of a
Write operation. The master must respond with an ACK after
receiving each Data Byte of a read operation except the last one.
A valid Identification Byte contains 1010 as the four MSBs. The
following three bits are the MSBs of the memory address to be
accessed. The LSB of the Identification Byte is the Read/Write
bit. Its value is “1” for a Read operation, and “0” for a Write
operation (see Table 2). The complete memory address location
to be accessed is a 11-bit word, since the memory has 2048
bytes. The eight LSBs are in the Address Byte.
TABLE 2. IDENTIFICATION BYTE FORMAT
1
0
1
0
MSB
A10
A9
A8
R/Wb
LSB
SCL
SDA
STOP
START
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 7. VALID DATA CHANGES, START AND STOP CONDITIONS
9
FN8243.2
June 8, 2012
ISL96017
SCL FROM MASTER
1
8
SDA OUTPUT FROM
TRANSMITTER
9
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER
Write Operation
Data Protection
A Write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, one or more Data Bytes,
and a STOP condition (See Figure 9). After each of the bytes, this
device responds with an ACK. At this time, if the operation is only
writing to volatile registers, then the device enters its standby
state. If one or more Data Bytes are to be written to non-volatile
memory, the device begins its internal write cycle to non-volatile
memory. During this cycle, the device ignores transitions at the
SDA and SCL pins, and the SDA output is at a high impedance
state. When the internal non-volatile write cycle is completed, the
device enters its standby state.
The WP pin has to be at logic HIGH to perform any Write
operation to the device. When WP is active (LOW) the device
ignores Data Bytes of a Write operation, does not respond to
them with ACK, and instead, goes to its standby state waiting for
a new START condition.
The memory is organized as 128 pages of 16 bytes each. This
allows writing 16 bytes on a single I2C interface operation,
followed by a single internal non-volatile write cycle. The
addresses of bytes within a page share the same eight MSBs,
and differ on the four LSBs. For example, the first page is located
at addresses 0 hex through F hex, the second page is located at
addresses 10 hex through 1F hex, etc.
A Write operation with more than one Data Byte sends the first
Data Byte to the memory address indicated by the three address
bits of the Identification Byte plus the eight bits of the Address
Byte, the second Data Byte to the following address, etc.
A single Write operation has to stay within a page. If the Address
Byte corresponds to the lowest address of a page, then the Write
operation can have anywhere from 1 to 16 Data Bytes. If the
Address Byte corresponds to the highest address of a page, then
only one byte can be written with that Write operation.
See “Access to DCP Register and IVR” for additional information.
10
A valid Identification Byte, Address Byte, and total number of SCL
pulses act as a protection of both volatile and non-volatile
registers.
During a Write sequence, Data Bytes are loaded into an internal
shift register as they are received. If the address bits in the
Identification Byte plus the bits in the Address Byte are all ones,
the Data Byte is transferred to the DCP Register at the falling
edge of the SCL pulse that loads the last bit (LSB) of the Data
Byte.
The STOP condition acts as a protection of non-volatile memory.
Non-volatile internal write cycles are started by STOP conditions.
Read Operation
A Read operation consist of a three byte instruction followed by
one or more Data Bytes (See Figure 10). The master initiates the
operation issuing the following sequence: a START, the
Identification Byte with the R/W bit set to “0”, an Address Byte
which contains the LSBs of the memory address, a second
START, and a second Identification Byte with the same address
bits but with the R/W bit set to “1”. After each of the three bytes,
this device responds with an ACK. Then this device transmits
Data Bytes as long as the master responds with an ACK during
the SCL cycle following the eighth bit of each byte. The master
terminates the Read operation (issuing a STOP condition)
following the last bit of the last Data Byte. The Data Bytes are
from the memory location indicated by an internal pointer. This
pointer initial value is determined by the address bits in the
Identification Byte plus the bits in the Address Byte in the Read
operation instruction, and increments by one during
transmission of each Data Byte.
FN8243.2
June 8, 2012
ISL96017
WRITE
S
T
A
R
T
SIGNALS FROM
THE MASTER
SLAVE
ADDRESS
SIGNAL AT SDA
10 1 0
FIRST DATA BYTE
TO WRITE
ADDRESS
BYTE
S
T
O
P
LAST DATA BYTE
TO WRITE
0
SIGNALS FROM
THE SLAVE
A
C
K
A
C
K
A
C
K
A
C
K
FIGURE 9. WRITE SEQUENCE
SIGNALS
FROM THE
MASTER
S
T
A
R
T
SIGNAL AT SDA
SLAVE
ADDRESS WITH
R/Wb=0
1010
S
T
A
R
T
ADDRESS
BYTE
0
S
T
A
O
C
P
K
READ
SLAVE
ADDRESS
WITH
R/Wb=1
A
C
K
A
C
K
1
A
C
K
A
C
K
SIGNALS FROM
THE SLAVE
A
C
K
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 10. READ SEQUENCE
VDD = 3.3V VDD = 3.3V
0.1µF
VDD = 3.3V
Rpu
Rpu
WP
VCC
RH
0.1µF
SCL
RW
SDA
+
RL
ISL96017
VOUT
-
R1
R2
FIGURE 11. TYPICAL APPLICATION DIAGRAM FOR IMPLEMENTING ADJUSTABLE VOLTAGE REFERANCE
Applications Information
The typical application diagram is shown on Figure 11. For proper
operation adding 0.1µF decoupling ceramic capacitor to VDD is
recommended. The capacitor value may vary based on expected
noise frequency of the design.
11
FN8243.2
June 8, 2012
ISL96017
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
May 30, 2012
FN8243.2 Updated to new datasheet format.
Corrected note number references in “Electrical Specifications”. All note numbers were incremented by 1.
April 17, 2006
FN8243.1 Corrections made to “Ordering Information” on page 2
1. Part number's were swapped - ISL96017UIRT8Z* should be for 50k Rtotal, and ISL96017WIRT8Z* - for 10k
Rtotal.
Corrections made to Features bullet on page 1:
2. Endurance cycles updated from 100,000 to 1,000,000.
December 20, 2005 FN8243.0 Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL96017
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/sear
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN8243.2
June 8, 2012
ISL96017
Package Outline Drawing
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 2/10
( 2.30)
3.00
( 1.95)
A
B
3.00
( 8X 0.50)
6
PIN 1
INDEX AREA
(4X)
(1.50)
( 2.90 )
0.15
PIN 1
TOP VIEW
(6x 0.65)
( 8 X 0.30)
TYPICAL RECOMMENDED LAND PATTERN
SEE DETAIL "X"
2X 1.950
PIN #1
INDEX AREA
0.10 C
0.75 ±0.05
6X 0.65
C
0.08 C
1
SIDE VIEW
6
1.50 ±0.10
8
8X 0.30 ±0.05
8X 0.30 ± 0.10
2.30 ±0.10
C
4
0.10 M C A B
0 . 2 REF
5
0 . 02 NOM.
0 . 05 MAX.
DETAIL "X"
BOTTOM VIEW
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.20mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7.
13
Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
FN8243.2
June 8, 2012
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