Dual 800mA Low Quiescent Current 2.25MHz High Efficiency Synchronous Buck Regulator ISL78228 Features The ISL78228 is a high efficiency, dual synchronous step-down DC/DC regulator that can deliver up to 800mA continuous output current per channel. The supply voltage range of 2.75V to 5.5V allows for the use of a 3.3V or 5V input. The current mode control architecture enables very low duty cycle operation at high frequency with fast transient response and excellent loop stability. The ISL78228 operates above the AM radio band as well as the 2.25MHz switching frequency, allowing for the use of small, low cost inductors and capacitors. Each channel is optimized for generating an output voltage as low as 0.6V. • Internal Current Mode Compensation The ISL78228 has a user configurable mode of operation-forced PWM mode and PFM/PWM mode. The forced PWM mode operation reduces noise and RF interference while the PFM mode operation provides high efficiency by reducing switching losses at light loads. In PFM mode of operation, both channels draw a total quiescent current of only 30µA, hence enabling high light load efficiency in order to maximize battery life. The ISL78228 offers a 1ms Power-Good (PG) to monitor both outputs at power-up. When shutdown, ISL78228 discharges the outputs capacitor. Other features include internal digital soft-start, enable for power sequence, overcurrent protection, and thermal shutdown. The ISL78228 is offered in a 3mmx3mm 10 Ld DFN package with 1mm maximum height. The complete converter occupies less than 1.8cm2 area. • 100% Maximum Duty Cycle for Lowest Dropout • Selectable Forced PWM Mode and PFM Mode • External Synchronization up to 4MHz • Start-up with Pre-biased Output • Soft-Stop Output Discharge During Disabled • Internal Digital Soft-Start - 2ms • Power-Good (PG) Output with 1ms Delay • TS16949 Compliant • AEC - Q100 Tested • Pb-free (RoHS Compliant) Applications • DC/DC POL Modules • µC/µP, FPGA and DSP Power • Rear Camera Systems • Navigation Systems • Infotainment Systems The ISL78228 is both AEC - Q100 rated and fully TS16949 compliant. The ISL78228 is rated for the automotive temperature range (-40°C to +105°C). 100 EFFICIENCY (%) 90 80 2.5VOUT-PFM 1.8VOUT-PFM 70 2.5VOUT-PWM 60 1.8VOUT-PWM 50 VIN = 5V 40 0.0 0.1 0.2 0.3 0.4 0.5 OUTPUT LOAD (A) 0.6 0.7 0.8 FIGURE 1. EFFICIENCY CHARACTERISTICS CURVE May 2, 2011 FN7849.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL78228 Typical Application L1 2.2µH OUTPUT1 2.5V/800mA LX1 C2 10µF PGND INPUT 2.75V TO 5.5V R2 316k FB1 VIN R3 100k EN1 C1 10µF C3 10pF ISL78228 EN2 L2 2.2µH OUTPUT2 1.8V/800mA LX2 PG C4 10µF PGND SYNC R5 200k C5 10pF FB2 R6 100k PGND 2 FN7849.0 May 2, 2011 ISL78228 Pin Configuration ISL78228 (10 LD 3X3 DFN) TOP VIEW FB1 1 EN1 2 VIN 3 LX1 NC 10 FB2 9 EN2 8 PG 4 7 LX2 5 6 SYNC PAD Pin Descriptions DFN SYMBOL DESCRIPTION 1 FB1 The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance error amplifier. The output voltage is set by an external resistor divider connected to FB1. With a properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a typical application. In addition, the regulator power-good and undervoltage protection circuitry use FB1 to monitor the Channel 1 regulator output voltage. 2 EN1 Regulator Channel 1 enable pin. Enable the output, VOUT1, when driven to high. Shutdown the VOUT1 and discharge output capacitor when driven to low. Do not leave this pin floating. 3 VIN Input supply voltage. Connect 10µF ceramic capacitor to power ground. 4 LX1 Switching node connection for Channel 1. Connect to one terminal of inductor for VOUT1. 5 NC Recommended to connect this pin to the exposed pad. 6 SYNC Mode Selection pin. Connect to logic high or input voltage VIN for PFM mode; connect to logic low or ground for forced PWM mode. Connect to an external function generator for Synchronization, and negative edge trigger. Do not leave this pin floating. 7 LX2 Switching node connection for Channel 2. Connect to one terminal of inductor for VOUT2. 8 PG 1ms timer output. At power-up or EN_ HI, this output is a 1ms delayed Power-Good signal for both the VOUT1 and VOUT2 voltages. There is an internal 1MΩ pull-up resistor. 9 EN2 Regulator Channel 2 enable pin. Enable the output, VOUT2, when driven to high. Shutdown the VOUT2 and discharge output capacitor when driven to low. Do not leave this pin floating. 10 FB2 The feedback network of the Channel 2 regulator. FB2 is the negative input to the transconductance error amplifier. The output voltage is set by an external resistor divider connected to FB2. With a properly selected divider, the output voltage can be set to any voltage between the power-rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a typical application. In addition, the regulator power-good and undervoltage protection circuitry use FB2 to monitor the Channel 2 regulator output voltage. - PAD The exposed pad must be connected to PGND for proper electrical performance. Add as much vias as possible for optimal thermal performance. Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING ISL78228ARZ 8228 TEMP. RANGE (°C) -40 to +105 PACKAGE (Pb-Free) 10 Ld 3x3 DFN PKG. DWG. # L10.3x3C NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78228. For more information on MSL please see techbrief TB363. 3 FN7849.0 May 2, 2011 ISL78228 Absolute Maximum Ratings (Reference to GND) Thermal Information Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V (20ms) EN1, EN2, PG, SYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VIN + 0.3V LX1, LX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 6.5V LX1, LX2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V (100ns) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V (DC) to 7V (20ms) FB1, FB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 3kV Machine Model (Tested per JESD-A115-A) . . . . . . . . . . . . . . . . . . . 300V Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . 2kV Latch Up (Tested per JESD78C; Class II, Level A) . . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 10 Ld 3x3 DFN Package (Notes 4, 5) . . . . . . 49 4 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75V to 5.5V Load Current Range Per Channel . . . . . . . . . . . . . . . . . . . . . 0mA to 800mA Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions: TA = -40°C to +105°C, VIN = 2.75V to 5.5V, EN1 = EN2 = VIN, SYNC = 0V, L = 2.2µH, C1 = 10µF, C2 = C4 = 10µF, IOUT1 = IOUT2 = 0A to 800mA. (Typical values are at TA = +25°C, VIN = 3.6V). Boldface limits apply over the operating temperature range, -40°C to +105°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS 2.5 2.75 V INPUT SUPPLY VIN Undervoltage Lockout Threshold VUVLO Rising Falling Quiescent Supply Current IVIN Shut Down Supply Current ISD 2.1 2.4 V SYNC = VIN, EN1 = EN2 = VIN, no load at the output and no switches switching. VFB1 = VFB2 = 0.7V 30 50 µA SYNC = GND, EN1 = EN2 = VIN, FS = 2.25MHz, no load at the output 0.1 1 mA VIN = 5.5V, EN1 = EN2 = GND 6.5 12 µA 0.6 0.610 V OUTPUT REGULATION FB1, FB2 Regulation Voltage VFB_ FB1, FB2 Bias Current IFB_ Line Regulation 0.590 VFB = 0.55V 0.1 µA VIN = VO + 0.5V to 5.5V (minimal 2.75V, IOUT = 0A) 0.2 %/V 2 ms Soft-Start Ramp Time Cycle OVERCURRENT PROTECTION Peak Overcurrent Limit Peak SKIP Limit Ipk1 0.95 1.2 1.6 A Ipk2 0.95 1.2 1.6 A 180 250 360 mA 180 250 360 mA VIN = 5.5V, IO = 200mA 180 350 mΩ VIN = 2.75V, IO = 200mA 320 450 mΩ VIN = 5.5V, IO = 200mA 180 350 mΩ VIN = 2.75V, IO = 200mA 320 450 mΩ Iskip1 VIN = 3.6V Iskip2 LX1, LX2 P-Channel MOSFET ON-Resistance N-Channel MOSFET ON-Resistance 4 FN7849.0 May 2, 2011 ISL78228 Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions: TA = -40°C to +105°C, VIN = 2.75V to 5.5V, EN1 = EN2 = VIN, SYNC = 0V, L = 2.2µH, C1 = 10µF, C2 = C4 = 10µF, IOUT1 = IOUT2 = 0A to 800mA. (Typical values are at TA = +25°C, VIN = 3.6V). Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) LX_ Maximum Duty Cycle TYP MAX (Note 6) % 100 PWM Switching Frequency FS 1.8 Synchronization Range 2.25 2.7 LX Minimum On-Time SYNC = 0 (forced PWM mode) Soft Discharge Resistance RDIS_ EN = LOW 80 100 UNITS 2.7 MHz 4 MHz 100 ns 130 Ω 0.3 V PG Output Low Voltage Sinking 1mA, VFB = 0.5V PG Pull-up Resistor 1 MΩ Internal PGOOD Low Rising Threshold Percentage of nominal regulation voltage 88 92 96 % Internal PGOOD Low Falling Threshold Percentage of nominal regulation voltage 82 89 91 % Delay Time (Rising Edge) 1 Internal PGOOD Delay Time (Falling Edge) 1 ms 2 µs 0.4 V EN1, EN2, SYNC Logic Input Low Logic Input High 1.4 SYNC Logic Input Leakage Current ISYNC Enable Logic Input Leakage Current IEN_ Pulled up to 5.5V V 0.1 1 µA 0.1 1 µA Thermal Shutdown 150 °C Thermal Shutdown Hysteresis 25 °C NOTE: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 5 FN7849.0 May 2, 2011 ISL78228 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 2.75V to 5.5V, EN = VIN, L1 = L2 = 2.2µH, C1 = 10µF, C2 = C4 = 10µF, VOUT1 = 2.5V, VOUT2 = 1.8V, IOUT1 = IOUT2 = 100 100 90 90 80 EFFICIENCY (%) EFFICIENCY (%) 0A to 800mA. 2.5VOUT - PWM 70 1.5VOUT - PWM 1.2VOUT - PWM 60 1.8VOUT - PWM 50 40 0.0 0.1 0.2 0.3 0.4 0.5 OUTPUT LOAD (A) 0.6 0.7 40 0.8 1.8VOUT - PFM 1.5VOUT - PFM 100 90 90 80 2.5VOUT - PWM 70 3.3VOUT - PWM 60 1.5VOUT - PWM 1.2VOUT - PWM 1.8VOUT - PWM 0.0 0.1 0.2 0.3 0.4 0.5 OUTPUT LOAD (A) 0.6 0.7 70 1.5VOUT - PFM 60 1.22 OUTPUT VOLTAGE (V) 0.25 3.3VIN - PWM MODE 5VIN - PWM MODE 5VIN - PFM MODE 0.10 0.00 0.0 3.3VIN - PFM 0.1 0.2 0.3 0.4 0.5 OUTPUT LOAD (A) 0.6 0.7 0.8 FIGURE 6. POWER DISSIPATION vs LOAD 2.25MHz 1.8VOUT PWM 6 0.8 0.1 3.3VOUT - PFM 1.2VOUT - PFM 2.5VOUT - PFM 0.2 0.3 0.4 0.5 0.6 0.7 0.8 FIGURE 5. EFFICIENCY vs LOAD 2.25MHz 5VIN PFM 1.23 0.05 0.7 OUTPUT LOAD (A) 0.30 0.15 0.3 0.4 0.5 0.6 OUTPUT LOAD (A) 1.8VOUT - PFM 40 0.0 0.8 FIGURE 4. EFFICIENCY vs LOAD 2.25MHz 5VIN PWM 0.20 0.2 80 50 50 0.0 0.1 FIGURE 3. EFFICIENCY vs LOAD 2.25MHz 3.3VIN PFM EFFICIENCY (%) EFFICIENCY (%) 1.2VOUT - PFM 60 100 40 2.5VOUT - PFM 70 50 FIGURE 2. EFFICIENCY vs LOAD 2.25MHz 3.3VIN PWM POWER DISSIPATION (W) 80 5VIN PFM MODE 5VIN PWM MODE 1.21 1.20 1.19 1.18 1.17 0.0 3.3V VIN PWM 0.1 0.2 3.3V VIN PFM 0.3 0.4 0.5 OUTPUT LOAD (A) 0.6 0.7 0.8 FIGURE 7. VOUT REGULATION vs LOAD 2.25MHz 1.2VOUT PFM FN7849.0 May 2, 2011 ISL78228 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 2.75V to 5.5V, EN = VIN, L1 = L2 = 2.2µH, C1 = 10µF, C2 = C4 = 10µF, VOUT1 = 2.5V, VOUT2 = 1.8V, IOUT1 = IOUT2 = 0A to 800mA. (Continued) 1.84 5 VIN PFM MODE 1.55 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.56 3.3V VIN PFM 1.54 1.53 1.52 3.3V VIN PWM 1.51 5VIN PWM MODE 1.50 0.0 0.1 0.2 0.3 0.4 0.5 OUTPUT LOAD (A) 0.6 0.7 0.8 3.3V VIN PFM 1.81 5VIN PWM MODE 1.80 1.79 3.3V VIN PWM 0.1 0.2 OUTPUT VOLTAGE (V) 5V VIN PFM 0.7 0.8 2.53 3.3V VIN PFM 2.52 5V VIN PWM 3.3V VIN PWM 2.51 2.50 0.1 0.2 0.3 0.4 0.5 0.6 0.7 3.40 3.38 3.36 5V VIN PWM 3.34 3.32 3.30 0.0 0.8 5V VIN PFM 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 11. VOUT REGULATION vs LOAD 2.25MHz 3.3VOUT FIGURE 10. VOUT REGULATION vs LOAD 2.25MHz 2.5VOUT 1.83 1.83 1.82 0A LOAD PWM OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 0.6 3.42 2.54 1.81 1.80 1.79 0.4A LOAD PWM 1.78 1.77 2.0 0.3 0.4 0.5 OUTPUT LOAD (A) FIGURE 9. VOUT REGULATION vs LOAD 2.25MHz 1.8VOUT 2.55 OUTPUT VOLTAGE (V) 1.82 1.78 0.0 FIGURE 8. VOUT REGULATION vs LOAD 2.25MHz 1.5VOUT 2.49 0.0 5 VIN PFM MODE 1.83 0.8A LOAD PWM 2.5 3.0 3.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE (V) FIGURE 12. OUTPUT VOLTAGE REGULATION vs VIN 1.8VOUT PWM MODE 7 6.0 0A LOAD 1.82 0.4A LOAD 1.81 1.80 1.79 0.8A LOAD 1.78 1.77 2.0 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5 6.0 FIGURE 13. OUTPUT VOLTAGE REGULATION vs VIN 1.8VOUT PFM MODE FN7849.0 May 2, 2011 ISL78228 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 2.75V to 5.5V, EN = VIN, L1 = L2 = 2.2µH, C1 = 10µF, C2 = C4 = 10µF, VOUT1 = 2.5V, VOUT2 = 1.8V, IOUT1 = IOUT2 = 0A to 800mA. (Continued) 500ns/DIV 500ns/DIV LX1 2V/DIV LX2 2V/DIV VOUT1 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV IL1 0.5A/DIV IL2 0.5A/DIV FIGURE 14. STEADY STATE OPERATION AT NO LOAD CHANNEL 1 (PWM) 500ns/DIV LX1 2V/DIV FIGURE 15. STEADY STATE OPERATION AT NO LOAD CHANNEL 2 (PWM) 500ns/DIV VOUT1 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV IL1 0.5A/DIV FIGURE 16. STEADY STATE OPERATION AT NO LOAD CHANNEL 1 (PFM) IL2 0.5A/DIV FIGURE 17. STEADY STATE OPERATION AT NO LOAD CHANNEL 2 (PFM) LX2 2V/DIV LX1 2V/DIV VOUT2 RIPPLE 20mV/DIV VOUT1 RIPPLE 20mV/DIV 500ns/DIV IL1 0.5A/DIV FIGURE 18. STEADY STATE OPERATION WITH FULL LOAD CHANNEL 1 8 LX2 2V/DIV 500ns/DIV IL2 0.5A/DIV FIGURE 19. STEADY STATE OPERATION WITH FULL LOAD CHANNEL 2 FN7849.0 May 2, 2011 ISL78228 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 2.75V to 5.5V, EN = VIN, L1 = L2 = 2.2µH, C1 = 10µF, C2 = C4 = 10µF, VOUT1 = 2.5V, VOUT2 = 1.8V, IOUT1 = IOUT2 = 0A to 800mA. (Continued) VOUT1 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV IL1 0.5A/DIV IL2 0.5A/DIV 50µs/DIV 50µs/DIV FIGURE 20. LOAD TRANSIENT CHANNEL 1 (PWM) FIGURE 21. LOAD TRANSIENT CHANNEL 2 (PWM) LX2 2V/DIV LX1 2V/DIV VOUT1 RIPPLE 50mV/DIV 50µs/DIV VOUT2 RIPPLE 50mV/DIV 50µs/DIV IL2 0.5A/DIV IL1 0.5A/DIV FIGURE 22. LOAD TRANSIENT CHANNEL 1 (PFM) 50µs/DIV FIGURE 23. LOAD TRANSIENT CHANNEL 2 (PFM) 50µs/DIV EN2 2V/DIV VOUT2 0.5V/DIV EN1 2V/DIV VOUT1 1V/DIV IL2 0.5A/DIV IL1 0.5A/DIV PG 5V/DIV PG 5V/DIV FIGURE 24. SOFT-START WITH NO LOAD CHANNEL 1 (PWM) 9 FIGURE 25. SOFT-START WITH NO LOAD CHANNEL 2 (PWM) FN7849.0 May 2, 2011 ISL78228 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 2.75V to 5.5V, EN = VIN, L1 = L2 = 2.2µH, C1 = 10µF, C2 = C4 = 10µF, VOUT1 = 2.5V, VOUT2 = 1.8V, IOUT1 = IOUT2 = 0A to 800mA. (Continued) 50µs/DIV EN1 2V/DIV 50µs/DIV EN2 2V/DIV VOUT2 0.5V/DIV VOUT1 1V/DIV IL2 0.5A/DIV IL IL0.5A/DIV 0.5A/DIV PG 5V/DIV FIGURE 26. SOFT-START AT NO LOAD CHANNEL 1 (PFM) 50µs/DIV EN1 2V/DIV PG 5V/DIV FIGURE 27. SOFT-START AT NO LOAD CHANNEL 2 (PFM) 50µs/DIV EN2 2V/DIV VOUT1 1V/DIV VOUT2 0.5V/DIV IL1 0.5A/DIV IL2 0.5A/DIV PG 5V/DIV FIGURE 28. SOFT-START AT FULL LOAD CHANNEL 1 1ms/DIV PG 5V/DIV FIGURE 29. SOFT-START AT FULL LOAD CHANNEL 2 EN2 5V/DIV 1ms/DIV EN1 5V/DIV VOUT2 0.5V/DIV VOUT1 1V/DIV IL1 0.5A/DIV PG 5V/DIV FIGURE 30. SOFT-DISCHARGE SHUTDOWN CHANNEL 1 10 IL2 0.5A/DIV PG 5V/DIV FIGURE 31. SOFT-DISCHARGE SHUTDOWN CHANNEL 2 FN7849.0 May 2, 2011 ISL78228 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 2.75V to 5.5V, EN = VIN, L1 = L2 = 2.2µH, C1 = 10µF, C2 = C4 = 10µF, VOUT1 = 2.5V, VOUT2 = 1.8V, IOUT1 = IOUT2 = 0A to 800mA. (Continued) 200ns/DIV 200ns/DIV LX1 2V/DIV LX1 2V/DIV SYNCH 2V/DIV SYNCH 2V/DIV IL1 0.5A/DIV VOUT1 RIPPLE 20mV/DIV IL1 0.5A/DIV VOUT1 RIPPLE 20mV/DIV FIGURE 32. CH1 STEADY STATE OPERATION AT NO LOAD (PFM) WITH FREQUENCY = 4MHz FIGURE 33. CH1 STEADY STATE OPERATION AT FULL LOAD (PFM) WITH FREQUENCY = 4MHz 200ns/DIV 200ns/DIV LX2 2V/DIV LX2 2V/DIV SYNCH 2V/DIV SYNCH 2V/DIV IL2 0.5A/DIV VOUT2 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV IL2 0.5A/DIV FIGURE 34. CH2 STEADY STATE OPERATION AT NO LOAD (PFM) WITH FREQUENCY = 4MHz 100ns/DIV LX1 5V/DIV FIGURE 35. CH2 STEADY STATE OPERATION AT FULL LOAD (PFM) WITH FREQUENCY = 4MHz 100ns/DIV LX1 5V/DIV LX2 5V/DIV LX2 5V/DIV SYNCH 5V/DIV SYNCH 5V/DIV VOUT1 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV FIGURE 36. CH1 AND CH2 STEADY STATE OPERATION AT NO LOAD (PFM) WITH FREQUENCY = 4MHz 11 VOUT1 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV FIGURE 37. CH1 AND CH2 STEADY STATE OPERATION AT FULL LOAD (PFM) WITH FREQUENCY = 4MHz FN7849.0 May 2, 2011 ISL78228 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 2.75V to 5.5V, EN = VIN, L1 = L2 = 2.2µH, C1 = 10µF, C2 = C4 = 10µF, VOUT1 = 2.5V, VOUT2 = 1.8V, IOUT1 = IOUT2 = 0A to 800mA. (Continued) PHASE1 5V/DIV LX1 5V/DIV IL1 0.5A/DIV VOUT1 1V/DIV VOUT1 1V/DIV IL1 0.5A/DIV 500µs/DIV 10µs/DIV PG 5V/DIV FIGURE 38. OUTPUT SHORT CIRCUIT CHANNEL 1 10µs/DIV PG 5V/DIV FIGURE 39. OUTPUT SHORT CIRCUIT RECOVERY CHANNEL 1 500µs/DIV PHASE2 5V/DIV LX2 5V/DIV VOUT2 0.5V/DIV IL2 0.5A/DIV IL2 0.5A/DIV VOUT2 1V/DIV PG 5V/DIV PG 5V/DIV FIGURE 40. OUTPUT SHORT CIRCUIT CHANNEL 2 FIGURE 41. OUTPUT SHORT CIRCUIT RECOVERY CHANNEL 2 2.4 VIN 6V IOUT2 OC OUTPUT CURRENT (A) VIN 6V IOUT1 OC 2.0 1.6 1.2 0.8 VIN 3.5V IOUT2 OC VIN 3.5V IOUT1 OC 0.4 0 -50 -30 -10 10 20 50 70 90 110 TEMPERATURE (°C) FIGURE 42. OUTPUT CURRENT LIMIT vs TEMPERATURE 12 FN7849.0 May 2, 2011 ISL78228 Block Diagram SHUTDOWN EN1 SOFTSTART SHUTDOWN 27pF 200k VIN + BANDGAP 0.6V + EAMP PWM/PFM LOGIC CONTROLLER PROTECTION DRIVER + COMP - 3pF SLOPE COMP FB1 0.3V 1.6k VIN + 0.552V + OSCILLATOR + OCP - 0.59V + SKIP - 0.09V - ZERO-CROSS SENSING 1M PG PGND + CSA1 - + SCP - PG1 LX1 1ms DELAY SGND SYNC THERMAL SHUTDOWN BANDGAP 0.6V + EN2 27pF SOFTSTART SHUTDOWN 200k VIN + SHUTDOWN + COMP - EAMP - PWM/PFM LOGIC CONTROLLER PROTECTION DRIVER 3pF SLOPE COMP FB2 0.3V 1.6k SHUTDOWN LX2 PGND + SCP + + CSA2 + OCP - 0.59V + SKIP - 0.09V + 0.552V - PG2 ZERO-CROSS SENSING 13 FN7849.0 May 2, 2011 ISL78228 Theory of Operation The ISL78228 is a dual 800mA step-down switching regulator optimized for battery-powered or mobile applications. The regulator operates at 2.25MHz fixed switching frequency under heavy load conditions to allow small external inductor and capacitors to be used for minimal printed-circuit board (PCB) area. At light load, the regulator reduces the switching frequency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. The two channels are in-phase operation. The quiescent current when the outputs are not loaded is typically only 30µA. The supply current is typically only 6.5µA when the regulator is shut down. PWM Control Scheme Pulling the SYNC pin LOW (<0.4V) forces the converter into PWM mode in the next switching cycle regardless of output current. Each of the channels of the ISL78228 employ the current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting shown in the “Block Diagram” on page 13. The current loop consists of the oscillator, the PWM comparator COMP, current sensing circuit, and the slope compensation for the current loop stability. The current sensing circuit consists of the resistance of the P-Channel MOSFET when it is turned on and the current sense amplifier CSA1 (or CSA2 on Channel 2). The gain for the current sensing circuit is typically 0.285V/A. The control reference for the current loops comes from the error amplifier EAMP of the voltage loop. The PWM operation is initialized by the clock from the oscillator. The P-Channel MOSFET is turned on at the beginning of a PWM cycle and the current in the MOSFET starts to ramp-up. When the sum of the current amplifier CSA1 (or CSA2) and the compensation slope (0.33V/µs) reaches the control reference of the current loop, the PWM comparator COMP sends a signal to the PWM logic to turn off the P-MOSFET and to turn on the N-Channel MOSFET. The N-MOSFET stays on until the end of the PWM cycle. Figure 43 shows the typical operating waveforms during the PWM operation. The dotted lines illustrate the sum of the compensation ramp and the current-sense amplifier CSA-output. The output voltage is regulated by controlling the reference voltage to the current loop. The bandgap circuit outputs a 0.6V reference voltage to the voltage control loop. The feedback signal comes from the VFB pin. The soft-start block only affects the operation during the start-up and will be discussed separately shortly. The error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. The voltage loop is internally compensated with the 27pF and 200kΩ RC network. The maximum EAMP voltage output is precisely clamped to 0.8V. VEAMP VCSA DUTY CYCLE IL VOUT FIGURE 43. PWM OPERATION WAVEFORMS SKIP Mode Pulling the SYNC pin HIGH (>2.0V) forces the converter into PFM mode. The ISL78228 enters a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. Figure 44 illustrates the skip-mode operation. A zero-cross sensing circuit shown in the “Block Diagram” on page 13 monitors the N-MOSFET current for zero crossing. When 8 consecutive cycles of the N-MOSFET crossing zero are detected, the regulator enters the skip mode. During the 8 detecting cycles, the current in the inductor is allowed to become negative. The counter is reset to zero when the current in any cycle does not cross zero. Once the skip mode is entered, the pulse modulation starts being controlled by the SKIP comparator shown in the “Block Diagram” on page 13. Each pulse cycle is still synchronized by the PWM clock. The P-MOSFET is turned on at the clock and turned off when its current reaches the threshold of 250mA. As the average inductor current in each cycle is higher than the average current of the load, the output voltage rises cycle over cycle. When the output voltage reaches 1.5% above the nominal voltage, the PWM PFM CLOCK 8 CYCLES PFM CURRENT LIMIT IL LOAD CURRENT 0 NOMINAL +1.5% VOUT NOMINAL FIGURE 44. SKIP MODE OPERATION WAVEFORMS 14 FN7849.0 May 2, 2011 ISL78228 P-MOSFET is turned off immediately. Then the inductor current is fully discharged to zero and stays at zero. The output voltage reduces gradually due to the load current discharging the output capacitor. When the output voltage drops to the nominal voltage, the P-MOSFET will be turned on again at the clock, repeating the previous operations. The regulator resumes normal PWM mode operation when the output voltage drops 1.5% below the nominal voltage. Synchronization Control The frequency of operation can be synchronized up to 4MHz by an external signal applied to the SYNC pin. The falling edge on the SYNC triggered the rising edge of the PWM ON pulse. Overcurrent Protection CSA1 and CSA2 are used to monitor output 1 and output 2 channels respectively. The overcurrent protection is realized by monitoring the CSA_ output with the OCP threshold logic, as shown in “Block Diagram” on page 13. The current sensing circuit has a gain of 0.285V/A, from the P-MOSFET current to the CSA_output. When the CSA_ output reaches the threshold of 590mV, the OCP comparator is tripped to turn off the P-MOSFET immediately. The overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper MOSFETs. Upon detection of overcurrent condition, the upper MOSFET will be immediately turned off and will not be turned on again until the next switching cycle. PG The power-good signal, (PG) monitors both of the output channels. When powering up, the open-collector power-on-reset output holds low for about 1ms after VO1 and VO2 reaches the preset voltages. The PG output also serves as a 1ms delayed Power-Good signal. If one of the output is disabled, then PG only monitors the active channels. There is an internal 1MΩ pull-up resistor. TABLE 1. PG EN1 EN2 PG1 INTERNAL PG2 INTERNAL PG 0 0 X X 0 0 1 X 1 1 1 0 1 X 1 1 1 1 1 1 UVLO When the input voltage is below the undervoltage lock out (UVLO) threshold, the regulator is disabled. Enable The enable (EN1, EN2) input allows the user to control the turning on or off of the regulator for purposes such as power-up sequencing. The regulator is enabled, there is typically a 600µs delay for waking up the bandgap reference, then the soft start-up begins. 15 Soft-Start-Up The soft-start-up eliminates the in-rush current during the start-up. The soft-start block outputs a ramp reference to both the voltage loop and the current loop. The two ramps limit the inductor current rising speed as well as the output voltage speed so that the output voltage rises in a controlled fashion. At the very beginning of the start-up, the output voltage is less than 0.2V; hence the PWM operating frequency is 1/3 of the normal frequency. In force PWM mode, the IC will continue to start-up in PFM mode to support pre-biased load applications. Discharge Mode (Soft-Stop) When a transition to shutdown mode occurs, or the output undervoltage fault latch is set, the outputs discharge to GND through an internal 100Ω switch. Power MOSFETs The power MOSFETs are optimize for best efficiency. The ON-resistance for the P-MOSFET is typically 180mΩ and the ON-resistance for the N-MOSFET is typical 180mΩ. 100% Duty Cycle The ISL78228 features 100% duty cycle operation to maximize the battery life. When the battery voltage drops to a level that the ISL78228 can no longer maintain the regulation at the output, the regulator completely turns on the P-MOSFET. The maximum dropout voltage under the 100% duty-cycle operation is the product of the load current and the ON-resistance of the P-MOSFET. Thermal Shut-Down The ISL78228 has built-in thermal protection. When the internal temperature reaches +150°C, the regulator is completely shut down. As the temperature drops to +130°C, the ISL78228 resumes operation by stepping through a soft-start-up. Applications Information Output Inductor and Capacitor Selection To consider steady state and transient operation, ISL78228 typically uses a 2.2µH output inductor. Higher or lower inductor values can be used to optimize the total converter system performance. For example, for higher output voltage 3.3V applications, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. The inductor ripple current can be expressed as shown in Equation 1: VO ⎞ ⎛ V O • ⎜ 1 – --------⎟ V ⎝ IN⎠ ΔI = -----------------------------------L • fS (EQ. 1) The inductor’s saturation current rating needs be at least larger than the peak current. The ISL78228 protects the typical peak current 1.2A. The saturation current needs be over 1.8A for maximum output current application. FN7849.0 May 2, 2011 ISL78228 ISL78228 uses internal compensation network and the output capacitor value is dependent on the output voltage. The ceramic capacitor is recommended to be X5R or X7R. The recommended minimum output capacitor values are shown in Table 2 for the ISL78228. TABLE 2. OUTPUT CAPACITOR VALUE vs VOUT ISL78228 VOUT (V) COUT (µF) L (µH) 0.8 10 1.0~2.2 1.2 10 1.0~2.2 1.6 10 1.0~2.2 1.8 10 1.5~3.3 2.5 10 1.5~3.3 3.3 6.8 1.5~4.7 3.6 8.6 1.5~4.7 In Table 2, the minimum output capacitor value is given for different output voltages to make sure the whole converter system is stable. Output Voltage Selection The output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier. Refer to “Typical Application” on page 2. The output voltage programming resistor, R2 (or R5 in Channel 2), will depend on the desired output voltage of the regulator. The value for the feedback resistor is typically between 0Ω and 750kΩ, as shown in Equation 2. 16 Let R3 = 100kΩ, then R2 will be: ⎛ V OUT ⎞ R 2 = R 3 ⎜ ------------- – 1⎟ V ⎝ FB ⎠ (EQ. 2) If the output voltage desired is 0.6V, then R3 is left unpopulated and short R2. For faster response performance, add 47pF in parallel to R2. Input Capacitor Selection The main functions of the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. One 10µF X5R or X7R ceramic capacitor is a good starting point for the input capacitor selection for both channels. PCB Layout Recommendation The PCB layout is a very important converter design step to make sure the designed converter works well. For ISL78228, the power loop is composed of the output inductor (L’s), the output capacitor (COUT1 and COUT2), the LX’s pins, and the GND pin. It is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wide. The switching node of the converter, the LX_ pins, and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. The input capacitor should be placed as closely as possible to the VIN pin. The ground of input and output capacitors should be connected as closely as possible. The heat of the IC is mainly dissipated through the thermal pad. Maximizing the copper area connected to the thermal pad is preferable. In addition, a solid ground plane is helpful for better EMI performance. It is recommended to add at least 5 vias ground connection within the pad for the best thermal relief. FN7849.0 May 2, 2011 ISL78228 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION 5/2/11 FN7849.0 CHANGE Initial Release Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL78228 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN7849.0 May 2, 2011 ISL78228 Package Outline Drawing L10.3x3C 10 LEAD DUAL FLAT PACKAGE (DFN) Rev 2, 09/09 3.00 6 PIN #1 INDEX AREA A B 10 6 PIN 1 INDEX AREA 1 2.38 3.00 0.50 2 10 x 0.25 6 (4X) 0.10 C B 1.64 TOP VIEW 10x 0.40 BOTTOM VIEW 5 (4X) PACKAGE OUTLINE 0.10 M C B SEE DETAIL "X" (10 x 0.60) (10x 0.25) 0.90 MAX 0.10 C BASE PLANE 2.38 0.20 C SEATING PLANE 0.08 C SIDE VIEW (8x 0.50) 1.64 TYPICAL RECOMMENDED LAND PATTERN C 0.20 REF 5 0.05 DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 7. COMPLAINT TO JEDEC MO-229-WEED-3 except for E-PAD dimensions. 18 FN7849.0 May 2, 2011