DATASHEET

ISL90726
®
Single Volatile 128-Tap XDCP™
Data Sheet
August 26, 2008
FN8244.4
Digitally Controlled Potentiometer (XDCP)
Features
The Intersil ISL90726 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, and a control section. The wiper position is
controlled by an I2C interface.
• Volatile Solid-State Potentiometer
The potentiometer is implemented by a resistor array
composed of 127 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the SDA and SCL inputs.
• Low Tempco
- Rheostat - 45 ppm/°C typical
- Divider - 15 ppm/°C typical
Pinout
• Low Power CMOS
- Active Current, 200µA Max
- Standby Current, 500nA Max
ISL90726
(6 LD SC-70)
TOP VIEW
• I2C Serial Bus Interface
• DCP Terminal Voltage, 2.7V to 5.5V
• 128 Wiper Tap Points
- Wiper Resistance 70Ω typ at VCC = 3.3V
• Available RTOTAL Values = 50kΩ, 10kΩ
VDD 1
6 RL
• Power on Preset to Midscale
GND 2
5 RW
SCL 3
4 SDA
• Packaging
- 6 Ld SC-70
• Pb-Free (RoHS compliant)
Applications
• Mechanical Potentiometer Replacement
• Transducer Adjustment of Pressure, Temperature,
Position, Chemical, and Optical Sensors
• Laser Diode and LED Biasing
• LCD Brightness and Contrast Adjustment
• Gain Control and Offset Adjustment
• DDR3 Margining
Ordering Information
PART NUMBER
(Note)
PART MARKING
RTOTAL (kΩ)
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG. DWG. #
ISL90726WIE627Z-TK*
ANF
10
-40 to +85
6 Ld SC-70
P6.049
ISL90726UIE627Z-TK*
ANG
50
-40 to +85
6 Ld SC-70
P6.049
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL90726
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1
VDD
Supply Voltage
2
GND
Ground
3
SCL
Open drain Serial Clock input
4
SDA
Open drain Serial Data I/O
5
RW
Potentiometer Wiper Terminal
6
RL
Potentiometer End Terminal
Block Diagram
VDD
RH
SCL
SDA
I2C
INTERFACE
WIPER
REGISTER
RW
RL
GND
2
FN8244.4
August 26, 2008
ISL90726
Absolute Maximum Ratings
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any Digital Interface Pin
with Respect to VSS . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Voltage at any DCP Pin with
Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level B at +85°C
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
6 Ld SC-70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
590
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Power rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Analog Specifications
SYMBOL
RTOTAL
Over recommended operating conditions unless otherwise stated.
PARAMETER
RH to RL Resistance
MIN
(Note 12)
TEST CONDITIONS
W, U versions respectively
CH/CL/CW
ILkgDCP
Wiper Resistance
-20
VCC = 3.3V @ +25°C
Potentiometer Capacitance
Leakage on DCP Pins
MAX
(Note 12)
10, 50
RH to RL Resistance Tolerance
RW
TYP
(Note 2)
Voltage at pin from GND to VCC
UNIT
kΩ
+20
%
85
Ω
10/10/25
pF
0.1
1
µA
RESISTOR MODE
RINL
(Note 7)
Integral Non-linearity
RDNL (Note 6) Differential Non-linearity
ROFFSET
(Note 5)
TCR
(Notes 8, 9)
Offset
Resistance Temperature
Coefficient
DCP register set between 20 hex and 7F hex.
Monotonic over all tap positions (Note 3)
-2
±0.25
2
MI
(Note 4)
W option
-1
±0.1
1
MI
(Note 4)
U option
-1
±0.1
1
MI
(Note 4)
W option
0
1
3
MI
(Note 4)
U option
0
0.5
2
MI
(Note 4)
DCP register set between 20 hex
and 7F hex. Monotonic over all tap
positions (Note 3)
DCP register set between 20 hex and 7F hex
(Note 3)
±45
ppm/°C
Operating Specifications
SYMBOL
ICC1
ISB
IComLkg
tDCP (Note 9)
VCCRamp
PARAMETER
TEST CONDITIONS
MIN
(Note 12)
TYP
(Note 2)
MAX
(Note 12) UNIT
VCC Supply Current
(Volatile Write/Read)
fSCL = 400kHz; SDA = Open; (for I2C, Active,
Read and Volatile Write States only)
200
µA
VCC Current (Standby)
VCC = +5.5V, I2C Interface in Standby State
500
nA
Common-Mode Leakage
Voltage at SDA pin at GND or VCC
3
µA
DCP Wiper Response Time
SCL falling edge of last bit of DCP Data Byte to
wiper change
VCC Ramp Rate
3
500
0.2
ns
V/ms
FN8244.4
August 26, 2008
ISL90726
Operating Specifications
SYMBOL
tD
(Continued)
PARAMETER
Power-up Delay
TEST CONDITIONS
MIN
(Note 12)
TYP
(Note 2)
MAX
(Note 12) UNIT
3
ms
-0.3
0.3*VCC
V
VCC + 0.3
V
VCC above VPOR, to DCP Initial Value Register
recall completed, and I2C Interface in standby
state
SERIAL INTERFACE SPECIFICATIONS
VIL (Note 10)
SDA, and SCL Input Buffer LOW
Voltage
VIH (Note 10)
SDA, and SCL Input Buffer
HIGH Voltage
0.7*VCC
Hysteresis
SDA and SCL Input Buffer
Hysteresis
0.05*VCC
VOL
Cpin (Note 9)
fSCL
SDA Output Buffer LOW
Voltage, Sinking 4mA
0
V
0.4
V
SDA, and SCL Pin Capacitance
10
pF
SCL Frequency
400
kHz
50
ns
900
ns
tIN
Pulse Width Suppression Time
at SDA and SCL Inputs
tAA
SCL Falling Edge to SDA Output SCL falling edge crossing 30% of VCC, until
Data Valid
SDA exits the 30% to 70% of VCC window.
Any pulse narrower than the max spec is
suppressed.
tBUF
Time the Bus Must be Free
Before the Start of a New
Transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC during
the following START condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
crossing 70% of VCC.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC to
SCL falling edge crossing 70% of VCC.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VCC to
SDA entering the 30% to 70% of VCC window.
0
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VCC.
600
ns
tHD:STO
STOP Condition Hold Time for
Read, or Volatile Only Write
From SDA rising edge to SCL falling edge. Both
crossing 70% of VCC.
600
ns
Output Data Hold Time
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window.
0
ns
tR (Note 11)
SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1*Cb
250
ns
tF (Note 11)
SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1*Cb
250
ns
tDH
4
FN8244.4
August 26, 2008
ISL90726
Operating Specifications
SYMBOL
(Continued)
PARAMETER
MIN
(Note 12)
TEST CONDITIONS
Cb (Note 11)
Capacitive Loading of SDA or
SCL
Total on-chip and off-chip
10
Rpu (Note 11)
SDA and SCL Bus Pull-up
Resistor Off-chip
Maximum is determined by tR and tF.
For Cb = 400pF, max is about 2kΩ ~ 2.5kΩ.
For Cb = 40pF, max is about 15kΩ ~ 20kΩ.
1
TYP
(Note 2)
MAX
(Note 12) UNIT
400
pF
kΩ
NOTES:
2. Typical values are for TA = +25°C and 3.3V supply voltage.
3. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
4. MI = |R127 – R0|/127. R127 and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively.
ROFFSET = R0/MI, when measuring between RW and RL.
5. ROFFSET = R127/MI, when measuring between RW and RH.
6. RDNL = (Ri – Ri-1)/MI, for i = 32 to 127.
7. RINL = [Ri – (MI • i) – R0]/MI, for i = 32 to 127.
6
[ Max ( Ri ) – Min ( Ri ) ]
10
8. TC = --------------------------------------------------------------- × --------------------- for i = 32 to 127, T = -40°C to +85°C. Max( ) is the maximum value of the resistance and Min ( ) is
R
[ Max ( Ri ) + Min ( Ri ) ] ⁄ 2 +125°C the minimum value of the resistance over the temperature range.
9. This parameter is not 100% tested.
10. VIL = 0V, VIH = VCC.
11. These are I2C-specific parameters and are not directly tested. However, they are used in the device testing to validate specifications.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
SDA vs SCL Timing
tHIGH
tF
SCL
tLOW
tR
tSU:DAT
tSU:STA
tHD:DAT
tSU:STO
tHD:STA
SDA
(INPUT TIMING)
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
Principles of Operation
The ISL90726 is an integrated circuit incorporating one DCP
with its associated registers and an I2C serial interface
providing direct communication between a host and the
potentiometer.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of the DCP
are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the wiper
terminal of a mechanical potentiometer. The position of the
wiper terminal within the DCP is controlled by an 7-bit volatile
Wiper Register (WR). The DCP has its own WR. When the WR
of the DCP contains all zeroes (WR<6:0> = 00h), its wiper
5
terminal (RW) is closest to its “Low” terminal (RL). When the
WR of the DCP contains all ones (WR<6:0> = 7Fh), its wiper
terminal (RW) is closest to its “High” terminal (RH). As the
value of the WR increases from all zeroes (00h) to all ones
(127 decimal), the wiper moves monotonically from the
position closest to RL to the position closest to RH. RH is not
connected to a device pin. The net effect is the resistance
between RW and RL increases monotonically.
While the ISL90726 is being powered up, the WR is reset to
40h (64 decimal), which locates RW roughly at the center
between RL and RH.
The WR and IVR can be read or written directly using the
I2C serial interface as described in the following sections.
FN8244.4
August 26, 2008
ISL90726
I2C Serial Interface
The ISL90726 supports bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL90726
operates as slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 1). On power-up of the ISL90726, the SDA pin is in
the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL90726 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 1). A START condition is ignored during the power-up
sequence and during internal non-volatile write cycles.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 1).
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 2).
The ISL90726 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL90726 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
A valid Identification Byte contains 0101110 as the seven
MSBs. The LSB in the Read/Write bit. Its value is “1” for a
Read operation, and “0” for a Write operation (see Table 1).
TABLE 1. IDENTIFICATION BYTE FORMAT
0
1
0
1
1
(MSB)
1
0
R/W
(LSB)
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL90726 responds with an ACK. At this time, the device
enters its standby state (see Figure 3).
Data Protection
A valid Identification Byte, Address Byte, and total number of
SCL pulses act as a protection of both volatile and nonvolatile registers. During a Write sequence, the Data Byte is
loaded into an internal shift register as it is received. If the
Address Byte is 0h, the Data Byte is transferred to the Wiper
Register (WR) at the falling edge of the SCL pulse that loads
the last bit (LSB) of the Data Byte. If an address other than
00h, or an invalid slave address is sent, then the device will
respond with no ACK.
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (see Figure 4). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL90726 responds with an ACK. Then the ISL90726
transmits the Data Byte as long as the master responds with
an ACK during the SCL cycle following the eighth bit of each
byte. The master then terminates the read operation (issuing
a STOP condition) following the last bit of the Data Byte
(see Figure 4).
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 1. VALID DATA CHANGES, START, AND STOP CONDITIONS
6
FN8244.4
August 26, 2008
ISL90726
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
S
T
A
R
T
IDENTIFICATION
BYTE
ADDRESS
BYTE
0 1 0 1 1 1 0 0
0 0 0 0 0 0 0 0
SIGNALS FROM
THE ISL23711
A
C
K
A
C
K
A
C
K
S
T
O
P
DATA
BYTE
FIGURE 3. BYTE WRITE SEQUENCE
SIGNALS
FROM THE
MASTER
S
T
A
R
T
SIGNAL AT SDA
IDENTIFICATION
BYTE WITH
R/W = 0
ADDRESS
BYTE
0 1 0 1 1 1 0 0
SIGNALS FROM
THE SLAVE
S
T
A IDENTIFICATION
R
BYTE WITH
T
R/W = 1
0 1 0 1 1 1 0 1
0 0 0 0 0 0 0 0
A
C
K
S
T
O
P
A
C
K
A
C
K
DATA BYTE
FIGURE 4. READ SEQUENCE
7
FN8244.4
August 26, 2008
ISL90726
Small Outline Transistor Plastic Packages (SC70-6)
0.20 (0.008) M
VIEW C
C
P6.049
CL
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
e
b
6
INCHES
5
4
CL
CL
E1
E
1
2
3
e1
A
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.031
0.043
0.80
1.10
-
A1
0.000
0.004
0.00
0.10
-
A2
0.031
0.039
0.00
1.00
-
b
0.006
0.012
0.15
0.30
b1
0.006
0.010
0.15
0.25
c
0.003
0.009
0.08
0.22
6
D
c1
0.003
0.009
0.08
0.20
6
CL
D
0.073
0.085
1.85
2.15
3
E
0.071
0.094
1.80
2.40
-
E1
0.045
0.053
1.15
1.35
3
C
A2
SEATING
PLANE
A1
-C-
e
e1
L
0.10 (0.004) C
WITH
b
PLATING
b1
0.0256 Ref
0.0512 Ref
0.010
c1
0.018
-
1.30 Ref
0.26
-
0.46
L1
0.017 Ref.
0.420 Ref.
L2
0.006 BSC
0.15 BSC
N
c
0.65 Ref
6
4
6
5
R
0.004
-
0.10
-
R1
0.004
0.010
0.15
0.25
α
0o
8o
0o
8o
Rev. 2 9/03
BASE METAL
NOTES:
1. Dimensioning and tolerance per ASME Y14.5M-1994.
4X θ1
2. Package conforms to EIAJ SC70 and JEDEC MO203AB.
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
R
GAUGE PLANE
SEATING
PLANE
L
C
L1
4X θ1
α
L2
5. “N” is the number of terminal positions.
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
VIEW C
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
FN8244.4
August 26, 2008
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