Neotek NT7108

NEOTEC SEMICONDUCTOR LTD.
NT7108
NT7108
Copyright: NEOTEC (C) 2002
http://www.neotec.com.tw
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any
means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of NEOTEC
12/18/2002
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NEOTEC SEMICONDUCTOR LTD.
NT7108
INTRODUCTION
The NT7108 is a LCD driver LSI with 64 channel outputs for dot matrix liquid crystal graphic
display systems. This device consists of the display RAM, 64 bits data latch, 64 bit drivers and
decoder logic. It has the internal display RAM for storing the display data transferred from a 8 bit
micro controller and generates the dot matrix liquid crystal driving signals corresponding to stored
data. The NT7108 composed of the liquid crystal display system in combination with the NT7107.
FEATURES
．Dot matrix LCD segment driver with 64 channel output
．Input and output signal
-Input: 8bit parallel display data control signal from MPU divided bias voltage (V0R, V0L,
V2R, V2L, V3R, V3L, V5R, V5L)
-Output: 64 channels for LCD driving.
．Display data is stored in display data RAM from MPU.
．Interface RAM
-Capacity: 512 bytes (4096 bits)
-RAM bit data: RAM bit data = 1: On
RAM bit data = 0: Off
．Applicable LCD duty:1/32-1/64
．LCD driving voltage: 8V-17V(VDD-VEE)
．Power supply voltage:+2.7~+5.5V
．Interface
Driver
COMMON
Other NT7107
．High voltage CMOS process.
．100QFP or bare chip available.
12/18/2002
SEGMENT
Other NT7108
Controller
MPU
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NEOTEC SEMICONDUCTOR LTD.
NT7108
Input
Register
Output
Register
8
8
Display
On/Off
I/O Buffer
DB<0:7>
CLK2
CLK1
BLOCK DIAGRAM
CS1B
CS2B
CS3
R/W
RS
E
RSTB
Instruction
Decoder
Busy
1
6
3
Y-Decoder
ADC
6
Y-Counter
X-Decoder
FRM
6
Z-Decoder
CL
Display Start Line Register
64
64
8
Display Data RAM
512 X 8 = 4096 bits
8
Page Selector
6
64
Data Latch
64
V0L
V2L
V3L
V5L
M
S2
S1
LCD Driver
S64
S63
12/18/2002
V0R
V2R
V3R
V5R
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NEOTEC SEMICONDUCTOR LTD.
NT7108
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DB1
DB0
VSS
V3L
V2L
V5L
V0L
VEE1
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
ADC
M
VDD
V3R
V2R
V5R
V0R
VEE2
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
NT7108
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
FRM
E
CLK1
CLK2
CL
RS
R/W
RSTB
CS1B
CS2B
CS3
NC
NC
NC
DB7
DB6
DB5
DB4
DB3
DB2
100 QFP
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NEOTEC SEMICONDUCTOR LTD.
NT7108
PIN DESCRIPTION
Table 1. Pin Description
Pin Number
QFP
Symbol
3
78
73,8
VDD
VSS
VEE1,2
74,7
76,5
77,4
75,6
I/O
Power
V0L,V0R,
V2L,V2R,
Power
V3L,V3R,
V5L,V5R
92
91
90
2
CS1B
CS2B
CS3
M
Input
1
ADC
Input
100
FRM
Input
99
E
Input
98
97
CLK1
CLK2
Input
96
CL
Input
95
RS
Input
94
RW
Input
79-86
DB0~
DB7
Input/
Output
12/18/2002
Input
Description
For internal logic circuit (+2.7~+5.5V)
GND (0V)
For LCD driver circuit
VSS = 0V, VDD = +5V±10%, VDD - VEE = 8V - 17V
The same voltage should be connected to VEE1 and VEE2.
Bias supply voltage terminals to drive LCD.
Select Level
Non-Select Level
V0L (R), V5L (R) V2L (R), V3L (R)
The same voltage should connect V0L and V0R (V2L & V2R,
V3L & V3R, V5L & V5R).
Chip selection
In order to interface data for input or output, the terminals have
to be CS1B=L, CS2B=L, and CS3=H.
Alternating signal input for LCD driving.
Address control signal to determine the relation between Y
address of display RAM and terminals from which the data is
output.
ADC=H Y0:S1-Y63:S64
ADC=L Y0:S64-Y63:S1
Synchronous control signal.
Presets the 6-bit Z counter and synchronizes the common signal
with the frame signal when the frame signal becomes high.
Enable signal.
Write mode (R/W=L) data of DB<0:7> is latched at the
falling edge of E
Read mode (R/W=H) DB<0:7> appears the reading data
while E is at high level.
2 phase clock signal for internal operation
Used to execute operations for input/output of display RAM data
and others.
Display synchronous signal.
Display data is latched at rising time of the CL signal and
increments the Z-address counter at the CL falling time.
Data or Instruction.
RS=H DB<0:7>:Display RAM data
RS=L DB<0:7>:Instruction data
Read or Write.
R/W=H Data appears at DB<0:7> and can be read by the CPU
while E=H, CS1B=L, CS2B-L and CS3=H.
R/W=L Display data DB<0:7> can be written at falling of E
when CS1B=L, CS2B=L and CS3=H.
Data bus.
Three state I/O common terminal.
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NEOTEC SEMICONDUCTOR LTD.
Pin Number
QFP
72-9
Symbol
S1-S64
93
RSTB
87
88
89
NC
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I/O
NT7108
Description
LCD segment driver output.
Display RAM data 1:On
Display RAM data 0:Off (relation of display RAM data & M)
M
Data
Output Level
Output
L
V2
L
H
V0
L
V3
H
H
V5
Reset signal.
When RSTB=L,
-ON/OFF register 0 set (display off)
Input
-Display start line register 0 set (display line from 0)
After releasing reset, this condition can be changed only by
instruction.
No connection. (Open)
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NEOTEC SEMICONDUCTOR LTD.
NT7108
OPERATING PRINCIPLES AND METHODS
I/O BUFFER
Input buffer controls the status between the enable and disable of chip. Unless the CS1B to CS3 is in
active mode, Input or output of data and instruction does not execute. Therefore internal state is not
change. But RSTB and ADC can operate regardless CS1B-CS3.
INPUT REGISTER
Input register is provided to interface with MPU, which is different operating frequency. Input
register stores the data temporarily before writing it into display RAM. When CS1B to CS3 are in
the active mode, R/W and RS select the input register. The data from MPU is written into input
register, then into display RAM. Data latched for falling of the E signal and write automatically into
the display data RAM by internal operation.
OUTPUT REGISTER
Output register stores the data temporarily from display data RAM when CS1B, CS2B and CS3 are
in active mode and R/W and RS=H, stored data in display data RAM is latched in output register.
When CS1B to CS3 is in active mode and R/W=H, RS=L, status data (busy check) can read out. To
read the contents of display data RAM, twice access of read instruction is needed. In first access,
data in display data RAM is latched into output register. In second access, MPU can read data which
is latched. That is, to read the data in display data RAM, it needs dummy read. But status read is not
needed dummy read.
RS
L
H
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R/W
L
H
L
H
Function
Instruction
Status read (busy check)
Data write (from input register to display data RAM)
Data read (from display data RAM to output register)
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NEOTEC SEMICONDUCTOR LTD.
NT7108
RESET
The system can be initialized by setting RSTB terminal at low level when turning power on,
receiving instruction from MPU.
When RSTB becomes low, following procedure is occurred.
‧Display off
‧Display start line register become set by 0. (Z-address 0)
While RSTB is low, No instruction except status read can be accepted. Therefore, execute other
instructions after making sure that DB4=0 (clear RSTB) and DB7=0 (ready) by status read
instruction. The Conditions of power supply at initial power up are shown in table 2.
Table 2. Power Supply Initial Conditions
Item
Symbol Min. Typ. Max.
Reset time
tRS
1.0
Rise time
tR
200
VDD
4.5V tRS
Unit
μs
ns
tR
0.7VDD
0.3VDD
RSTB
Busy Flag
Busy Flag indicates the NT7108 is operating or no operating. When busy flag is high, NT7108 is in
internal operating. When busy flag is low, NT7108 can accept the data or instruction. DB7 indicates
busy flag of the NT7108.
RS
R/W
E
Address
N
N+1
Output register
DB0-DB7
Busy
check
Write
address N
Busy
check
Read data
(dummy)
N+2
Data at address N Data at address N+1
Busy Read data Busy Data read
address
check at address check
N
N+1
Busy Check
E
Busy Flag
T Busy
1/fCLK ≦ T Busy≦ 3/ fCLK
fCLK is CLK1, CLK2 frequency
Busy Check
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NEOTEC SEMICONDUCTOR LTD.
NT7108
Display ON / OFF Flip-Flop
The display on/off flip-flop makes on/off the liquid crystal display. When flip-flop is reset (logical
low), selective voltage or non-selective voltage appears on segment output terminals. When flip-flop
is set (logic high), non-selective voltage appears on segment output terminals regardless of display
RAM data. The display on/off flip-flop can changes status by instruction. The display data at all
segments disappear while RSTB is low. The status of the flip-flop is output to DB5 by status read
instruction. The display on/off flip-flop synchronized by CL signal.
X Page Register
X page register designates pages of the internal display data RAM. Count function is not available.
An address is set by instruction.
Y Address Counter
An Address is set by instruction and is increased by 1 automatically by R/W operations of display
data. The Y address counter loops the values of 0 to 63 to count.
Display Data RAM
Display data RAM stores a display data for liquid crystal display. To indicate on state dot matrix of
liquid crystal display, write data 1. The other way, off state, writes 0.
Display data RAM address and segment output can be controlled by ADC signal.
‧ADC=H Y-address 0:S1-Y address 63:S64
‧ADC=L Y-address 0:S64-Y address 63:S1
ADC terminal connects the VDD or Vss.
Display Start Line Register
The display start line register indicates of display data RAM to display top line of liquid crystal
display. Bit data (DB<0.5>) of the display start line set instruction is latched in display start line
register. Latched data is transferred to the Z address counter while FRM is high, presetting the Z
address counter. It is used for scrolling of the liquid crystal display screen.
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NEOTEC SEMICONDUCTOR LTD.
NT7108
DISPLAY CONTROL INSTRUCTION
The display control instructions control the internal state of the NT7108. Instruction is received from
MPU to NT7108 for the display control. The following table shows various instructions.
Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Display on/off
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
H
Status read
L
H
Busy
L
Write display
data
H
L
Read display
data
H
H
Set address
(Y address)
Set page
(X address)
Display
Start line
(Z address)
12/18/2002
Function
Controls the display on or off.
Internal status and display RAM
H
H
H
H
H
L/H
data is not affected.
L:OFF, H:ON
Sets the Y address in the Y
Y address (0-63)
address counter.
Sets the X address at the X
H
H
H
Page (0-7)
address register.
Indicates the display data
RAM displayed at the top of the
Display start line (0-63)
screen.
Read status.
BUSY L: Ready
H: In operation
On/
Reset L
L
L
L ON/OFF L: Display ON
Off
H: Display OFF
RESET L: Normal
H: Reset
Writes data (DB0: 7) into display
data RAM. After writing
Write data
instruction, Y address is
increased by 1 automatically.
Reads data (DB0: 7) from display
Read data
data RAM to the data bus.
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NEOTEC SEMICONDUCTOR LTD.
NT7108
DISPLAY ON/OFF
RS
0
R/W
0
DB7
0
DB6
0
DB5
1
DB4
1
DB3
1
DB2
1
DB1
1
DB0
D
The display data appears when D is 1 and disappears when D is 0. Though the data is not on the
screen with D=0, it remains in the display data RAM. Therefore, you can make it appear by
changing D=0 into D=1.
SET ADDRESS (Y ADDRESS)
RS
0
R/W
0
DB7
0
DB6
1
DB5
AC5
DB4
AC4
DB3
AC3
DB2
AC2
DB1
AC1
DB0
AC0
Y address (AC0-AC5) of the display data RAM is set in the Y address counter. An address is set by
instruction and increased by 1 automatically by read or write operations of display data.
SET PAGE (X ADDRESS)
RS
0
R/W
0
DB7
1
DB6
0
DB5
1
DB4
1
DB3
1
DB2
AC2
DB1
AC1
DB0
AC0
X address (AC0-AC2) of the display data RAM is set in the X address register. Writing or reading to
or from MPU is executed in this specified page until the next page is set.
DISPLAY START LINE (Z ADDRESS)
RS
0
R/W
0
DB7
1
DB6
1
DB5
AC5
DB4
AC4
DB3
AC3
DB2
AC2
DB1
AC1
DB0
AC0
Z address (AC0-AC5) of the display data RAM is set in the display start line register and displayed
at the top of the screen. When the display duty cycle is 1/64 or others (1/32-1/64), the data of total
line number of LCD screen, from the line specified by display start line instruction, is displayed.
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NEOTEC SEMICONDUCTOR LTD.
NT7108
STATUS READ
RS
0
R/W
1
DB7
BUSY
DB6
0
DB5
DB4
ON/OFF RESET
DB3
0
DB2
0
DB1
0
DB0
0
‧BUSY
When BUSY is 1, the Chip is executing internal operation and no instructions are accepted.
When BUSY is 0, the Chip is ready to accept any instructions.
‧ON/OFF
When ON/OFF is 1, the display is OFF.
When ON/OFF is 0, the display is ON.
‧RESET
When RESET is 1, the system is being initialized.
In this condition, no instructions except status read can be accepted.
When RESET is 0, initializing has finished and the system is in usual operation condition.
WRITE DISPLAY DATA
RS
1
R/W
0
DB7
D7
DB6
D6
DB5
D5
DB4
D4
DB3
D3
DB2
D2
DB1
D1
DB0
D0
Writes data (D0-D7) into the display data RAM. After writing instruction, Y address is increased by
1automatically.
READ DISPLAY DATA
RS
1
R/W
1
DB7
D7
DB6
D6
DB5
D5
DB4
D4
DB3
D3
DB2
D2
DB1
D1
DB0
D0
Reads data (D0-D7) from the display data RAM. After reading instruction, Y address is increased by
1 automatically.
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NEOTEC SEMICONDUCTOR LTD.
NT7108
MAXIMUM ABSOLUTE LIMIT
Characteristic
Operating voltage
Supply voltage
Driver supply voltage
Symbol
VDD
VEE
VB
VLCD
TOPR
TSTG
Value
-0.3 to +7.0
VDD-19.0 to VDD +0.3
-0.3 to VDD +0.3
VEE-0.3 to VDD +0.3
-30 to +85
-55 to +125
Unit
V
Note
(1)
(4)
(1),(3)
(2)
Operating temperature
℃
Storage temperature
NOTES:
1. Based on Vss=0V
2. Applies the same supply voltage to VEE1 and VEE2. VLCD=VDD-VEE.
3. Applies to M, FRM, CL, RSTB, ADC, CLK1, CLK2, CS1B, CS2B, CS3, E, R/W, RS and
DB0-DB7.
4. Applies to V0L(R), V2L(R), V3L(R) and V5L(R).
Voltage level: VDD≧V0L=V0R≧V2L=V2R≧V3L=V3R≧V5L=V5R≧VEE.
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NEOTEC SEMICONDUCTOR LTD.
NT7108
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (VDD=5.0V, Vss=0V, VDD-VEE=8 to 17V, Ta=-30℃ to +85℃)
Characteristic
Symbol
Condition
Min. Typ. Max. Unit Note
2.7
5.5
Operating Voltage
VDD
0.7VDD VDD
(1)
Input high Voltage
VIH1
2.0
VDD
(2)
VIH2
0
- 0.3VDD V
(1)
Input low Voltage
VIL1
0
0.8
(2)
VIL2
Output high voltage
VOH
IOH=-200μA
2.4
(3)
IOL=1.6mA
0.4
(3)
Output low voltage
VOL
VIN=VSS-VDD
-1.0
1.0
(4)
Input leakage current
ILKG
V
IN
=V
SS
-V
DD
Three-state(off) input
ITSL
-5.0
5.0
(5)
current
VIN=VEE-VDD
Driver input leakage
IDIL
μA (6)
-2.0
2.0
current
During display
100
(7)
Operating current
IDD1
During access
IDD2
500
(7)
Access cycle = 1 MHz
VDD-VEE=15V
On resistance
RON
kΩ (8)
7.5
ILOAD= ±0.1mA
NOTES:
1. CL, FRM, M RSTB, CLK1, CLK2
2. CS1B, CS2B, CS3, E, R/W, RS, DB0 - DB7
3. DB0 - DB7
4. Except DB0 -DB7
5. DB0 - DB7 at high impedance
6. V0L(R), V2L(R), V3L(R), V5L(R)
7. 1/64 duty, fCLK=250kHz, frame frequency=70HZ, output: no load
8. VDD - VEE =15.5V
V0L(R)>V2L(R)=VDD-2/7(VDD-VEE)>V3L(R)=VEE+2/7(VDD-VEE)>V5L(R)
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NEOTEC SEMICONDUCTOR LTD.
NT7108
AC CHARACTERISTICS (VDD=+5V±10%, Vss=0V, Ta=-30℃
℃ to +85℃
℃)
Clock Timing
Characteristic
Symbol
Min
Type
Max
CLK1, CLK2 cycle time
tCY
2.5
-
20
CLK1 "low" level width
CLK2 "low" level width
CLK1 "high" level width
CLK2 "high" level width
CLK1-CLK2 phase difference
CLK2-CLK1 phase difference
CLK1, CLK2 rise time
CLK1, CLK2 fall time
tWL1
tWL2
tWH1
tWH2
tD12
tD21
tR
tF
625
625
1875
1875
625
625
-
-
150
150
Unit
μs
ns
tCY
tF
CLK1
tWH1
tR
0.7VDD
0.3VDD
tD12
tD21
tWL1
CLK2
0.7VDD
0.3VDD
tF
tWH2
tWL2
tR
tCY
Figure 1. External Clock Waveform
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NEOTEC SEMICONDUCTOR LTD.
Display Control Timing
Characteristic
FRM delay time
M delay time
CL "low" level width
CL "high" level width
NT7108
Symbol
tDF
tDM
tWL
tWH
Min
-2
-2
35
35
Type
-
Max
2
2
-
Unit
μs
tWL
CL
0.7VDD
0.3VDD
tWH
tDF
FRM
0.7VDD
0.3VDD
tDF
tDM
M
Figure 2. Display Control Waveform
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NEOTEC SEMICONDUCTOR LTD.
MPU Interface
Characteristic
E cycle
E high level width
E low level width
E rise time
E fall time
Address set-up time
Address hold time
Data set-up time
Data delay time
Data hold time (write)
Data hold time (read)
NT7108
Symbol
tC
tWH
tWL
tR
tF
tASU
tAH
tDSU
tD
tDHW
tDHR
Min
1000
450
450
140
10
200
10
20
Type
-
Max
25
25
320
-
Unit
ns
tC
0.7V
E 0.3VDD
DD
tWL
0.7VDD
0.3VDD
R/W
CS1B, CS2B,
CS3, RS
tWH
tR
tASU
tF
tAH
tASU
0.7VDD
0.3VDD
tDSU
tDHW
0.7VDD
0.3VDD
DB0-DB7
Figure 3. MPU Write Timing
tC
0.7V
E 0.3VDD
DD
0.7VDD
0.3VDD
R/W
CS1B, CS2B,
CS3, RS
DB0-DB7
tWL
0.7VDD
0.3VDD
tWH
tR
tF
tASU
tAH
tASU
tAH
tD
tDHR
0.7VDD
0.3VDD
Figure 4. MPU Read Timing
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NEOTEC SEMICONDUCTOR LTD.
NT7108
TIMING DIAGRAM (1/64 DUTY)
CLK1
CLK2
1
2
INPUT
64
3
1
48
2
3
49
64
1
2
3
64
1
CL
FRM
1 Frame
1 Frame
M
V0
V1
COMMON
C1 V4
V4
V5
V1
V1
C2 V4
V4
V5
V0
V5
V0
V1
V4
V0
V1
C64 V4
V5
V1
V4
SEGMENT
V0
V2
S1 V3
V3
V2
V5
V0
S64 V3
V2
V3
V2
V5
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NEOTEC SEMICONDUCTOR LTD.
NT7108
APPLICATION CIRCUIT
15
VEE
V0R/L
V2R/L
V3R/L
V5R/L
S1~S64
CS3
NT7108 CS2B
CS1B
DB0~DB7
RSTB
E
R/W
RS
VSS
VDD
FRM
M
CLK1
CLK2
CL
S1~S64
FRM
M
CLK1
CLK2
CL
VSS
5
VDD
15
CS3
CS2B NT7108
CS1B
DB0~DB7
RSTB
E
R/W
RS
SEG128
V0R/L
V2R/L
V3R/L
V5R/L
VEE
1/128 duty COMMON driver (NT7107) interface circuit
VDD
V0R/L
V1R/L
V4R/L
V5R/L
VEE
VSS
MS
V0R/L
V1R/L
V4R/L
V5R/L
VEE
VSS
15
RS
R/W
E
RSTB
DB0~DB7
CS1B
CS2B
CS3
MPU
OPEN
OPEN
OPEN
VEE
C1~C64
DIO2
DIO1
CLK2
CL2
M NT7107 CLK1
(Slave) FRM
2
CR
R
5
V4 V5
OPEN OPEN
C1~C64
DIO1
CR NT7107
DIO2
R
DS1 (Master) CL2
DS2
M
PCLK2
CLK1
MS
CLK2
FS
FRM
SHL
VDD
15
VEE
V0R/L
V2R/L
V3R/L
V5R/L
S1~S64
COM128
FRM
M
CLK1
CLK2
CL
VDD
COM1
CS3
NT7108 CS2B
CS1B
DB0~DB7
RSTB
E
R/W
RS
VSS
PCLK2
FS
DS1
DS2
SHL
SEG1
S1~S64
FRM
M
CLK1
CLK2
CL
VSS
CS3
CS2B NT7108
CS1B
DB0~DB7
RSTB
E
R/W
RS
VDD
15
V0R/L
V2R/L
V3R/L
V5R/L
VEE
LCD Panel
OPEN
VDD
V0
V1
V2
V3
VDD
12/18/2002
19/22
NEOTEC SEMICONDUCTOR LTD.
NT7108
PAD DIAGRAM
Note: Please connects the substrate to VDD or floating
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
52
29
53
28
54
27
55
26
56
25
57
24
58
23
59
22
60
21
61
20
62
19
63
18
64
17
X,Y(0,0)
65
16
66
15
67
69
70
13
12
11
71
10
72
9
73
8
74
7
75
6
76
5
77
4
78
12/18/2002
14
Chip size: 3050 X 4220
Pad size: 95x95
Unit: um
68
79
8
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
1
2
3
20/22
NEOTEC SEMICONDUCTOR LTD.
PAD DIAGRAM
Pad No. Pad name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
12/18/2002
ADC
M
VDD
V3R
V2R
V5R
V0R
VEE
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
NT7108
X
Y
Pad No.
Pad name
X
Y
1125.000
1250.000
1375.000
1408.100
-1994.198
-1994.198
-1994.198
-1725.300
-1600.300
-1475.300
-1350.300
-1225.300
-1100.300
-975.300
-850.300
-725.300
-600.300
-475.300
-350.300
-225.300
-100.300
24.700
149.700
274.700
399.700
524.700
649.700
774.700
899.700
1024.700
1124.700
1274.700
1399.700
1994.200
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
VEE
V0L
V5L
V2L
V3L
GND
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
CS3
CS2B
CS1B
RSTB
R/W
RS
CL
CLK2
CLK1
E
FRM
-1187.500
-1312.500
-1408.098
1994.200
1994.200
1399.700
1274.700
1149.700
1024.700
899.700
774.700
649.700
524.700
399.700
274.700
149.700
27.700
-100.300
-225.300
-350.300
-475.300
-600.300
-725.300
-850.300
-975.300
-1100.300
-1225.300
-1350.300
-1475.300
-1600.300
-1725.300
-1994.198
1312.500
1187.500
1062.500
937.500
812.500
687.500
562.500
437.500
312.500
187.500
62.500
-62.500
-187.500
-312.500
-437.500
-562.500
-687.500
-812.500
-937.500
-1062.500
-1375.000
-1250.000
-1125.000
-1000.000
-875.000
-750.000
-625.000
-500.000
-375.000
-250.000
-125.000
0.000
125.000
250.000
375.000
500.000
625.000
750.000
875.000
1000.000
21/22
NEOTEC SEMICONDUCTOR LTD.
NT7108
VERSION HISTORY
Date
6/5/2002
12/11/2002
12/18/2002
12/18/2002
Description
Add the notice of substrate connection.
To correct some mistakes at page 5,6,15,19
To correct some mistakes at page 3,4,7,8,12,16
22/22