Avant SBN6400G

DATA SHEET
SBN6400G
64-COMMON Driver for
Dot-Matrix STN LCD
To improve design and/or performance,
Avant Electronics may make changes to its
products. Please contact Avant Electronics
for the latest versions of its products
data sheet (v1)
2005 Jan 18
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
1
GENERAL
1.1
Description
The SBN6400G is 64-COMMON driver, designed to be paired with the SBN0064G 64-SEGMENT driver to drive a
dot-matrix STN LCD panel.
Functionally, the SBN6400G includes 64 COMMON drivers, on-chip RC oscillator, a 64-bit bi-directional shift register,
and timing generation circuit. The RC oscillator needs only an external resistor and capacitor. The timing generation
circuit generates clocks and display control signals for both the SBN6400G and the SBN0064G.
To expand COMMON number, the SBN6400G can be cascaded in master-slave connection.
1.2
Features
• To be paired with the SBN0064G 64-SEGMENT driver.
• 64-COMMON STN LCD drivers.
• Master Mode and Slave Mode for cascaded connection to expand COMMON numbers.
• On-chip RC oscillator; only an external resistor and an external capacitor are needed.
• Provides clocks and display control signal to the SBN0064G.
• External LCD bias (V0, V1, V4, V5).
• Selectable display duty cycle: 1/48, 1/64, 1/96, 1/128.
• Operating voltage range (VDD): 2.7 ~ 5.5 volts.
• LCD bias voltage (VLCD=VDD - V5, the voltage added to the LCD cell): 13 volts (max).
• Negative power supply (VNEG=VDD-VEE): 16 volts (max).
• Operating frequency range: 550 KHz.
• Operating temperature range: -20 to +75 °C.
• Storage temperature range: -55 to +125 °C.
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
1.3
Ordering information
Table 1
Ordering information
PRODUCT TYPE
DESCRIPTION
SBN6400G-LQFPG
LQFP100 Pb-free package.
SBN6400G-QFPG
QFP100 Pb-free package.
SBN6400G-LQFP
LQFP100 general package.
SBN6400G-QFP
QFP100 general package.
SBN6400G-D
tested die.
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
FUNCTIONAL BLOCK DIAGRAM AND DESCRIPTION
V5L
V4L
V1L
V0L
COM63
COM62
Functional block diagram
COM0
2.1
COM1
2
V5R
V4R
64-bits output Driver
64-bits Level Shifter
V1R
V0R
High Voltage Circuit
VEE1
VEE2
64
64-bit, bi-directional shift register
DIO1
SHL
PSEL
COMMON Shift Direction,
Phase Selection
DIO2
M
CL
VDD
Timing Generation
Circuit
On-chip
RC oscillator
CLK1
CLK2
DS2
DS1
FS
M/S
CR
R
C
VSS
FRM
Fig.1 Functional Block Diagram
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
3
PIN(PAD) ASSIGNMENT, PAD COORDINATES, SIGNAL DESCRIPTION
The SBN6400G pinning diagram (LQFP100 or QFP100)
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
VEE2
V1R
V4R
V5R
V0R
NC
CL
NC
3.1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SBN6400G
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
DIO2
PSEL
NC
M
FRM
NC
CLK1
CLK2
M/S
NC
VSS
SHL
NC
CR
NC
R
NC
C
DS2
DS1
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
VEE1
V1L
V4L
V5L
V0L
VDD
DIO1
FS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Fig.2 Pin assignment of LQFP100/QFP100 package.
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
9
8
7
6
5
4
3
2
10 COM12
11 COM11
12 COM10
13 COM9
14 COM8
15 COM7
16 COM6
17 COM5
18 COM4
19 COM3
20 COM2
21 COM1
22 COM0
23 VEE1
24 V1L
25 V4L
26 V5L
The SBN6400G pad placement
27 V0L
3.2
Pad #1
VDD 28
1 COM21
DIO1 29
92 COM22
FS 30
91 COM23
DS1 31
90 COM24
DS2 32
89 COM25
C 33
88 COM26
87 COM27
R 34
86 COM28
Y
3799 µm
CR 35
85 COM29
SHL 36
84 COM30
(0,0)
VSS 37
83 COM31
X
M/S 38
82 COM32
chip ID
81 COM33
80 COM34
CLK2 39
79 COM35
CLK1 40
78 COM36
77 COM37
FRM 41
76 COM38
M 42
PSEL 43
Chip size : 3999 µm x 3799 µm.
75 COM39
Pad size: 90 µm x 90 µm.
74 COM40
73 COM41
DIO2 44
72 COM42
COM43 71
COM44 70
COM45 69
COM46 68
COM47 67
COM48 66
COM49 65
COM50 64
COM51 63
COM52 62
COM53 61
COM54 60
COM55 59
COM56 58
COM57 57
COM58 56
COM59 55
COM60 54
COM61 53
COM62 52
COM63 51
VEE2 50
V1R 49
V4R 48
V0R 46
V5R 47
CL 45
3999 µm
Note:
(1)
(2)
(3)
(4)
The total of pad number is 92.
The chip ID is located at the right middle part of the chip.
The chip ID is 12001.
The die origin is at the center of the chip.
Fig.3 The pad placement
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
3.3
Pad coordinates
Table 2
The pad coordinates (unit: µm)
PAD
NO.
PAD
NAME
X
Y
PAD
NO.
PAD
NAME
X
Y
PAD PAD
NO. NAME
X
Y
1
COM21
1866
1575
35
CR
-1857
305
69
1399
-1767
2
COM20
1659
1768
36
SHL
-1857
163
70
COM44
1529
-1767
3
COM19
1529
1768
37
VSS
-1857
20
71
COM43
1659
-1767
4
COM18
1399
1768
38
M/S
-1857
-130
72
COM42
1866
-1575
5
COM17
1269
1768
39
CLK2
-1857
-379
73
COM41
1866
-1425
6
COM16
1139
1768
40
CLK1
-1857
-625
74
COM40
1866
-1275
7
COM15
1009
1768
41
FRM
-1857
-873
75
COM39
1866
-1125
8
COM14
879
1768
42
M
-1857
-1052
76
COM38
1866
-974
9
COM13
749
1768
43
PSEL
-1857
-1276
77
COM37
1866
-824
10
COM12
619
1768
44
DIO2
-1857
-1558
78
COM36
1866
-674
11
COM11
489
1768
45
CL
-1857
-1748
79
COM35
1866
-524
12
COM10
359
1768
46
V0R
-1591
-1767
80
COM34
1866
-374
13
COM9
229
1768
47
V5R
-1461
-1767
81
COM33
1866
-224
14
COM8
99
1768
48
V4R
-1331
-1767
82
COM32
1866
-74
15
COM7
-31
1768
49
V1R
-1201
-1767
83
COM31
1866
76
16
COM6
-161
1768
50
VEE2
-1071
-1767
84
COM30
1866
226
17
COM5
-291
1768
51
COM63
-941
-1767
85
COM29
1866
376
18
COM4
-421
1768
52
COM62
-811
-1767
86
COM28
1866
525
19
COM3
-551
1768
53
COM61
-681
-1767
87
COM27
1866
675
20
COM2
-681
1768
54
COM60
-551
-1767
88
COM26
1866
825
21
COM1
-811
1768
55
COM59
-421
-1767
89
COM25
1866
975
22
COM0
-941
1768
56
COM58
-291
-1767
90
COM24
1866
1125
23
VEE1
-1071
1768
57
COM57
-161
-1767
91
COM23
1866
1275
24
V1L
-1201
1768
58
COM56
-31
-1767
92
COM22
1866
1425
25
V4L
-1331
1768
59
COM55
99
-1767
26
V5L
-1461
1768
60
COM54
229
-1767
27
V0L
-1591
1768
61
COM53
359
-1767
28
VDD
-1838
1785
62
COM52
489
-1767
29
DIO1
-1857
1533
63
COM51
619
-1767
30
FS
-1857
1345
64
COM50
749
-1767
31
DS1
-1857
1165
65
COM49
879
-1767
32
DS2
-1857
984
66
COM48
1009
-1767
33
C
-1857
776
67
COM47
1139
-1767
34
R
-1852
601
68
COM46
1269
-1767
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COM45
data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
3.4
Signal description
Table 3 Pin signal description
To avoid a latch-up effect at power-on: VSS − 0.5 V < voltage at any pin at any time < VDD + 0.5 V .
Pin
number
Pad
number
SYMBOL
DESCRIPTION
COMMON outputs.
The output voltage level of COMMON outputs are decided by the combination of
the alternating frame signal (M) and the internal Shift Register Output. Depending
on the value of M and the Shift Register Output, a single voltage level is selected
from V0, V1, V4, or V5 for COMMON driver, as shown in Fig. 4.
1~22,
1~22,
59~100
51~92
COM21~0
COM63~22
M
Internal
Shift Register
COM output
0
0
1
0
1
0
1
0
1
0
1
0
1
V1
V0
V4
V5
V1
V0
V4
V5
Fig.4 COMMON output voltage level
External negative power supply for LCD bias.
23, 58
23, 50
VEE1, VEE2
These two inputs are internally connected together inside the chip. However, to
avoid flickering, same external negative bias voltage should be connected to these
two inputs.
External LCD Bias voltage.
24, 25,
26, 27
24, 25,
26, 27
V1L, V4L,
V5L V0L
These pins should be connected to V1, V4, V5, and VDD, respectively, of the
external LCD bias circuit, and the condition VDD≥V1≥V2≥V3≥V4≥V5 must always
be met.
These pins are internally connected to V1R, V4R, V5R, and V0R, respectively.
Power supply for logic circuit of the chip.
28
28
VDD
The VDD should be in the range from 2.7 volts to 5.5 volts.
Input or output for master/slave mode operation in a cascading connection.
29, 50
29, 44
DIO1, DIO2
Please refer to Sections 4.6 and 4.7.
Oscillator Frequency Selection.
When the device operates in master mode, FS is used to select the RC oscillator
frequency to make frame frequency approximately equal to 70Hz.
30
30
FS
If the RC oscillator frequency is 550K Hz (at VDD=5 volts), then this input should be
connected to VDD.
If the RC oscillator frequency is 225K Hz (at VDD=5 volts), then this input should be
connected to VSS.
Usually, 550K Hz is recommended and this pin should be connected to VDD.
When the device operates in slave mode, this input should be connected to VDD.
2005 Jan 18
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
Pin
number
Pad
number
SYMBOL
DESCRIPTION
Display duty selection inputs.
31, 32
31, 32
DS1, DS2
These two inputs are used to select display duty cycle when the SBN6400G
operates in master mode.
These pins are not valid in slave mode and should be connected to VDD.
Pins of the on-chip RC oscillator for connection to external resistor and capacitor.
33, 35,
37
33, 34,
35
C, R, CR
When operating in slave mode, the device’s C and R terminals should be left open
and its CR terminal should be connected to VDD.
Instead of the RC oscillator, if an external clock source is to be used, then this clock
source should be added to the CR terminal. In this case, both the C and R terminals
should be left open.
This input is used to select COMMON output sequence
39
36
SHL
When SHL=1, COMMON output sequence is from COM0 to COM63.
When SHL=0, COMMON output sequence is from COM63 to COM0.
40
37
VSS
42
38
M/S
When this input is connected to VDD, the SBN6400G operates in Master Mode.
When this input is connected to VSS, the SBN6400G operates in Slave Mode.
39, 40
CLK2,
CLK1
Clock outputs to the SBN0064G.
43, 44
Ground.
This input is used to select Master Mode or Slave Mode.
The frequency of these two clocks is a half of the RC oscillator clock frequency.
Frame signal, indicating the start of a frame.
46
41
FRM
When the SBN6400G operates in master mode, its FRM output should be
connected to the FRM input of the SBN0064G.
When the SBN6400G operates in slave mode, its FRM output should be left open.
For the timing of this signal, please refer to Fig. 11
Alternating frame signal for generating LCD biases of reverse polarites.
47
42
M
This is an I/O terminal. When the SBN6400G operates in master mode, this
terminal becomes output and should be connected to its slave.
When the device operates in slave mode, this terminal becomes input and accepts
M output from its master.
Phase selection for COMMON output.
49
43
PSEL
This input selects the phase relation between the COMMON outputs and the CL
clock. If PSEL=1 (i.e., connected to VDD), each COMMON output starts on the
rising edge of CL. If PSEL=0 (i.e., connected to VSS), each COMMON output starts
on the falling edge of CL.
Usually, PSEL should be connected to VDD.
2005 Jan 18
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
Pin
number
Pad
number
52
45
SYMBOL
DESCRIPTION
Shift clock for the internal 64-bit, bi-directional shift register.
CL
The time duration of each COMMON output is equal to one clock period of the CL
clock.
External LCD Bias voltage.
54, 55,
56, 57
46, 47,
48, 49
V0R, V5R,
V4R, V1R
These terminals should be connected to V1, V4, V5, and VDD, respectively, of the
external LCD bias circuit, and the condition VDD≥V1≥V2≥V3≥V4≥V5 must always
be met.
These terminals are internally connected to V1L, V4L, V5L, and V0L, respectively.
34, 36,
38, 41,
45, 48,
51, 53
2005 Jan 18
No Connection.
NC
For package type, these pins should be left open.
For die, there is no NC pad.
10 of 34
data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
4
FUNCTIONAL DESCRIPTION
4.1
On-chip RC oscillator
When operating in master mode, the SBN6400G’s on-chip RC-type oscillator is used to provide clocks and necessary
control signals to itself, its slave, and the SBN0064G SEGMENT Driver.
External resistor Rf and capacitor Cf need to be connected across R, CR, and C, as shown in Fig. 5. The recommended
value for Rf is 33K ohm and that for Cf is 20 pF. During PCB layout, the resistor and the capacitor should be placed as
close to the SBN6400G as possible, such that stray capacitance, inductance, and resistance can be minimized.
Note:
(1) When operating in slave mode,
the C and R terminals should be
left open and the CR terminal
should be connected to VDD.
(2) When operating in master mode
and using an external clock
source, the C and R terminals
should be left open and external
clock source should be added to
the CR terminal.
VDD
CR
Cf
CLK
VSS
20P
VDD
C
VSS
Rf
33K
VDD
R
VSS
Fig.5 On-chip RC oscillator
The typical oscillation frequency of the oscillator at different power supply voltages, with Cf fixed to 20 pF, is given in
Table 4.
Table 4
On-chip RC oscillator characteristics, Cf= 20 pF, Tamb = −20 to +75 °C
Rf value (unit: ohm)
VDD=5V
VDD=3V
VDD=2.7V
47K
406
361
350
43K
443
392
377
39K
484
425
406
33K
557
485
463
30K
601
521
497
unit
KHz
Note:
1. The values given in this table are typical values. ±10% variation from lot to lot may exists.
2005 Jan 18
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
4.2
RC-oscillator Frequency Selection (FS)
When the RC oscillator frequency is 550 KHz, FS should be connected to VDD. When the RC oscillator frequency is below
300 KHz, FS should be connected to VSS. In the both cases, the purpose of this input is to make frame frequency
approximately equal to 70 Hz.
Usually, 550 KHz operation is recommended.
4.3
Timing Generation
The SBN6400G’s internal timing generation circuit is shown in Fig. 6.
When M/S=1, the SBN6400G operates in Master Mode, sends M and CL to its slave, and sends M, CL, FRM, CLK1, and
CLK2 to the SBN0064G.
When M/S=0, the SBN6400G operates in Slave Mode and receives M and CL from its master. In addition, when
operating in slave mode, the SBN6400G will not send out FRM, CLK1, and CLK2. These terminals should be left open.
To internal logic circuit
M
to slave / from master
CL
C
CR
RC Oscillator
CLK
(basic clock)
Timing Generation
Circuit
R
Note:
(1) If FS=1, then CLK clock will be
divided by 2 inside the Timing
Generator Circuit.
DS1 DS2 M/S
M
CL
FRM
CLK1
CLK2
to SBN0064G
FS
From external pins(pads)
Fig.6 Timing generation circuit
4.4
Duty selection
When the SBN6400G operates in Master Mode, the display duty is decided by its DS1 and DS2 inputs. When the
SBN6400G operates in slave mode, its DS1 and DS2 has no function and should be connected to VDD.
Table 5 gives the setting of the DS1 and DS2 and the corresponding display duty cycle.
Table 5
Duty selection
2005 Jan 18
DS1
DS2
Duty
1
1
1/128
1
0
1/96
0
1
1/64
0
0
1/48
12 of 34
data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
4.5
Phase relation between CL and COMMON outputs
The PSEL input is used to select the phase relation between CL clock and COMMON outputs. The CL clock is the shift
clock to the internal 64-bit, bi-directional Shift Register. A CL clock period is the time duration for displaying a horizontal
line of LCD pixels.
If PSEL=H, the COM0 starts from the rising edge of CL clock. If PSEL=L, then COM0 starts from the falling edge of CL,
as shown in Fig. 7.
Usually, it is recommended that PSEL be connected to VDD.
0
1
2
61
62
63
0
1
2
61
62
63
CL
COM0 scan period
COM0
PSEL=H
COM1 scan period
COM1
COM2 scan period
COM2
COM0 scan period
COM0
COM1 scan period
PSEL=L
COM1
COM2 scan period
COM2
Fig.7 Phase relation between COMMON and CL, as decided by PSEL
2005 Jan 18
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
4.6
Master/Slave connection
The SBN6400G can be cascaded in master-slave connection to expand the total number of COMMONs.
When a device is selected as master, its DIO1, DIO2, M, and CL are all in output state. Its M output and CL output should
be connected to its slave and its M, CL, FRM, CLK1 and CLK2 should be connected to the SBN0064G.
COM0
VDD
CLK2
COM64 ~~ COM127
COM63
COM0
CL
CL
M
Slave
M/S
DIO1
DIO2
SHL
VSS
COM63
SBN6400G
M
Master
M/S
CLK1
COM0 ~~~ COM63
SBN6400G
Open
To SBN0064G
FRM
CLK2
CLK1
FRM
To SBN0064G
DIO1
DIO2
SHL
open
To next stage or open
Fig.8 Master/Slave connection with SHL=1
4.7
COMMON output sequence
The COMMON output sequence is decided by both the M/S and the SHL inputs, as shown in Table 6.
Table 6
COMMON output sequence in master-slave connection
M/S
SHL
DIO1
DIO2
COMMON SHIFT DIRECTION
1
(master)
1
x
Output
C0 → C63
0
Output
x
C63 → C0
Note 1
1
Input
Output
C0 → C63(master), C0 → C63(slave)
Note 2
0
Output
Input
C63 → C0(master), C63 → C0(slave)
Note 3
0
(slave)
NOTES
Notes
1. When the SBN6400G is in master mode, both its DIO1 and DIO2 are always output, and COMMON output sequence
is decided by SHL. If SHL=1, COM0 is output first and COM63 is output last. If SHL=0, COM63 is output first and
COM0 is output last.
2. When the SBN6400G operates in slave mode and its SHL is HIGH, its DIO1 becomes input and its DIO2 becomes
output. The slave’s DIO1 should be connected to DIO2 of the master. The COM0 of the master is output first. After
COM63 of the master is output, COM0 of the slave is output. COM63 of the slave is output last.
3. When the SBN6400G operates in slave mode and its SHL is LOW, its DIO1 becomes output and its DIO2 becomes
input. The slave’s DIO2 should be connected to DIO1 of the master. The COM63 of the master is output first. After
COM0 of the master is output, COM63 of the slave is output. COM0 of the slave is output last.
2005 Jan 18
14 of 34
data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
5
LCD BIAS AND COMMON OUTPUT VOLTAGE
5.1
LCD bias circuit
A typical LCD bias circuit for 1/64 display duty is shown in Fig. 9. The condition VDD≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 must
always be met. The maximum allowed voltage for LCD bias (VDD-V5) is 13 volts. Note that V0 should be connected to
VDD.
COMPONENT
RECOMMENDED
VALUE
C
0.1 µF,
electrolytic
R1
2.2K ohm
R2
10K ohm
R3
10K ohm,
variable resistor
VDD
VDD
VDD
C
C
C
Note:
C
(1) V0 should always be connected to VDD.
(2) For cascading application, it is recommended that a
buffer be added for each of V1, V2, V3, V4, and V5.
For 64 COM x 64 SEG application, these buffers are
not needed.
(3) The LCD bias voltage (VLCD = V0 - V5) should not
exceed 13 volts, without regard to display duty.
(4) The voltage difference between VDD (the most
positve power) and VEE (the most negative
power), VDD - VEE, should not exceeds 16 volts,
without regards to display duty.
C
R1
R1
R2
R1
R1
V0
V0L/V0R
V1
V1R/V1L
V2
To SBN0064G
V3
To SBN0064G
SBN6400G
V4
V4R/V4L
V5
V5R/V5L
R3
COM0~COM63
VEE1,VEE2 VSS
VEE
Fig.9 LCD Bias circuit for 1/64 display duty
5.2
Relation of display duty, CL period, LCD bias, and recommended resistor ladder for bias
Table 7gives the relation of display duty, CL period, LCD bias, and recommended resistor ladder for bias.
Table 7
Relation of display duty and LCD bias
Duty
CL period
Bias
Resistor ladder
1/48
64 x CLK2
1/8
R2= 4 x R1
1/64
48 x CLK2
1/9
R2= 5 x R1
1/96
32 x CLK2
1/11
R2= 7 x R1
1/128
24 x CLK2
1/12
R2= 8 x R1
Note:
1. When the display duty cycle 1/64 is chosen, the condition ( R1 ) ⁄ ( 4 × R1 + R2 ) = 1 ⁄ 9 should be met. We choose
R1=2.2K ohm and, therefore, the calculated value of R2 is 11K ohm. As 11K ohm is not a standard value for
resistors, we choose a 10K ohm resistor for R1.
2. The duration (period) of a CL clock is a multiple of the CLK2 clock. The time duration of each COMMON output is
equal to one period of the CL clock.
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
5.3
COMMON, SEGMENT output voltage
Table 8 gives the output voltage level of the SBN6400G COMMON Driver and the SBN0064G SEGMENT Driver.
The COMMON output voltage level of the SBN6400G COMMON Driver is decided by the combination of the alternating
LCD bias voltage (M) and its internal Shift Register Output.
The SEGMENT output voltage level of the SBN0064G SEGMENT driver is decided by the combination of the alternating
LCD bias voltage (M) and the output of its on-chip Display Data Memory.
Table 8
COMMON/SEGMENT output voltage level
Frame (M)
Data/COM
DISPLAY
ON/OFF
SEG0~SEG63
(SBN0064G)
COM0~COM63
(SBN6400G)
L
L
ON
V2
V1
L
H
ON
V0
V5
H
L
ON
V3
V4
H
H
ON
V5
V0
x(don’t care)
x(don’t care)
OFF
V2, V3
x
Note:
1. “Data” in the “Data/COM” column means the data output from the on-chips Display Data RAM of the SBN0064G
SEGMENT Driver, and “COM” means the output of the SBN6400G’s internal Shift Register Output, which
sequentially activates COM0~COM63.
2. The column DISPLAY ON/OFF is applicable only to the SBN0064G.
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
6
SYSTEM CONFIGURATION WITH THE SBN0064G
Table 9 gives examples of system configuration with the SBN0064G.
Table 9
Examples of system configuration with the SBN0064G.
Configuration
Description
COM0
64 x 64 panel
SBN6400G
One SBN6400G drives the COM 0 ~ 63 of
the panel and supplies timing and display
control signals M, CL, FRM, CLK1, and
CLK2 to one SBN0064G, which interfaces
with a host microcontroller and drives
SEG 0 ~ 63.
SEG0
SEG63
COM63
M, CL, FRM,
CLK1, CLK2
SBN0064G
COM0
M, CL, FRM,
CLK1, CLK2
SEG63
SEG0
SBN0064G
64 x 64 panel
One SBN6400G drives the COM 0 ~ 63 of
both the upper panel and the lower panel,
and supplies timing and display control
signals M, CL, FRM, CLK1, and CLK2 to two
SBN0064G. The two SBN0064G
respectively interfaces with the host
microcontroller and drives SEG 0 ~ 63 of the
upper panel and the lower panel.
COM63
Upper panel
Lower panel
COM0
64 x 64 panel
SBN6400G
SEG63
SEG0
COM63
SBN0064G
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
Configuration
Description
M, CL, FRM,
CLK1, CLK2
COM0
64 x 64 panel
SBN6400G
Master
SEG63
SEG0
SBN0064G
COM63
One SBN6400G operates in Master Mode
and supplies timing and display control
signals to two SBN0064G. One SBN6400G
operates in Slave Mode and receives M and
CL signals from the Master.
Upper panel
M, CL
Lower panel
COM0
64 x 64 panel
SBN6400G
SEG63
Slave
SEG0
COM63
SBN0064G
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
7
APPLICATION EXAMPLE 1: MASTER MODE, 1/64 DISPLAY DUTY
7.1
Application circuit for 1/64 display duty, Master Mode operation
VDD
VDD
COM0
COM0
COM63
COM63
V0L, V0R
V1L, V1R
V4L, V4R
64 COM x 64 SEG
LCD panel
V5L, V5R
SBN6400G
SHL
C
DS1
CR
DS2
Cf
20P
R
M/S
CL
CL
M
M
open
DIO1
FRM
FRM
open
DIO2
CLK1
VSS
CLK2
CLK1
CLK2
VEE
SEG63
SEG0
SEG63
VDD
Rf
33K
FS
PSEL
SEG0
VDD
SBN0064
Microcontroller
Interface
To / From
Microcontroller
VSS
VEE V0, V2, V3, V5
VDD
V0, V1, V2, V3, V4, V5
VDD
VEE
LCD Bias Circuit
VSS
Fig.10 Application circuit for 1/64 display duty, Master Mode operation
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
7.2
Timing diagram of Master Mode, 1/64 display duty cycle(DS1=L, DS2=H, SHL=H(L), PSEL=H)
0
1
2
3
4
91
92
93
94
95
Note:
CLK
(1) CLK is the clock from the
RC-oscillator.
CLK1
0
CLK2
46
1
(2) The frequency of both CLK1 and
CLK2 is a half of the CLK.
47
TCL
TCL
0
1 Frame
1
2
61
1 Frame
62
63
0
1
2
61
62
63
CL
FRM
M
DIO1 (DIO2)
(input of slave)
DIO2 (DIO1)
(output)
C0 (C63)
V1
V0
V4
C1 (C62)
V1
V4
V4
C62 (C1)
V5
V0
V1
V1
V4
V5
V0
V1
V4
V1
V4
V0
C63 (C0)
V0
V1
V4
V1
V4
V5
V1
V5
V5
V4
Fig.11 Master mode timing for 1/64 display duty
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
8
APPLICATION EXAMPLE 2: MASTER MODE, 1/128 DISPLAY DUTY
8.1
Application circuit for 1/128 display duty, Master Mode operation
VDD
VDD
V0L, V0R
C
V1L, V1R
CR
Cf
20P
V4L, V4R
V5L, V5R
Rf
33K
R
SBN6400G
SHL
Master CL
DS1
M
DS2
FRM
FS
CLK1
M/S
CLK2
PSEL
open
128 COM x 64 SEG
LCD panel
COM0
COM0
DIO1
DIO2
COM63
VEE COM63
VSS
VDD
COM64
COM0
V0L, V0R
V1L, V1R
V4L, V4R
COM127
COM63
V5L, V5R
C
SBN6400G
open
SEG0
SEG63
VDD SEG0
SEG63
CR
Slave
SHL
R open
DS1
VDD
DS2
FS
M/S
open
CL
CL
PSEL
M
M
DIO1
FRM
DIO2
VSS
CLK1
VEE
CLK2
open
open
open
FRM
SBN0064
Microcontroller
Interface
CLK1
To/From
Microcontroller
VSS
CLK2 VEE V0, V2, V3, V5
VDD
V0, V1, V2, V3, V4, V5
VDD
VEE
LCD Bias Circuit
VSS
Fig.12 Application circuit for 1/128 display duty, Master Mode operation
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
8.2
Timing diagram of Master Mode, 1/128 display duty cycle(DS1=H, DS2=H, SHL=H(L), PSEL=H)
0
1
2
3
4
43
44
45
46
47
Note:
(1) CLK is the clock from the
RC-oscillator.
(2) The frequency of both CLK1 and
CLK2 is a half of the CLK.
CLK
CLK1
0
CLK2
22
1
23
TCL
TCL
0
1
2
125
126
127
0
1
2
125
126
127
CL
FRM
M
DIO1 (DIO2)
C0 (C127)
V1
V0
V4
V1
V4
V4
C126 (C1)
V5
V0
C1 (C126) V1
V1
V4
V5
V0
V1
V4
V1
V4
V0
C127 (C0)
V0
V1
V4
V1
V4
V5
V1
V5
V5
V4
DIO2 (DIO1)
Fig.13 Master mode timing for 1/128 display duty
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
9
ELECTRICAL CHARACTERISTICS
9.1
Absolute maximum rating
Table 10 Absolute maximum rating
VDD = 5 V ±10%; VSS = 0 V; all voltages with respect to VSS, unless otherwise specified; Tamb = −20 to +75 °C
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
voltage on the VDD pin(pad)
−0.3
+7.0
Volts
VDD-16
13
Volts
VDD + 0.3
Volts
200
mW
VEE
Negative voltage on the VEE pin(pad)
VLCD (note 2)
LCD bias voltage, VLCD=V0-V5
VI
input voltage on any pin with respect to VSS
PD
power dissipation
Tstg
storage temperature range
−55
+125
°C
Tamb
operating ambient temperature range
-30
+ 85
°C
Tsol (note 3)
soldering temperature/time at pin
−0.3
Volts
260 °C,
10 Second
Notes
1. The following applies to the Absolute Maximum Rating:
a) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
b) The SBN6400G includes circuitry specifically designed for the protection of its internal devices from the damaging
effect of excessive static charge (ESD). However, it is suggested that conventional precautions be taken to avoid
applying greater than the rated maxima.
c) Parameters are valid over operating temperature range, unless otherwise specified.
d) All voltages are with respect to VSS, unless otherwise noted.
2. The condition VDD(V0)≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 must always be met.
3. QFP-type packages are sensitive to moisture of the environment, please check the drypack indicator on the tray
package before soldering. Exposure to moisture longer than the rated drypack level may lead to cracking of the
plastic package or broken bonding wiring inside the chip.
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
10 DC CHARACTERISTICS
Table 11 DC Characteristics
VDD = 5 V ±10%; VSS = 0 V; all voltages with respect to VSS, unless otherwise specified; Tamb = −20 to +75 °C.
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
2.7
5.0
5.5
V
VDD
Supply voltage for logic
VLCD
LCD bias voltage VLCD= V0(VDD)-V5 Note 1.
13
V
VNEG
VNEG=VDD-VEE
16
V
VIL
LOW level input voltage
Note 2.
0
0.8
V
VIH
HIGH level input voltage
Note 2.
VDD-2.2
VDD
V
VOL
LOW level output voltage of output
terminals, at IOL=1.6 mA.
Note 3
0.0
0.3
V
VOH
HIGH level output voltage of output
terminals, at IOH=-200µA.
Note 3.
VDD − 0.3
VDD
V
ILKG
Leakage current of input pins(pads)
for all inputs
0.2
µA
ISTBY
Standby current at VDD=5 volts
Note 4
3.0
µA
IDD(1)
Operating current for master mode
with 1/128 display duty cycle
Note 5
960
µA
IDD(2)
Operating current for slave mode
with 1/128 display duty cycle
Note 6
180
µA
IEE
Operating current measured at the
VEE pin(pad)
Note 7
90
µA
Cin
Input capacitance of all input pins
8.0
pF
RON
LCD driver ON resistance
1.5
ΚΩ
5.0
Note 8
Notes:
1. LCD bias voltage VLCD is V0 - V5. V0 should always be connected to VDD.
2. For all input pins (pads), FS, DS1,DS2, CR, SHL, MS, and PSEL. Also, for all I/Os, DIO1, DIO2, M, and CL when
they are used as inputs.
3. For all output pins (pads), CLK1, CLK2, and FRM. Also, for all I/Os, DIO1, DIO2, M, and CL when they are used as
outputs
4. Conditions for the measurement: CR=VDD, measured at the VDD pin.
5. This value is measured at the VDD pin (pad). The condition for the measurement is as follows:
a) Rf=33K, Cf=20 pF,
b) Display duty cycle=1/128 (DS1=DS2=1),
c) Master mode (M/S=1), and FS=SHL=PSEL=1, and
d) COM0~COM63 were left open.
6. This value is measured at the VDD pin (pad). The condition for the measurement is as follows:
a) Display duty cycle=1/128 (DS1=DS2=1), Slave mode (M/S=0), and FS=SHL=PSEL=CR=1,
b) CL, M, and DIO1 are from the master, and
c) COM0~COM63 were left open.
7. The condition for the measurement is the same as those described in Note 5, except that the value is measured at
the VEE pin(pad).
8. This measurement is for the transmission high-voltage PMOS or NMOS of COM0~COM63. Please refer to
Section 12, Pin Circuits, for detailed schematic of these drivers. The measurement is for the case when the voltage
differential between the source and the drain of the high voltage PMOS or NMOS is 0.1 volts.
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
11 AC TIMING CHARACTERISTICS
11.1
CLK1, CLK2 timing for Master Mode
tWH1
CLK1
tR1
tF1
0.2VDD
CLK2
0.8VDD
0.8VDD
0.8VDD
0.2VDD
tD21
tD12
tWL1
0.8VDD
0.8VDD
0.2VDD
0.8VDD
0.2VDD
tR2
tF2
tWL2
tWH2
Fig.14 CLK1 and CLK2 timing for Master Mode
Table 12 CLK1 and CLK2 timing characteristics for Master Mode
VDD = 5 V ±10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified; Tamb = −20 to +75 °C.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
TWH1
CLK1 clock high pulse width
2000
TWL1
CLK1 cock low pulse width
600
TR1
CLK1 clock rise time
130
TF1
CLK1 clock fall time
130
TWH2
CLK2 clock high pulse width
2000
TWL2
CLK2 clock low pulse width
600
TR2
CLK2 clock rise time
130
TF2
CLK2 clock fall time
130
TD12
CLK1-to-CLK2 delay
660
TD21
CLK2-to-CLK1 delay
660
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UNIT
ns
data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
11.2
CL, FRM, DIO1, DIO2 and M timing for Master Mode
Start of a new frame
TWHCL
CL
0.8 x VDD
0.8 x VDD
0.2 x VDD
0.2 x VDD
0.2 x VDD
TDS
TDH
TDS
DIO1 (SHL=VDD)
DIO2 (SHL=VSS)
(input of Slave)
0.8 x VDD
TWLCL
0.8 x VDD
0.8 x VDD
TDD
TDD
DIO2, DIO1
(output of Master)
0.8 x VDD
TDFRM
0.2 x VDD
TDFRM
0.8 x VDD
FRM
0.2 x VDD
TDM
0.8 x VDD
M
0.2 x VDD
Note:
(1) PSEL=1, M/S=1
(2) Cf=20 pF, Rf=33K ohm.
Fig.15 CL, FRM, DIO1, DIO2, and M timing when in Master Mode
Table 13 CL, FRM, DIO1, DIO2, and M timing for Master Mode
VDD = 5 V ±10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified; Tamb = −20 to +75 °C.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
TWHCL
CL clock high pulse width
33
µs
TWLCL
CL cock low pulse width
33
µs
TDS
DIO1 setup time (for SHL=1),
DIO2 setup time (for SHL=0)
18
µs
TDH
DIO1 hold time (for SHL=1),
DIO2 hold time (for SHL=0)
38
µs
TDD
Data delay time
4.6
µS
TDFRM
FRM delay time
-1.8
+1.8
µS
TM
M delay time
-1.8
+1.8
µS
Note:
The measurement is with the load circuit connected for output terminals. The load circuit is shown in Fig. 16.
2005 Jan 18
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
Pin
CL
Note:
CL= 30 pF (including wiring and probe capacitance).
VSS
2005 Jan 18
Fig.16 Load circuit for timing diagrams.
27 of 34
data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
11.3
Slave Mode timing for 1/64 display duty cycle(DS1=L, DS2=H, SHL=H(L), PSEL=L)
0
1
2
61
62
63
0
1
2
61
62
63
CL
M
DIO1 (DIO2)
C0 (C63)
V1
V0
V4
V1
V4
V4
C62 (C1)
V5
V0
C1 (C62) V1
V1
V4
V5
V0
V1
V4
V1
V4
V0
C63 (C0)
V0
V1
V4
V1
V4
V5
V1
V5
V5
V4
DIO2 (DIO1)
Note
(1) PSEL=L.
(2) SHL=H.
(3) if SHL=L, then COMMON output sequence is inverted, as
shown in the parenthesis.
Fig.17 Slave mode timing for 1/64 display duty
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
12 PIN CIRCUITS
Table 14 MOS-level schematics of all input, output, and I/O pins.
SYMBOL
Input/
output
CIRCUIT
NOTES
VDD
PMOS
CLK1, CLK2,
Outputs
FR
NMOS
The output PMOS and
NMOS also act as
ESD-protection
devices. Their sizes
have been enlarged to
increase ESD
protection voltage.
VSS
VDD
DS1, DS2,
FS, SHL,
PSEL, M/S
Input
VSS
C, R, CR
Inputs
For the pin electronics of the these inputs, please refer to Fig. 5,
Section 4.1, On-Chip RC oscillator.
VDD
Output Enable
DIO1, DIO2,
M, CL
I/O
PMOS
Data out
The output PMOS and
NMOS also act as
ESD-protection
devices. Their sizes
have been enlarged to
increase ESD
protection voltage.
NMOS
VSS
Data in
2005 Jan 18
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
SYMBOL
Input/
output
CIRCUIT
VDD
EN1
NOTES
VDD
COM0~COM63
V0R/V0L
VEE
COM0~63,
V0R, V0L,
VDD
VEE
V1R/V1L
V1R, V1L,
V4R, V4L,
EN2
VEE
VDD
EN3
VDD
EN4
V4R/V4L
V5R, V5L
VEE
V5R/V5L
VEE
2005 Jan 18
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
13 APPLICATION NOTES
1. It is recommended that the following power-up sequence be followed to ensure reliable operation of your display
system. As the ICs are fabricated in CMOS and there is intrinsic latch-up problem associated with any CMOS
devices, proper power-up sequence can reduce the danger of triggering latch-up. When powering up the system,
control logic power must be powered on first. When powering down the system, control logic must be shut off later
than or at the same time with the LCD bias (VEE).
1 second (minimum)
1 second (minimum)
5V
VDD
0V
0~50 ms
0~50 ms
Signal
VEE
0 second
(minimum)
0 second
(minimum)
-11V
Fig.18 Recommended power up/down sequence
2. The metal frame of the LCD panel should be grounded.
3. A 0.1 µF ceramic capacitor should be connected between VDD and VSS.
4. A 0.1 µF ceramic capacitor should be connected between VDD (or VSS) and each of V1, V2, V3, V4, and V5.
2005 Jan 18
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
14 PACKAGE INFORMATION
Package information is provided in another
document. Please contact Avant Electronics for
package information.
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
15 SOLDERING
15.1
Introduction
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and
surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for
surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often
used.
This text gives a very brief insight to a complex technology. For more in-depth account of soldering ICs, please refer to
dedicated reference materials.
15.2
Reflow soldering
Reflow soldering techniques are suitable for all QFP packages.
The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight),
vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, please
contact Avant for drypack information.
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the
printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between
50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.
15.3
Wave soldering
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
If wave soldering cannot be avoided, the following conditions must be observed:
• A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering
technique should be used.
• The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves
downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
15.4
Repairing soldered joints
Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less
than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a
dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
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data sheet (v1)
SBN6400G
Avant Electronics
64-COMMON Driver for Dot-Matrix STN LCD
16 LIFE SUPPORT APPLICATIONS
Avant’s products, unless specifically specified, are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal injury. Avant customers using or
selling Avant’s products for use in such applications do so at their own risk and agree to fully indemnify Avant for any
damages resulting from such improper use or sale.
2005 Jan 18
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data sheet (v1)
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