DATASHEET

X9111
®
Single Supply/Low Power/1024-Tap/SPI Bus
Data Sheet
September 15, 2006
Single Digitally-Controlled (XDCP™)
Potentiometer
FN8159.4
Features
• 1024 Resistor Taps – 10-Bit Resolution
The X9111 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS integrated
circuit.
• SPI Serial Interface for Write, Read, And Transfer
Operations Of The Potentiometer
• Wiper Resistance, 40Ω Typical @ 5V
The digital controlled potentiometer is implemented using
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the SPI bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• Four Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on
Power-Up.
• Standby Current <3µA Max
• VCC: 2.7V to 5.5V Operation
• 100kΩ End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes Per Bit Per Register
• 14 Ld TSSOP
• Low Power CMOS
• Single Supply Version of the X9110
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
TSSOP
SO
A0
1
14
VCC
2
13
RL
NC
3
12
RH
CS
4
11
RW
SCK
SI
VSS
5
10
6
9
8
HOLD
A1
X9111
7
WP
Functional Diagram
VCC
SPI
Bus
Interface
Address
Data
Status
Bus
Interface &
Control
RH
Write
Read
Transfer
Control
VSS
1
Power On Recall
100kΩ
1024-taps
POT
Wiper Counter
Register (WCR)
Data Registers
(DR0-DR3)
NC
Wiper
RW
RL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
XDCP is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.
X9111
Ordering Information
PART NUMBER
PART MARKING
POTENTIOMETER
VCC LIMITS (V) ORGANIZATION (kΩ) TEMP RANGE (°C)
5 ±10%
100
PACKAGE
X9111TV14I
X9111TV I
X9111TV14IZ (Note)
X9111TV ZI
X9111TV14
X9111TV
0 to +70
14 Ld TSSOP (4.4mm)
X9111TV14Z (Note)
X9111TV Z
0 to +70
14 Ld TSSOP (4.4mm) (Pb-free)
X9111TV14-2.7
X9111TV F
0 to +70
14 Ld TSSOP (4.4mm)
X9111TV14Z-2.7 (Note)
X9111TV ZF
0 to +70
14 Ld TSSOP (4.4mm) (Pb-free)
X9111TV14I-2.7*
X9111TV G
-40 to +85
14 Ld TSSOP (4.4mm)
X9111TV14IZ-2.7* (Note)
X9111TV ZG
-40 to +85
14 Ld TSSOP (4.4mm) (Pb-free)
2.7 to 5.5
-40 to +85
14 Ld TSSOP (4.4mm)
-40 to +85
14 Ld TSSOP (4.4mm) (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Detailed Functional Diagram
VCC
Power On
Recall
HOLD
CS
DR0 DR1
SCK
Interface
and
Control
Circuitry
SO
SI
A0
A1
Data
Control
DR2 DR3
Wiper
Counter
Register
(WCR)
RH
100kΩ
1024-taps
RL
RW
WP
VSS
Circuit Level Applications
System Level Applications
• Vary the gain of a voltage amplifier
• Adjust the contrast in LCD displays
• Provide programmable dc reference voltages for
comparators and detectors
• Control the power level of LED transmitters in
communication systems
• Control the volume in audio circuits
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless
systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent systems
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits
2
FN8159.4
September 15, 2006
X9111
CHIP SELECT (CS)
Pin Descriptions
When CS is HIGH, the X9111 is deselected and the SO pin is at
high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state. CS LOW
enables the X9111, placing it in the active power mode. It
should be noted that after a power-up, a HIGH to LOW
transition on CS is required prior to the start of any operation.
PIN
(TSSOP)
SYMBOL
1
SO
Serial Data Output
2
A0
Device Address
3
NC
No Connect
4
CS
Chip Select
HARDWARE WRITE PROTECT INPUT (WP)
5
SCK
Serial Clock
6
SI
Serial Data Input
The WP pin when LOW prevents nonvolatile writes to the
Data Registers.
7
VSS
System Ground
8
WP
Hardware Write Protect
RH, RL
9
A1
Device Address
The RH and RL pins are equivalent to the terminal connections
on a mechanical potentiometer.
10
HOLD
Device Select. Pause the Serial Bus
11
RW
Wiper Terminal of the Potentiometer
12
RH
High Terminal of the Potentiometer
13
RL
Low Terminal of the Potentiometer
14
VCC
FUNCTION
Potentiometer Pins
RW
The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.
Bias Supply Pins
System Supply Voltage
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
Pin Descriptions
The VCC pin is the system supply voltage. The VSS pin is
the system ground.
Bus Interface Pins
SERIAL OUTPUT (SO)
SO is a serial data output pin. During a read cycle, data is
shifted out on this pin. Data is clocked out by the falling edge
of the serial clock.
SERIAL INPUT (SI)
Other Pins
NO CONNECT (NC)
Pin should be left open. This pin is used for Intersil
manufacturing and test purposes.
SI is the serial data input pin. All opcodes, byte addresses and
data to be written to the pots and pot registers are input on this
pin. Data is latched by the rising edge of the serial clock.
Principles of Operation
SERIAL CLOCK (SCK)
Serial Interface
The SCK input is used to clock data into and out of the
X9111.
The X9111 supports the SPI interface hardware conventions.
The device is accessed via the SI input with data clocked-in on
the rising SCK. CS must be LOW and the HOLD and WP pins
must be HIGH during the entire operation.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the serial
communication with the controller without resetting the serial
sequence. To pause, HOLD must be brought LOW while SCK is
LOW. To resume communication, HOLD is brought HIGH, again
while SCK is LOW. If the pause feature is not used, HOLD should
be held HIGH at all times.
DEVICE ADDRESS (A0, A1)
The address inputs are used to set the 8-bit slave address. A
match in the slave address serial data stream must be made
with the address input (A1–A0) in order to initiate
communication with the X9111.
3
Device Description
The SO and SI pins can be connected together, since they
have three state outputs. This can help to reduce system pin
count.
Array Description
The X9111 is comprised of a resistor array (see Figure 1).
The array contains the equivalent of 1023 discrete resistive
segments that are connected in series. The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (RH and RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (RW)
output. Within the individual array only one switch may be
turned on at a time.
FN8159.4
September 15, 2006
X9111
Serial Data Path
RH
Serial
Bus
Input
From Interface
Circuitry
Register 0
(DR0)
Register 1
(DR1)
10
Register 2
(DR2)
10
Register 3
(DR3)
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
C
O
U
N
T
E
R
D
E
C
O
D
E
If WCR = 000[HEX] then RW = RL
If WCR = 3FF[HEX] then RW = RH
RL
R
W
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
These switches are controlled by a Wiper Counter Register
(WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to
select, and enable, one of 1024 switches.
Wiper Counter Register (WCR)
The X9111 contains a Wiper Counter Register (see Table 1)
for the XDCP potentiometer. The WCR is equivalent to a
serial-in, parallel-out register/counter with its outputs
decoded to select one of 1024 switches along its resistor
array. The contents of the WCR can be altered in one of
three ways: (1) it may be written directly by the host via the
write Wiper Counter Register instruction (serial load); (2) it
may be written indirectly by transferring the contents of one
of four associated Data Registers via the XFR Data Register;
(3) it is loaded with the contents of its Data Register zero
(DR0) upon power-up.
The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9111 is powered-down.
Although the register is automatically loaded with the value
in R0 upon power-up, this may be different from the value
present at power-down. Power-up guidelines are
recommended to ensure proper loadings of the R0 value into
the WCR.
Data Registers (DR3 to DR0)
The potentiometer has four 10-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the Wiper Counter Register. All operations
changing data in one of the Data Registers is a nonvolatile
operation and will take a maximum of 10ms.
4
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
A DR[9:0] is used to store one of the 1024 wiper position (0
~1023). Table 2
Status Register (SR)
This 1-bit status register is used to store the system status
(see Table 3).
WIP: Write In Progress status bit, read only.
• When WIP=1, indicates that high-voltage write cycle is in
progress.
• When WIP=0, indicates that no high-voltage write cycle is
in progress.
Device Instructions
Identification Byte (ID and A)
The first byte sent to the X9111 from the host, following a CS
going HIGH to LOW, is called the Identification Byte. The
most significant four bits of the slave address are a device
type identifier. The ID[3:0] bits is the device ID for the X9111;
this is fixed as 0101[B] (refer to Table 4).
The A1–A0 bits in the ID byte are the internal slave address.
The physical device address is defined by the state of the
A1–A0 input pins. The slave address is externally specified
by the user. The X9111 compares the serial data stream with
the address input state; a successful compare of the address
FN8159.4
September 15, 2006
X9111
bits is required for the X9111 to successfully continue the
command sequence. Only the device whose slave address
matches the incoming device address sent by the master
executes the instruction. The A1–A0 inputs can be actively
driven by CMOS input signals or tied to VCC or VSS. The
R/W bit is used to set the device to either read or write
mode.
Instruction Byte and Register Selection
The next byte sent to the X9111 contains the instruction and
register pointer information. The three most significant bits
are used provide the instruction opcode (I[2:0]). The RB and
RA bits point to one of the four registers. The format is
shown in Table 5.
TABLE 1. WIPER LATCH, WL (10-BIT), WCR9–WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V)
WCR9
WCR8
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
V
V
V
V
V
V
V
V
V
V
(MSB)
(LSB)
TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE, NV)
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
MSB
LSB
TABLE 3. STATUS REGISTER, SR (1-BIT)
WIP
(LSB)
TABLE 3. IDENTIFICATION BYTE FORMAT
Internal Slave
Address
Device Type
Identifier
ID3
ID2
ID1
ID0
0
1
0
1
0
A1
A0
(MSB)
Read or
Write Bit
R/W
(LSB)
TABLE 4. INSTRUCTION BYTE FORMAT
Register
Selection
Instruction
Opcode
I2
I1
I0
(MSB)
5
0
RB
RA
RB
RA
REGISTER
0
0
1
1
0
1
0
1
DR0
DR1
DR2
DR3
0
0
(LSB)
FN8159.4
September 15, 2006
X9111
host and the X9111; either between the host and one of the
Data Registers or directly between the host and the Wiper
Counter Register. These instructions are:
Five of the seven instructions are four bytes in length. These
instructions are:
• Read Wiper Counter Register – read the current wiper
position of the selected pot,
• XFR Data Register to Wiper Counter Register – This
transfers the contents of one specified Data Register to
the associated Wiper Counter Register.
• Write Wiper Counter Register – change current wiper
position of the selected pot,
• Read Data Register – read the contents of the selected
data register;
• XFR Wiper Counter Register to Data Register – This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
• Write Data Register – write a new value to the selected
data register.
See Instruction format for more details.
Write in Process (WIP bit)
• Read Status – This command returns the contents of the
WIP bit which indicates if the internal write cycle is in
progress.
The contents of the Data Registers are saved to nonvolatile
memory when the CS pin goes from LOW to HIGH after a
complete write sequence is received by the device. The
progress of this internal write operation can be monitored by
a Write In Process bit (WIP). The WIP bit is read with a Read
Status command (see Figure 4).
The basic sequence of the four byte instructions is illustrated
in Figure 3. These four-byte instructions exchange data
between the WCR and one of the Data Registers. A transfer
from a Data Register to a WCR is essentially a write to a
static RAM, with the static RAM controlling the wiper
position. The response of the wiper to this action will be
delayed by tWRL. A transfer from the WCR (current wiper
position), to a Data Register is a write to nonvolatile memory
and takes a minimum of tWR to complete. The transfer can
occur between the potentiometer and one of its associated
registers. The Read Status Register instruction is the only
unique format (see Figure 4).
Power Up and Down Requirements
There are no restrictions on the power-up condition of VCC
and the voltages applied to the potentiometer pins provided
that the VCC is always more positive than or equal to the
voltages at RH, RL, and RW, i.e., VCC ≥ RH, RL, RW. There
are no restrictions on the power-down condition. However,
the datasheet parameters for the DCP do not apply until
1millisecond after VCC reaches its final value.
Two instructions require a two-byte sequence to complete
(see Figure 2). These instructions transfer data between the
CS
SCK
SI
0
1
0
1
0
ID3
ID2
ID1
ID0
0
Device ID
0
A1
A0
R/W
Internal
Address
I2
I1
I0
RB
Instruction
Opcode
RA
0
0
0
0
Register
Address
FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE
CS
SCK
SI
0
1
0
1
ID3 ID2 ID1 ID0 0
Device ID
0
0
0
A1 A0 R/W I2 I1
Internal
Address
X
X
0
0 X
I0 0 RB RA 0 0
Instruction
Opcode
Register
Address
X
X X
X X
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
Wiper
Position
FIGURE 3. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS)
6
FN8159.4
September 15, 2006
X9111
CS
SCK
SI
0
1
0
1
1
0
ID3 ID2 ID1 ID0 0 A1 A0 R/W I2 I1
Internal
Address
Device ID
0
0
0 RB RA 0
0
0
I0
Instruction
Opcode
X
X
X
X X X X
X X X
0
0
0
0 0
0 0
WIP
Register
Address
Status
Bit
FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTERS)
TABLE 5. INSTRUCTION SET
INSTRUCTION SET
INSTRUCTION
R/W
I3
I2
I1
0
RB
RA
0
0
OPERATION
Read Wiper Counter
Register
1
1
0
0
0
0
0
0
0
Read the contents of the Wiper Counter
Register
Write Wiper Counter
Register
0
1
0
1
0
0
0
0
0
Write new value to the Wiper Counter
Register
Read Data Register
1
1
0
1
0
1/0
1/0
0
0
Read the contents of the Data Register
pointed to RB-RA
Write Data Register
0
1
1
0
0
1/0
1/0
0
0
Write new value to the Data Register
pointed to RB-RA
XFR Data Register to
Wiper Counter Register
1
1
1
0
0
1/0
1/0
0
0
Transfer the contents of the Data Register
pointed to by RB-RA to the Wiper Counter
Register
XFR Wiper Counter
Register to Data Register
0
1
1
1
0
1/0
1/0
0
0
Transfer the contents of the Wiper Counter
Register to the Data Register pointed to by
RB-RA
Read Status (WIP bit)
1
0
1
0
0
0
0
0
1
Read the status of the internal write cycle,
by checking the WIP bit (read status
register).
NOTE: 1/0 = data is one or zero
Instruction Format
Read Wiper Counter Register (WCR)
0
1
0
1
Device
Addresses
0
A1 A0
R/ W = 1
CS
Falling
Edge
Device Type
Identifier
Instruction
Opcode
1
0
0
Register
Addresses
0
0
0
0
0
Wiper Position
(Sent by X9111 on SO)
X
X
X
X
X
W
X C
R
9
Wiper Position
(sent by X9111 on SO)
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
CS
W Rising
C Edge
R
0
Write Wiper Counter Register (WCR)
0
1
0
1
Device
Addresses
0 A1 A0
7
R/ W = 0
CS
Falling
Edge
Device Type
Identifier
Instruction
Opcode
1
0
1
0
Register
Addresses
0
0
0
0
Wiper Position
(Sent by Master on SI)
X
X
X
X
X
W
C
X R
9
Wiper Position
(Sent by Master on SI)
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
CS
W Rising
C Edge
R
0
FN8159.4
September 15, 2006
X9111
Read Data Register (DR)
Device
Addresses
Instruction
Opcode
R/ W = 1
CS
Falling
Edge
Device
Type
Identifier
0 1 0 1 0 A1 A0
1
0
1
Register
Addresses
0
RB RA
Wiper Position
(Sent by X9111 on SO)
0
0
X
X
X
X
X
Wiper Position
(sent by X9111 on SO)
W W W W W W W W W W
C C C C C C C C C C
X
R R R R R R R R R R
9 8 7 6 5 4 3 2 1 0
CS
Rising
Edge
CS
Falling
Edge
0
1
0
Device
Addresses
1
0 A1 A0
Instruction
Opcode
R/ W = 0
Device Type
Identifier
1
1
0
Register
Addresses
R
B
0
R
A
0
Wiper Position or Data
(Sent by Master on SI)
W
C
X X X X X X
R
9
0
Wiper Position or Data
(Sent by Master on SI)
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
CS
Rising
W
C Edge
R
0
HIGH-VOLTAGE
WRITE CYCLE
Write Data Register (DR)
Transfer Data Register (DR) to Wiper Counter Register (WCR)
0
1
0
Device
Addresses
1
0
A1 A0
Instruction
Opcode
R/ W = 1
CS
Falling
Edge
Device Type
Identifier
1
1
0
Register
Addresses
0
RB RA
0
0
CS
Rising
Edge
Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS
Falling
Edge
0
1
0
1
Device
Addresses
0
R/ W = 0
Device Type
Identifier
A1 A0
Instruction
Opcode
1
1
1
Register Addresses
0
RB
RA
0
0
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
Read Status Register (SR)
CS
Falling
Edge
0
1
0
1
Device
Addresses
0 A1 A0
R/ W = 1
Device Type
Identifier
Instruction
Opcode
0
1
0
0
Register
Addresses
0
0
0
1
Status Data
(Sent by Slave on SO)
X
X
X
X
X
X
X
Status Data
(Sent by Slave on SO)
X
0
0
0
0
0
0
0
WI
P
CS
Rising
Edge
NOTES:
1. “A0 and A1”: stand for the device address sent by the master.
2. WCRx refers to wiper position data in the Wiper Counter Register
3. “X”: Don’t Care.
8
FN8159.4
September 15, 2006
X9111
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on SCK any address input
with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
∆V = | (VH–VL) |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to Vcc
Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . +300°C
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VCC) Limits
X9111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V±10%
X9111-2.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Characteristics Over recommended industrial operation conditions unless otherwise stated.
SYMBOL
RTOTAL
PARAMETER
TEST CONDITIONS
MIN
End to End Resistance
TYP
100
End to End Resistance Tolerance
Power Rating
+25°C, each pot
IW
Wiper Current
RW
Wiper Resistance
VTERM
%
50
mW
±3
mA
Ω
Wiper Current = ±50µA,
VCC = 3V
150
300
Ω
VCC
V
Noise
Ref: 1V
VSS
-120
dBV
1.6
%
Rw(n)(actual) -Rw(n)(expected), where
n = 8 to 1006
Rw(n)(actual) -Rw(n)(expected) (Note 4)
±1.5
Rw(m + 1) -[Rw(m) + MI], where m = 8 to
1006
Rw(m + 1) -[Rw(m) + MI] (Note 4)
Temperature Coefficient of RTOTAL
±0.5
±1
MI (Note 3)
±2.0
MI (Note 3)
±0.5
MI (Note 3)
±1.0
MI (Note 3)
±300
Ratiometric Temp. Coefficient
Potentiometer Capacitancies
±20
110
Resolution
CH/CL/CW
kΩ
40
VSS = 0V
Relative Linearity (Note 2)
UNITS
Wiper Current = ±50µA,
VCC = 5V
Voltage on any RH or RL Pin
Absolute Linearity (Note 1)
MAX
ppm/°C
20
See Macro model
10/10/25
ppm/°C
pF
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
3. MI = RTOT/1023 or (RH – RL)/1023, single pot
4. n = 0, 1, 2, …,1023; m =0, 1, 2, …, 1022.
5. ESD Rating on RH, RL, RW pins is 1.5kV (HBM, 1.0µA leakage maximum), ESD rating on all other pins is 2.0kV.
9
FN8159.4
September 15, 2006
X9111
D.C. Operating Characteristics Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNITS
400
µA
5
mA
ICC1
VCC supply current
(active)
fSCK = 2.5 MHz, SO = Open, VCC = 5.5V
Other Inputs = VSS
ICC2
VCC supply current
(nonvolatile write)
fSCK = 2.5MHz, SO = Open, VCC = 5.5V
Other Inputs = VSS
ISB
VCC current (standby)
SCK = SI = VSS, Addr. = VSS,
CS = VCC = 5.5V
3
µA
ILI
Input leakage current
VIN = VSS to VCC
10
µA
ILO
Output leakage current
VOUT = VSS to VCC
10
µA
VIH
Input HIGH voltage
VCC x 0.7
VCC + 1
V
VIL
Input LOW voltage
-1
VCC x 0.3
V
VOL
Output LOW voltage
IOL = 3mA
0.4
V
VOL
Output LOW voltage
IOH = -1mA, VCC ≥ +3V
VCC - 0.8
V
VOL
Output LOW voltage
IOH = -0.4mA, VCC ≤ +3V
VCC - 0.4
V
1
Endurance And Data Retention
PARAMETER
MIN
UNITS
Minimum Endurance
100,000
Data changes per bit per register
Data Retention
100
years
Capacitance
SYMBOL
TEST
CIN/OUT (Note 6) Input/Output capacitance (SI)
COUT (Note 6)
CIN (Note 6)
Output capacitance (SO)
Input capacitance (A0, CS, WP, HOLD, and SCK)
TEST CONDITIONS
MAX
UNITS
VOUT = 0V
8
pF
VOUT = 0V
8
pF
VIN = 0V
6
pF
Power-Up Timing
SYMBOL
tr VCC (Note 6)
PARAMETER
VCC power-up rate
MIN
MAX
UNITS
0.2
50
V/ms
tPUR (Note 7)
Power-up to initiation of read operation
1
ms
tPUW (Note 7)
Power-up to initiation of write operation
50
ms
NOTES:
6. This parameter is not 100% tested.
7. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These
parameters are not 100% tested.
A.C. Test Conditions
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
10
FN8159.4
September 15, 2006
X9111
Equivalent A.C. Load Circuit
3V
5V
1462Ω
SPICE Macromodel
1382Ω
RTOTAL
SO pin
SO pin
2714Ω
1217Ω
100pF
RL
RH
CW
CL
10pF
100pF
CL
10pF
25pF
RW
AC Timing
SYMBOL
PARAMETER
MIN
MAX
UNITS
2.0
MHz
fSCK
SSI/SPI clock frequency
tCYC
SSI/SPI clock cycle time
400
ns
tWH
SSI/SPI clock high time
150
ns
tWL
SSI/SPI clock low time
150
ns
tLEAD
Lead time
150
ns
tLAG
Lag time
150
ns
tSU
SI, SCK, HOLD and CS input setup time
50
ns
tH
SI, SCK, HOLD and CS input hold time
50
ns
tRI
SI, SCK, HOLD and CS input rise time
50
ns
tFI
SI, SCK, HOLD and CS input fall time
50
ns
500
ns
100
ns
tDIS
SO output disable time
0
tV
SO output valid time
tHO
SO output hold time
tRO
SO output rise time
50
ns
tFO
SO output fall time
50
ns
tHOLD
0
ns
HOLD time
400
ns
tHSU
HOLD setup time
50
ns
tHH
HOLD hold time
50
ns
tHZ
HOLD low to output in high Z
100
ns
tLZ
HOLD high to output in low Z
100
ns
TI
Noise suppression time constant at
SI, SCK, HOLD and CS inputs
20
ns
tCS
CS deselect time
100
ns
tWPASU
WP, A0, A1 setup time
0
ns
tWPAH
WP, A0, A1 hold time
0
ns
11
FN8159.4
September 15, 2006
X9111
High-voltage Write Cycle Timing
SYMBOL
tWR
PARAMETER
TYP
MAX
UNITS
5
10
ms
MIN
MAX
UNITS
Wiper response time after the third (last) power supply is stable
5
10
µs
Wiper response time after instruction issued (all load instructions)
5
10
µs
High-voltage write cycle time (store instructions)
XDCP Timing
SYMBOL
tWRPO
tWRL
PARAMETER
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
12
FN8159.4
September 15, 2006
X9111
Timing Diagrams
Input Timing
tCS
CS
SCK
tSU
tH
...
tWH
tWL
...
MSB
SI
tLAG
tCYC
tLEAD
tRI
tFI
LSB
High Impedance
SO
Output Timing
CS
SCK
...
tV
tDIS
...
MSB
SO
SI
tHO
LSB
ADDR
Hold Timing
CS
tHSU
tHH
SCK
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
13
FN8159.4
September 15, 2006
X9111
XDCP Timing (for All Load Instructions)
CS
SCK
...
tWRL
SI
...
MSB
LSB
RW
SO
High Impedance
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
tWPASU
tWPAH
WP
A0
A1
Applications information
Basic Configurations of Electronic Potentiometers
+VR
VR
RW
I
Three terminal Potentiometer;
Variable voltage divider
14
Two terminal Variable Resistor;
Variable current
FN8159.4
September 15, 2006
X9111
Application Circuits
Noninverting Amplifier
VS
Voltage Regulator
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
R1
Comparator with Hysterisis
R2
VS
VS
–
+
100kΩ
–
VO
+
+12V
10kΩ
R1
}
10kΩ
}
TL072
10kΩ
VO
R2
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
-12V
15
FN8159.4
September 15, 2006
X9111
Application Circuits (Continued)
Attenuator
Filter
C
VS
R2
R1
VO
–
–
VS
+
R
VO
+
R3
R4
R2
R1 = R2 = R3 = R4 = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
VO = G VS
-1/2 ≤ G ≤ +1/2
R2
}
VS
R1
}
Inverting Amplifier
Equivalent L-R Circuit
R2
C1
–
VS
VO
+
+
–
R1
ZIN
VO = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
Function Generator
C
R2
–
+
R1
–
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
16
FN8159.4
September 15, 2006
X9111
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
SYMBOL
3
0.05(0.002)
-A-
INCHES
GAUGE
PLANE
-B1
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
B M
0.25
0.010
SEATING PLANE
L
A
D
-C-
α
e
A1
b
A2
c
0.10(0.004)
0.10(0.004) M
C A M
B S
MIN
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
MILLIMETERS
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.041
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.195
0.199
4.95
5.05
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
NOTES:
MAX
α
14
0o
14
7
8o
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
FN8159.4
September 15, 2006
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