DATASHEET

DATASHEET
Single Supply/Low Power/256-Tap/SPI Bus, Quad
Digitally-Controlled (XDCP™) Potentiometer
X9251
Features
The X9251 integrates four digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated circuit.
• Four potentiometers in one package
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
SPI bus interface. Each potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and four nonvolatile
Data Registers that can be directly written to and read by the
user. The content of the WCR controls the position of the wiper.
At power-up, the device recalls the content of the default Data
Registers of each DCP (DR00, DR10, DR20, and DR30) to the
corresponding WCR.
• SPI serial interface for write, read, and transfer operations of
the potentiometer
• 256 resistor taps–0.4% resolution
• Wiper resistance: 100Ω typical at VCC = 5V
• 4 Nonvolatile data registers for each potentiometer
• Nonvolatile storage of multiple wiper positions
• Standby current <5µA max
• VCC: 2.7V to 5.5V operation
• 50kΩ version of total resistance
The XDCP can be used as a three terminal potentiometer or as
a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• 100 year data retention
• Single supply version of X9250
• Endurance: 100,000 data changes per bit per register
• 24 Ld SOIC, 24 Ld TSSOP
• Low power CMOS
• Pb-free (RoHS compliant)
HOLD
A1
SPI
Interface
A0
SO
SI
RH1
RH0
VCC
WCR0
DR00
DR01
DR02
DR03
POWER UP,
INTERFACE
CONTROL
AND
STATUS
DCP0
WCR1
DR10
DR11
DR12
DR13
DCP1
RH3
RH2
WCR2
DR20
DR21
DR22
DR23
DCP2
WCR3
DR30
DR31
DR32
DR33
DCP3
SCK
CS
VSS
WP
RW0
RL0
RW1
RL1
RW2
RL2
RW3
RL3
FIGURE 1. FUNCTIONAL DIAGRAM
December 3, 2014
FN8166.6
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005-2007, 2014. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
X9251
Circuit Level Applications
System Level Applications
• Vary the gain of a voltage amplifier
• Adjust the contrast in LCD displays
• Provide programmable DC reference voltages for comparators
and detectors
• Control the power level of LED transmitters in communication
systems
• Control the volume in audio circuits
• Set and regulate the DC biasing point in an RF power amplifier
in wireless systems
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter
circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent systems
• Vary the frequency and duty cycle of timer ICs
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits
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FN8166.6
December 3, 2014
X9251
Ordering Information
PART
MARKING
PART NUMBER (Notes 2, 3)
VCC LIMITS
(V)
POTENTIOMETER
ORGANIZATION
(kΩ)
5 ±10%
50
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
X9251US24Z (Note 1)
X9251US Z
0 to +70
24 Ld SOIC (300 mil)
M24.3
X9251US24IZ (Note 1)
X9251US ZI
-40 to +85
24 Ld SOIC (300 mil)
M24.3
X9251UV24Z
X9251UV Z
0 to +70
24 Ld TSSOP (4.4mm)
M24.173
X9251UV24IZ
X9251UV ZI
-40 to +85
24 Ld TSSOP (4.4mm)
M24.173
-40 to +85
24 Ld SOIC (300 mil)
M24.3
0 to +70
24 Ld SOIC (300 mil)
M24.3
0 to +70
24 Ld TSSOP (4.4mm)
M24.173
-40 to +85
24 Ld TSSOP (4.4mm)
M24.173
X9251US24IZ-2.7 (Note 1) X9251US ZG
2.7 to 5.5
X9251US24Z-2.7 (Note 1) X9251US ZG
X9251UV24Z-2.7
X9251UV ZF
X9251UV24IZ-2.7 (Note 1) X9251UV ZG
NOTES:
1. Add "T1" suffix for tape and reel.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for X9251. For more information on MSL, please see tech brief TB363
Pin Configuration
Pin Descriptions
X9251
(24 LD SOIC/TSSOP)
TOP VIEW
PIN
(SOIC)
SYMBOL
1
SO
Serial Data Output for SPI bus
Device Address for SPI bus (see Note 4)
FUNCTION
SO
1
24
HOLD
2
A0
A0
2
23
SCK
RW3
3
Wiper Terminal of DCP3
3
22
RL2
RW3
RH3
4
High Terminal of DCP3
21
RH2
RH3
4
RL3
20
RL3
Low Terminal of DCP3
5
RW2
5
NC
VCC
System Supply Voltage
19
NC
7
6
VCC
7
18
VSS
8
RL0
Low Terminal of DCP0
RL0
8
17
RW1
9
RH0
High Terminal of DCP0
RH0
9
16
RH1
10
RW0
Wiper Terminal of DCP0
11
CS
SPI bus. Chip Select active low input
WP
Hardware Write Protect - active low
X9251
RW0
10
15
RL1
CS
11
14
A1
12
WP
12
13
SI
13
SI
Serial Data Input for SPI bus
14
A1
Device Address for SPI bus (see Note 4)
15
RL1
Low Terminal of DCP1
16
RH1
High Terminal of DCP1
17
RW1
Wiper Terminal of DCP1
18
VSS
System Ground
20
RW2
Wiper Terminal of DCP2
21
RH2
High Terminal of DCP2
22
RL2
Low Terminal of DCP2
23
SCK
Serial Clock for SPI bus
24
HOLD
6, 19
NC
Device select. Pauses the SPI serial bus.
No Connect
NOTE:
4. A0 and A1 device address pins must be tied to a logic level.
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FN8166.6
December 3, 2014
X9251
Functional Pin Descriptions
Bus Interface Pins
Potentiometer Pins
SERIAL OUTPUT (SO)
RH, RL
SO is a serial data output pin. During a read cycle, data is shifted
out on this pin. Data is clocked out by the falling edge of the
serial clock.
The RH and RL pins are equivalent to the terminal connections on
a mechanical potentiometer. Since there are 4 potentiometers,
there are 4 sets of RH and RL such that RH0 and RL0 are the
terminals of DCP0 and so on.
SERIAL INPUT (SI)
SI is the serial data input pin. All opcodes, byte addresses and
data to be written to the device registers are input on this pin.
Data is latched by the rising edge of the serial clock.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the X9251.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select the device.
Once the part is selected and a serial sequence is underway,
HOLD may be used to pause the serial communication with the
controller without resetting the serial sequence. To pause, HOLD
must be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while SCK is LOW.
If the pause feature is not used, HOLD should be held HIGH at all
times.
DEVICE ADDRESS (A1 AND A0)
The address inputs are used to set the two least significant bits of
the slave address. A match in the slave address serial data
stream must be made with the address input in order to initiate
communication with the X9251. Device pins A1 and A0 must be
tied to a logic level which specifies the internal address of the
device, see Figures 3, 4, 5, 6 and 7.
CHIP SELECT (CS)
When CS is HIGH, the X9251 is deselected and the SO pin is at
high impedance, and (unless an internal write cycle is underway)
the device is in the standby state. CS LOW enables the X9251,
placing it in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is required prior to
the start of any operation.
RW
The wiper pins are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4 potentiometers,
there are 4 sets of RW such that RW0 is the terminals of DCP0
and so on.
Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
The VCC pin is the system supply voltage. The VSS pin is the
system ground.
Other Pins
NO CONNECT
No connect pins should be left floating. These pins are used for
Intersil manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin, when LOW, prevents nonvolatile writes to the Data
Registers.
Principles of Operation
The X9251 is an integrated circuit incorporating four DCPs and
their associated registers and counters, and a serial interface
providing direct communication between a host and the
potentiometers.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each DCP are
equivalent to the fixed terminals of a mechanical potentiometer
(RH and RL pins). The RW pin is an intermediate node, equivalent
to the wiper terminal of a mechanical potentiometer.
The position of the wiper terminal within the DCP is controlled by
an 8-bit volatile Wiper Counter Register (WCR).
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FN8166.6
December 3, 2014
X9251
One of Four Potentiometers
#: 0, 1, 2, or 3
RH
SERIAL
BUS
INPUT
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
DR#0
DR#1
8
8
DR#2
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR#)
DR#3
COUNTER
--DECODE
DCP
CORE
RW
INC/DEC
LOGIC
IF WCR = 00[H] then RW is closest to RL
IF WCR = FF[H] then RW is closest to RH
UP/DN
MODIFIED SCK
UP/DN
CLK
RL
FIGURE 2. DETAILED POTENTIOMETER BLOCK DIAGRAM
Power-Up and Down Recommendations
There are no restrictions on the power-up or power-down
conditions of VCC and the voltages applied to the potentiometer
pins provided that VCC is always more positive than or equal to
VH, VL, and VW (i.e., VCC  VH, VL, VW). The VCC ramp rate
specification is always in effect.
Wiper Counter Register (WCR)
The X9251 contains four Wiper Counter Registers, one for each
potentiometer. The Wiper Counter Register can be envisioned as
a 8-bit parallel and serial load counter with its outputs decoded
to select one of 256 wiper positions along its resistor array. The
contents of the WCR can be altered in four ways: it may be
written directly by the host via the Write Wiper Counter Register
instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated data registers
via the XFR Data Register instruction (parallel load); it can be
modified one step at a time by the Increment/Decrement
instruction (see “Instruction Format” on page 10 for more
details). Finally, it is loaded with the contents of its Data Register
zero (DR#0) upon power-up (see Figure 2).
The wiper counter register is a volatile register; that is, its
contents are lost when the X9251 is powered down. Although the
register is automatically loaded with the value in DR#0 upon
power-up, this may be different from the value present at
power-down. Power-up guidelines are recommended to ensure
proper loadings of the DR#0 value into the WCR#.
Data Registers (DR)
Each of the four DCPs has four 8-bit nonvolatile Data Registers.
These can be read or written directly by the host. Data can also
be transferred between any of the four Data Registers and the
associated Wiper Counter Register. All operations changing data
in one of the Data Registers is a nonvolatile operation and takes
a maximum of 10ms.
If the application does not require storage of multiple settings for
the potentiometer, the Data Registers can be used as regular
memory locations for system parameters or user preference data.
Bits [7:0] are used to store one of the 256 wiper positions or data
(0 ~ 255).
Status Register (SR)
This 1-bit Status Register is used to store the system status.
WIP: Write In Progress status bit, read only.
• WIP = 1, indicates that high-voltage write cycle is in progress.
• WIP = 0, indicates that no high-voltage write cycle is in
progress.
TABLE 1. WIPER COUNTER REGISTER, WCR (8-BIT), WCR[7:0]: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE)
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
(MSB)
WCR0
(LSB)
TABLE 2. DATA REGISTER, DR (8-BIT), DR[7:0]: USED TO STORE WIPER POSITIONS OR DATA (NONVOLATILE)
BIT 7
BIT 6
BIT 5
(MSB)
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BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
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FN8166.6
December 3, 2014
X9251
Serial Interface
The least significant four bits of the Identification Byte are the
Slave Address bits, AD[3:0]. For the X9251, A3 is 0, A2 is 0, A1 is
the logic value at the input pin A1, and A0 is the logic value at the
input pin A0. Only the device which Slave Address matches the
incoming bits sent by the master executes the instruction. The A1
and A0 inputs can be actively driven by CMOS input signals or
tied to VCC or VSS.
The X9251 supports the SPI interface hardware conventions. The
device is accessed via the SI input with data clocked in, on the
rising SCK. CS must be LOW and the HOLD and WP pins must be
HIGH during the entire operation.
The SO and SI pins can be connected together, since they have
three-state outputs. This can help to reduce system pin count.
Instruction Byte
Identification Byte
The next byte sent to the X9251 contains the instruction and
register pointer information. The four most significant bits are
used to provide the instruction opcode (I[3:0]). The RB and RA
bits point to one of the four Data Registers of each associated
XDCP. The least two significant bits point to one of four Wiper
Counter Registers or DCPs. The format is shown below in Table 4.
The first byte sent to the X9251 from the host, following a CS
going HIGH to LOW, is called the Identification Byte. The most
significant four bits of the Identification Byte are a Device Type
Identifier, ID[3:0]. For the X9251, this is fixed as 0101 (refer to
Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT
DEVICE TYPE IDENTIFIER
SLAVE ADDRESS
ID3
ID2
ID1
ID0
A3
A2
A1
A0
0
1
0
1
0
0
Pin A1
Logic Value
Pin A0
Logic Value
(LSB)
(MSB)
TABLE 4. INSTRUCTION BYTE FORMAT
INSTRUCTION OPCODE
I3
I2
REGISTER SELECTION
I1
I0
RB
RA
DCP SELECTION
(WCR SELECTION)
P1
(MSB)
P0
(LSB)
Data Register Selection
REGISTER
RB
RA
DR#0
0
0
DR#1
0
1
DR#2
1
0
DR#3
1
1
#: 0, 1, 2, or 3
TABLE 5. INSTRUCTION SET
INSTRUCTION SET
INSTRUCTION
I3
I2
I1
I0
RB
RA
P1
P0
Read Wiper Counter Register
1
0
0
1
0
0
1/0
1/0
Read the contents of the Wiper Counter Register
pointed to by P1, P0
Write Wiper Counter Register
1
0
1
0
0
0
1/0
1/0
Write new value to the Wiper Counter Register
pointed to by P1, P0
Read Data Register
1
0
1
1
1/0
1/0
1/0
1/0
Read the contents of the Data Register pointed to by
P1, P0 and RB, RA
Write Data Register
1
1
0
0
1/0
1/0
1/0
1/0
Write new value to the Data Register pointed to by P1,
P0 and RB, RA
XFR Data Register to
Wiper Counter Register
1
1
0
1
1/0
1/0
1/0
1/0
Transfer the contents of the Data Register pointed to by
P1, P0 and RB, RA to its associated Wiper Counter
Register
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OPERATION
FN8166.6
December 3, 2014
X9251
TABLE 5. INSTRUCTION SET (Continued)
INSTRUCTION SET
INSTRUCTION
I3
I2
I1
I0
RB
RA
P1
P0
OPERATION
XFR Wiper Counter
Register to Data Register
1
1
1
0
1/0
1/0
1/0
1/0
Transfer the contents of the Wiper Counter Register
pointed to by P1, P0 to the Data Register pointed to
by RB, RA
Global XFR Data Registers to Wiper
Counter Registers
0
0
0
1
1/0
1/0
0
0
Transfer the contents of the Data Registers pointed to
by RB, RA of all four pots to their respective Wiper
Counter Registers
Global XFR Wiper Counter Registers
to Data Register
1
0
0
0
1/0
1/0
0
0
Transfer the contents of both Wiper Counter Registers
to their respective data Registers pointed to by RB, RA
of all four pots
Increment/Decrement
Wiper Counter Register
0
0
1
0
0
0
1/0
1/0
Enable Increment/decrement of the Control Latch
pointed to by P1, P0
NOTE: 1/0 = data is one or zero
Instructions
Four of the nine instructions are three bytes in length. These
instructions are:
• Read Wiper Counter Register – read the current wiper position
of the selected potentiometer
• Write Wiper Counter Register – change current wiper position
of the selected potentiometer
• Read Data Register – read the contents of the selected Data
Register
• Write Data Register – write a new value to the selected Data
Register
• Read Status – this command returns the contents of the WIP
bit which indicates if the internal write cycle is in progress
The basic sequence of the three-byte instructions is illustrated in
Figure 4. These three-byte instructions exchange data between
the WCR and one of the Data Registers. A transfer from a Data
Register to a WCR is essentially a write to a static RAM, with the
static RAM controlling the wiper position. The response of the
wiper to this action is delayed by tWRL. A transfer from the WCR
(current wiper position), to a Data Register is a write to
nonvolatile memory and takes a minimum of tWR to complete.
The transfer can occur between one of the four potentiometer’s
WCR, and one of its associated registers, DRs; or it may occur
globally, where the transfer occurs between all potentiometers
and one associated register. The Read Status Register instruction
is the only unique format (see Figure 6).
Four instructions require a two-byte sequence to complete. These
instructions transfer data between the host and the X9251;
either between the host and one of the data registers or directly
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between the host and the Wiper Counter Register. These
instructions are:
• XFR Data Register to Wiper Counter Register – This transfers
the contents of one specified Data Register to the associated
Wiper Counter Register.
• XFR Wiper Counter Register to Data Register – This transfers
the contents of the specified Wiper Counter Register to the
specified associated Data Register.
• Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
• Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper Counter
Registers to the specified associated Data Registers.
Increment/Decrement Command
The final command is Increment/Decrement (see Figures 7 and 8).
The Increment/Decrement command is different from the other
commands. Once the command is issued and the X9251 has
responded with an Acknowledge, the master can clock the
selected wiper up and/or down in one segment steps, thereby
providing a fine tuning capability to the host. For each SCK clock
pulse (tHIGH) while SI is HIGH, the selected wiper moves one
wiper position towards the RH terminal. Similarly, for each SCK
clock pulse while SI is LOW, the selected wiper moves one wiper
position towards the RL terminal. A detailed illustration of the
sequence and timing for this operation are shown. See
“Instruction Format” on page 10 for more details.
FN8166.6
December 3, 2014
X9251
CS
SCK
SI
0
1
0
1
0
0
ID3
ID2
ID1
ID0
0
0
A1
A0
INTERNAL
ADDRESS
DEVICE ID
I3
I2
I1
RB
I0
INSTRUCTION
OPCODE
RA
P1
REGISTER
ADDRESS
P0
DCP/WCR
ADDRESS
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
CS
SCK
SI
0
ID3
1
0
ID2
ID1
1
0
0
ID0
0
0
A1
A0
I3
I1
I0
INSTRUCTION
OPCODE
INTERNAL
ADDRESS
DEVICE ID
I2
RB RA P1 P0
D7
D6 D5 D4
D3
D2
D1 D0
DATA FOR WCR[7:0] OR DR[7:0]
REGISTER DCP/WCR
ADDRESS ADDRESS
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE; WRITE CASE
CS
SCK
SI
0
ID3
1
0
ID2
ID1
1
0
0
ID0
0
0
X
A1
A0
INTERNAL
ADDRESS
DEVICE ID
I3
I2
I1
I0
INSTRUCTION
OPCODE
RB RA P1 P0
X
X
X
X
X
X
X
DON’T CARE
REGISTER DCP/WCR
ADDRESS ADDRESS
S0
D7
D6 D5 D4
D3
D2
D1 D0
WCR[7:0]
OR
DATA REGISTER BIT [7:0]
FIGURE 5. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE, READ CASE
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X9251
CS
SCK
SI
0
ID3
1
0
ID2
ID1
1
0
0
ID0
0
0
1
A1
A0
INTERNAL
ADDRESS
DEVICE ID
I3
0
1
1
I2
I1
I0
INSTRUCTION
OPCODE
0
RB RA
0
0
0
0
0
P1 P0
0
WIP
REGISTER POT/WCR
ADDRESS ADDRESS
STATUS
BIT
FIGURE 6. THREE-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTER)
CS
SCK
SI
0
ID3
1
0
ID2
ID1
1
0
0
ID0
0
0
DEVICE ID
A1
A0
INTERNAL
ADDRESS
I2
I3
I1
I0
INSTRUCTION
OPCODE
RB RA P1 P0
REGISTER POT/WCR
ADDRESS ADDRESS
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
FIGURE 7. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
tWRID
SCK
SI
VOLTAGE OUT
RW
INC/DEC CMD ISSUED
FIGURE 8. INCREMENT/DECREMENT TIMING SPEC
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X9251
Instruction Format
Read Wiper Counter Register (WCR)
CS
FALLING
EDGE
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
0
0
A1
INSTRUCTION
OPCODE
A0
1
0
0
WCR
ADDRESSES
1
0
0
0
WIPER POSITION
(SENT BY X9251 ON SO)
W W W W W W W W
C C C C C C C C
R R R R R R R R
7 6 5 4 3 2 1 0
0
CS
RISING
EDGE
Write Wiper Counter Register (WCR)
CS
FALLING
EDGE
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
0
0
A1
INSTRUCTION
OPCODE
A0
1
0
1
WCR
ADDRESSES
0
0
0
0
DATA BYTE
(SENT BY HOST ON SI)
W W W W W W W W
C C C C C C C C
R R R R R R R R
7 6 5 4 3 2 1 0
0
CS
RISING
EDGE
Read Data Register (DR)
CS
FALLING
EDGE
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
0
0
A1
INSTRUCTION
OPCODE
A0
1
0
1
1
DR AND WCR
ADDRESSES
RB
RA
P1
DATA BYTE
(SENT BY X9271 ON SO)
P0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
CS
RISING
EDGE
Write Data Register (DR)
CS
FALLING
EDGE
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
0
0
A1
INSTRUCTION
OPCODE
A0
1
1
0
0
DR AND WCR
ADDRESSES
RB
RA
P1
DATA BYTE
(SENT BY HOST ON SI)
P0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
CS
RISING
EDGE
HIGH-VOLTAGE
WRITE CYCLE
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS FALLING
EDGE
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
0
0
A1
INSTRUCTION
OPCODE
A0
0
0
DR
ADDRESSES
0
1
RB
RA
0
CS RISING
EDGE
0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS
FALLING
EDGE
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
0
0
A1
A0
INSTRUCTION
OPCODE
1
0
0
0
DR
ADDRESSES
RB
RA
0
CS
RISING
EDGE
0
HIGH-VOLTAGE
WRITE CYCLE
Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS
FALLING
EDGE
DEVICE TYPE
IDENTIFIER
0
1
0
1
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DEVICE
ADDRESSES
0
0
10
A1
A0
INSTRUCTION
OPCODE
1
1
1
0
DR AND WCR
ADDRESSES
RB
RA
0
0
CS
RISING
EDGE
HIGH-VOLTAGE
WRITE CYCLE
FN8166.6
December 3, 2014
X9251
Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS FALLING
EDGE
DEVICE TYPE
IDENTIFIER
0
1
DEVICE
ADDRESSES
0
1
0
0
A1
INSTRUCTION
OPCODE
A0
1
1
0
DR AND WCR
ADDRESSES
1
RB
RA
0
CS RISING
EDGE
0
Increment/Decrement Wiper Counter Register (WCR)
CS
FALLING
EDGE
DEVICE TYPE
IDENTIFIER
0
1
0
1
DEVICE
ADDRESSES
0
0
A1 A0
INSTRUCTION
OPCODE
0
0
1
0
WCR
ADDRESSES
X
X
0
INCREMENT/DECREMENT
(SENT BY MASTER ON SI)
0
I/D
I/D
.
.
.
.
I/D I/D
CS
RISING
EDGE
Read Status Register (SR)
CS
FALLIN
G EDGE
DEVICE TYPE
IDENTIFIER
0
1
0
1
DEVICE
ADDRESSES
0
0
A1
A0
INSTRUCTION
OPCODE
WCR
ADDRESSES
0
0
1
0
1
0
0
1
DATA BYTE
(SENT BY X9251 ON SO)
0
0
0
0
0
0
0
WIP
CS
RISING
EDGE
NOTES:
5. “A1 ~ A0”: stands for the device addresses sent by the master.
6. WPx refers to wiper position data in the Counter Register
7. “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
8. “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
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Absolute Maximum Ratings
Recommended Operating Conditions
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +135C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C
Voltage on SCK, CS, SI, SO, WP, HOLD, VCC
with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1V to +7V
V = | (VH - VL) |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . +300C
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA
Power Rating (each pot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50mW
Commercial Temperature Range . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage (VCC) Limits (Note 12)
X9251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
X9251-2.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
Analog Characteristics
SYMBOL
RTOTAL
Over the recommended operating conditions unless otherwise specified.
PARAMETER
TEST CONDITIONS
End to End Resistance
MIN
U version
TYP
50
End to End Resistance Tolerance
RW
Wiper Resistance
IW =
IW =
V TERM
V(VCC)
RTOTAL
V(VCC)
RTOTAL
Voltage on any RH or RL Pin
VSS = 0V
Noise (Note 14)
Ref: 1V
at VCC = 3V
at VCC = 5V
VSS
Resolution
CH/CL/CW
Absolute Linearity (Note 9)
Rw(n)(actual) - Rw(n)(expected) (Note 13)
Relative Linearity (Note 10)
Rw(n + 1) - [Rw(n) + MI] (Note 13)
Temperature Coefficient of RTOTAL
(Note 14)
Ratiometric Temp. Coefficient
(Note 14)
Potentiometer Capacitances
See macromodel on page 13, (Note 14)
DC Operating Characteristics
SYMBOL
MAX
UNITS
kΩ
±20
%
300
Ω
220
Ω
VCC
V
-120
dBV√Hz
0.4
%
-1
+1
MI
(Note 11)
-0.6
+0.6
MI
(Note 11)
300
ppm/C
20
ppm/°C
10/10/25
pF
Over the recommended operating conditions unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
400
µA
5
mA
ICC1
VCC Supply Current (Active)
fSCK = 2.5MHz, SO = Open, VCC = 6V
Other Inputs = VSS
ICC2
VCC Supply Current
(Nonvolatile Write)
fSCK = 2.5MHz, SO = Open, VCC = 6V
Other Inputs = VSS
ISB
VCC Current (Standby)
SCK = SI = VSS, Addr. = VSS,
CS = VCC = 6V
3
µA
1
ILI
Input Leakage Current
VIN = VSS to VCC
10
µA
ILO
Output Leakage Current
VOUT = VSS to VCC
10
µA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VOL
Output LOW Voltage
IOL = 3mA
VOH
Output HIGH Voltage
IOH = -1mA, VCC  +3V
VCC - 0.8
V
VOH
Output HIGH Voltage
IOH = -0.4mA, VCC  +3V
VCC - 0.4
V
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12
VCC x 0.7
V
VCC x 0.3
V
0.4
V
FN8166.6
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X9251
Endurance and Data Retention
PARAMETER
Minimum endurance
Data retention
MIN
UNITS
100,000
Data changes per bit per register
100
years
Capacitance
SYMBOL
TEST
TEST CONDITIONS
TYP
UNITS
VOUT = 0V
8
pF
Output capacitance (SO)
VOUT = 0V
8
pF
Input capacitance (A0, A1, CS, WP, HOLD, and SCK)
VIN = 0V
6
pF
CIN/OUT (Note 14) Input/Output capacitance (SI)
COUT (Note 14)
CIN (Note 14)
Power-Up Timing
SYMBOL
PARAMETER
MIN
MAX
UNITS
tr VCC (Note 14)
VCC Power-up Rate
0.2
V/ms
tPUR (Note 15)
Power-up to Initiation of Read Operation
1
ms
tPUW (Note 15)
Power-up to Initiation of Write Operation
50
ms
AC Test Conditions
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10ns
Input and Output Timing Level
VCC x 0.5
NOTES:
9. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
10. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a
measure of the error in step size.
11. MI = RTOT/255 or (RH - RL)/255, single pot.
12. During power up VCC > VH, VL, and VW.
13. n = 0, 1, 2, …,255; m = 0, 1, 2, …, 254.
14. This parameter is not 100% tested
15. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These
parameters are periodically sampled and not 100% tested.
Equivalent AC Load Circuit
VCC
SPICE MACROMODEL
RTOTAL
2kΩ
RH
RL
CW
CL
SO PIN
2kΩ
CL
10pF
25pF
10pF
10pF
RW
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X9251
AC TIMING
SYMBOL
PARAMETER
MIN
MAX
UNITS
2
MHz
fSCK
SPI clock frequency
tCYC
SPI Clock Cycle Time
500
ns
tWH
SPI Clock High Time
200
ns
tWL
SPI Clock Low Time
200
ns
tLEAD
Lead Time
250
ns
tLAG
Lag Time
250
ns
tSU
SI, SCK, HOLD and CS Input Setup Time
50
ns
tH
SI, SCK, HOLD and CS Input Hold Time
50
ns
tRI
SI, SCK, HOLD and CS Input Rise Time
tFI
SI, SCK, HOLD and CS Input Fall Time
tDIS
SO Output Disable Time
tV
SO Output Valid Time
tHO
SO Output Hold Time
0
2
µs
2
µs
250
ns
200
ns
0
ns
tRO (Note 14)
SO Output Rise Time
100
ns
tFO (Note 14)
SO Output Fall Time
100
ns
tHOLD
HOLD Time
400
ns
tHSU
HOLD Setup Time
100
ns
tHH
HOLD Hold Time
100
tHZ
HOLD Low to Output in High Z
100
ns
tLZ
HOLD High to Output in Low Z
100
ns
TI
Noise Suppression Time Constant at SI, SCK, HOLD and CS Inputs
10
ns
ns
CS Deselect Time
2
µs
tWPASU
WP, A0 Setup Time
0
ns
tWPAH
WP, A0 Hold Time
0
ns
tCS
High-Voltage Write Cycle Timing
SYMBOL
tWR
PARAMETER
TYP
MAX
UNITS
5
10
ms
MIN
MAX
UNITS
Wiper response time after the third (last) power supply is stable
5
10
µs
Wiper response time after instruction issued (all load instructions)
5
10
µs
High-voltage write cycle time (store instructions)
XDCP Timing
SYMBOL
tWRPO (Note 14)
tWRL (Note 14)
PARAMETER
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X9251
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Timing Diagrams
Input Timing
tCS
CS
tCYC
tLEAD
SCK
tSU
tH
tLAG
...
tWH
tWL
...
SI
MSB
SO
HIGH IMPEDANCE
tRI
tFI
LSB
Output Timing
CS
SCK
...
tV
MSB
SO
SI
tHO
tDIS
...
LSB
ADDR
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X9251
Hold Timing
CS
tHSU
tHH
SCK
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
XDCP Timing (for All Load Instructions)
CS
SCK
...
tWRL
...
MSB
SI
LSB
VWx
SO
HIGH IMPEDANCE
Write Protect and Device Address Pins Timing
(ANY INSTRUCTION)
CS
tWPASU
tWPAH
WP
A0
A1
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X9251
Applications information
Basic Configurations of Electronic Potentiometers
+VR
VR
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
NON INVERTING AMPLIFIER
VS
VOLTAGE REGULATOR
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1 + R2/R1)VS
VO (REG) = 1.25V (1 + R2/R1) + Iadj R2
OFFSET VOLTAGE ADJUSTMENT
R1
COMPARATOR WITH HYSTERESIS
R2
VS
VS
–
+
100kΩ
VO
–
VO
+
+12V
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10kΩ
}
10kΩ
}
TL072
10kΩ
R1
R2
VUL = {R1/(R1 + R2)} VO(max)
RLL = {R1/(R1 + R2)} VO(min)
-12V
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Application Circuits (continued)
ATTENUATOR
FILTER
C
VS
+
R2
R1
VS
VO
–
–
R
VO
+
R3
R4
R2
R1 = R2 = R3 = R4 = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2RC)
VO = G VS
-1/2  G  +1/2
R2
}
VS
R1
}
INVERTING AMPLIFIER
EQUIVALENT L-R CIRCUIT
R2
C1
–
VS
VO
+
+
–
R1
ZIN
VO = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
FUNCTION GENERATOR
C
R2
–
R1
–
+
} RA
+
} RB
FREQUENCY  R1, R2, C
AMPLITUDE RA, RB
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X9251
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
December 3, 2014
FN8166.6
Updated to Intersil new standards.
Updated Ordering Information Table on page 3, by removing obsoleted parts and 100kΩ referenced parts, adding
Note 3 and changed TSSOP POD references from “MDP0044” to “M24.173”.
Added Revision History and About Intersil verbiage.
Updated M24.3 POD to the latest revision.
-“Updated to new POD standard by removing table listing dimensions and putting dimensions on drawing.
Added Land Pattern.”
Replaced MDP0044 POD with M24.173 POD to update to new format and only show 24 Ld version.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN8166.6
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X9251
Package Outline Drawing
M24.3
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC)
Rev 2, 3/11
24
INDEX
AREA
7.60 (0.299)
7.40 (0.291) 10.65 (0.419)
10.00 (0.394)
DETAIL "A"
1
2
3
TOP VIEW
1.27 (0.050)
0.40 (0.016)
SEATING PLANE
2.65 (0.104)
2.35 (0.093)
15.60 (0.614)
15.20 (0.598)
0.75 (0.029)
x 45°
0.25 (0.010)
0.30 (0.012)
0.10 (0.004)
1.27 (0.050)
0.51 (0.020)
0.33 (0.013)
8°
0°
0.32 (0.012)
0.23 (0.009)
SIDE VIEW “B”
SIDE VIEW “A”
1.981 (0.078)
9.373 (0.369)
1.27 (0.050)
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. Package length does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
3. Package width does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm
(0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions in
( ) are not necessarily exact.
8. This outline conforms to JEDEC publication MS-013-AD ISSUE C.
0.533 (0.021)
TYPICAL RECOMMENDED LAND PATTERN
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Package Outline Drawing
M24.173
24 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 1, 5/10
A
1
3
7.80 ±0.10
SEE DETAIL "X"
13
24
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
12
0.15 +0.05
-0.06
B
0.65
TOP VIEW
END VIEW
1.00 REF
H
- 0.05
C
0.90 +0.15
-0.10
1.20 MAX
GAUGE
PLANE
SEATING PLANE
0.25 +0.05
-0.06
0.10 M C B A
0.10 C
5
0°-8°
0.05 MIN
0.15 MAX
SIDE VIEW
0.25
0.60± 0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
is 0.07mm.
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153.
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