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1-8
®
Dual Digitally Controlled Potentiometer
(XDCP™) with Operational Amplifier
Programmable Analog
March 11, 2005
FN8199.0
DESCRIPTION
The X9438 is a monolithic CMOS IC that incorporates
two operational amplifiers and two nonvolatile digitally
controlled potentiometers. The amplifiers are CMOS
differential input voltage operational amplifiers with
near rail-to-rail outputs. All pins for the two amplifiers
are brought out of the package to allow combining
them with the potentiometers, or using them as complete stand-alone amplifiers.
FEATURES
•
•
•
•
Two CMOS voltage operational amplifiers
Two digitally controlled potentiometers
Can be combined or used separately
Amplifiers:
—Low voltage operation
—V+/V- = ±2.7V to ±5.5V
—Rail-to-rail CMOS performance
—1MHz gain bandwidth product
• Digitally controlled potentiometers
—Dual 64 tap potentiometers
—Rtotal = 10kΩ
—2-wire serial interface
—VCC = 2.7V to 5.5V
The digitally controlled potentiometers consist of a
series string of 63 polycrystalline resistors that behave
as standard integrated circuit resistors. The two-wire
serial port, common to both pots, allows the user to
program the connection of the wiper output to any of
the resistor nodes in the series string. The wiper position is saved in the on board E2 memory to allow for
nonvolatile restoration of the wiper position.
A wide variety of applications can be implemented
using the potentiometers and the amplifiers. A typical
application is to implement the amplifier as a wiper
buffer in circuits that use the potentiometer as a voltage
reference. The potentiometer can also be combined
with the amplifier yielding a digitally programmable gain
amplifier or programmable current source.
BLOCK DIAGRAM
VCC
RW0
RH0 RL0
V+
VNI0
SCL
SDA
A3
A2
A1
A0
Control and
Memory
+
VOUT0
–
WCR0
VINV0
VNI1
+
WP
VOUT1
–
WCR1
VINV1
VSS
1
RW1
RL1 RH1
V-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9438
PIN DESCRIPTIONS
Analog Supplies V+, V-
Host Interface Pins
The analog supplies V+, V- are the supply voltages for
the XDCP analog section and the operational amplifiers.
Serial Clock (SCL)
System Supply VCC and Ground VSS.
The SCL input is used to clock data into and out of the
X9438.
The system supply VCC and its reference VSS is used
to bias the interface and control circuits.
Serial Data (SDA)
PIN CONFIGURATION
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor.
Device Address (A0 - A3)
The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9438. A maximum of 16 devices may share the
same 2-wire serial bus.
Potentiometer Pins(1)
TSSOP
SOIC
VCC
1
24
V+
NC
1
24
RL0
RH0
2
3
23
22
2
3
23
22
RW0
4
5
21
20
A0
VOUT0
V
VNI0
INV0
VNI0
V
4
5
21
20
A2
WP
SDA
6
19
X9438
7
18
8
17
9
16
A1
RL1
INV0
A0
NC
A3
SCL
VINV1
RH1
RW1
10
15
11
14
VOUT1
VSS
12
13
V-
VNI1
VOUT0
V+
VCC
RL0
RH0
RW0
6
19
X9438
7
18
8
17
9
16
10
A3
SCL
VINV1
VNI1
VOUT1
VVSS
RW1
RH1
15
RL1
A2
11
14
A1
WR
12
13
SDA
RH (RH0 - RH1), RL (RL0 - RL1)
The RH and RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer.
PIN NAMES
Symbol
Description
RW (RW0 - RW1)
SCL
Serial Clock
The wiper output is equivalent to the wiper output of a
mechanical potentiometer.
SDA
Serial Data
A0 - A3
Device Address
Amplifier and Device Pins
RH0 - RH1,
RL0 - RL1
Potentiometers (terminal equivalent)
Amplifier Input Voltage VNI(0,1) and VINV(0,1)
RW0 - RW1
Potentiometers (wiper equivalent)
VNI and VINV are inputs to the noninverting (+) and
inverting (-) inputs of the operational amplifiers.
VNI(0,1),
VINV(0,1)
Amplifier Input Voltages
VOUT0, VOUT1
Amplifier Outputs
Amplifier Output Voltage VOUT(0,1)
WP
Hardware Write Protection
VOUT is the voltage output pin of the operational
amplifier.
V+,V-
Analog and Voltage Amplifier Supplies
VCC
System/Digital Supply Voltage
Hardware Write Protect Input WP
VSS
System Ground
The WP pin, when low, prevents non-volatile writes to
the wiper counter registers.
NC
No Connection
Note:
(1) Alternate designations for RH, RL, RW are VH, VL, VW
2
FN8199.0
March 11, 2005
X9438
PRINCIPLES OF OPERATION
The X9438 is an integrated microcircuit incorporating
two resistor arrays, two operational amplifiers and
their associated registers and counters; and the serial
interface logic providing direct communication
between the host and the digitally controlled potentiometers and operational amplifiers.
Serial Interface
The X9438 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers and provide the clock for both transmit and receive operations.
Therefore, the X9438 will be considered a slave
device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (tLOW). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9438 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (tHIGH). The X9438 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this condition is met.
Stop Condition
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits
of data.
The X9438 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the command byte. If the command is followed by a data byte
the X9438 will respond with a final acknowledge.
Operational Amplifier
The voltage operational amplifiers are CMOS rail-torail output general purpose amplifiers. They are
designed to operate from dual (±) power supplies. The
amplifiers may be configured like any standard amplifier. All pins are externally available to allow connections with the potentiometers or as stand alone
amplifiers.
Potentiometer/Array Description
The X9438 is comprised of two resistor arrays and two
operational amplifiers. Each array contains 63 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RH and RL
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(RW) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by a volatile wiper counter register (WCR).
The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
INSTRUCTIONS AND PROGRAMMING
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant four bits of the slave address are the device type
identifier (refer to Figure 1). For the X9438 this is fixed
as 0101[B].
Figure 1. Address/Identification Byte Format
Device Type
Identifier
0
1
0
1
A3
A2
A1
A0
Device Address
3
FN8199.0
March 11, 2005
X9438
The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A0 - A3 inputs. The X9438 compares
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9438 to respond with an acknowledge. The
A0 - A3 inputs can be actively driven by CMOS input
signals or tied to VCC or VSS.
The disabling of the inputs, during the internal non-volatile write operation, can be used to take advantage of
the typical 5ms EEPROM write cycle time. Once the
stop condition is issued to indicate the end of the nonvolatile write command the X9438 initiates the internal
write cycle. ACK polling (Flow 1) can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9438 is
still busy with the write operation no ACK will be
returned. If the X9438 has completed the write operation an ACK will be returned and the master can then
proceed with the next operation.
Flow 1. ACK Polling Sequence
Nonvolatile Write
Command Completed
Enter Ack Polling
Issue
START
Issue Slave
Address
Issue STOP
No
Yes
Further
Operation?
The byte following the address contains the instruction
and register pointer information. The four most significant bits are the instruction. The next four bits point to
one of the two pots and when applicable they point to
one of the four WCRs associated data registers. The
format is shown below in Figure 2.
Figure 2. Instruction Byte Format
Acknowledge Polling
ACK
Returned?
Instruction Structure
No
Yes
Issue
Instruction
Issue STOP
Prooceed
Prooceed
4
Register
Select
I3
I2
I1
Instructions
I0
R1
R0
0
P0
WCR Select
The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the two registers that is to be acted upon when a register oriented
instruction is issued. The last bit (P0) selects which
one of the two potentiometers is to be affected by the
instruction.
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions
exchange data between the wiper counter register and
one of the data registers. A transfer from a data register to a wiper counter register is essentially a write to a
static RAM. The response of the wiper to this action
will be delayed tWRL. A transfer from the wiper counter
register (current wiper position) to a data register is a
write to non-volatile memory and takes a minimum of
tWR to complete. The transfer can occur between one
of the two potentiometers and one of its associated
registers; or it may occur globally, wherein the transfer
occurs between all of the potentiometers and one of
their associated registers.
Four instructions require a three-byte sequence to
complete. The basic sequence is illustrated in Figure
4. These instructions transfer data between the host
and the X9438; either between the host and one of the
data registers or directly between the host and the
wiper counter and analog control registers. These
instructions are: 1) Read Wiper Counter Register or
read the current wiper position of the selected pot, 2)
Write Wiper Counter Register, i.e. change current
wiper position of the selected pot; 3) Read Data Register, read the contents of the selected non-volatile register; 4) Write Data Register, write a new value to the
selected data register. The bit structures of the instructions are shown in Figure 6.
FN8199.0
March 11, 2005
X9438
Figure 3. Two-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
R1 R0 0
P0
A
C
K
S
T
O
P
Figure 4. Three-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0 A
C
K
I3
I2
I1 I0
0
P0 R1 R0 A
C
K
D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
(tHIGH) while SDA is HIGH, the selected wiper will
move one resistor segment towards the VH terminal.
Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the VL terminal. A detailed illustration of the
sequence for this operation is shown in Figure 5.
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9438 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
Figure 5. Increment/Decrement Command Sequence
SCL
SDA
X
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
5
A
C
K
I3
I2
I1
I0
X
P1 P0 R1 R0 A
C
K
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
FN8199.0
March 11, 2005
X9438
Figure 6. Instruction Set
Read Wiper Counter Register (WCR)
Read the contents of the Wiper Counter Register P0.
S device type
device
instruction
WCR
S
T identifier
addresses
opcode
addresses
A
A
C
A
A
A
A
P
R 0 1 0 1
1 0 0 1 0 0 0
3 2 1 0 K
0
T
register data
S
(sent by slave on SDA)
A
C
D D D D D D
K 0 0 5 4 3 2 1 0
M
A
C
K
S
T
O
P
S
A
C
K
S
T
O
P
M
A
C
K
S
T
O
P
P0: 0 - WCR0, 1 - WCR1
Write Wiper Counter Register (WCR)
Write new value to the Wiper Counter Register P0.
S device type
device
instruction
WCR
S
T identifier
addresses
opcode
addresses
A
A
C
P
R 0 1 0 1 A A A A
1 0 1 0 0 0 0
3 2 1 0 K
0
T
register data
S
(sent by master on SDA)
A
C
D D D D D D
K 0 0 5 4 3 2 1 0
P0: 0 - WCR0, 1 - WCR1
Read Data Register (DR)
Read the contents of the Register pointed to by P0 and R1 - R0.
S device type
device
instruction WCR/DR
S
T identifier
addresses
opcode
addresses
A
A
C
R R
P
R 0 1 0 1 A A A A
1 0 1 1
0
3 2 1 0 K
1 0
0
T
register data
S
(sent by master on SDA)
A
C
D D D D D D
K 0 0 5 4 3 2 1 0
R1 R0:
00 - R0,
01 - R2,
10 - R1
11 - R3
Write Data Register (DR)
Write new value to the Register pointed to by P0 and R1 - R0.
S device type
device
instruction
S
T identifier
addresses
opcode
A
A
C
R 0 1 0 1 A A A A
1 1 0 0
3 2 1 0 K
T
WCR/DR
addresses
R
1
R
0
0
register data
S
(sent by master on SDA)
A
P C
D D D D D D
0 0
0 K
5 4 3 2 1 0
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Definitions:
SACK - Slave acknowledge, MACK - Master acknowledge, I/D - Increment/Decrement (1/0), R - Register,
P - Potentiometer
6
FN8199.0
March 11, 2005
X9438
Figure 6. Instruction Set (continued)
Transfer Data Register to Wiper Counter Register
Transfer the contents of the Register pointed to by R1 - R0 to the WCR pointed to by P0.
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
WCR/DR
S
opcode
addresses
A
C
R R
P
K 1 1 0 1 1 0 0 0
S
A
C
K
S
T
O
P
Transfer Wiper Counter Register to Data Register
Transfer the contents of the WCR pointed to by P0 to the Register pointed to by R1 - R0.
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
WCR/DR
S
opcode
addresses
A
C
R R
P
1 1 1 0
0
K
1 0
0
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Global Transfer Data Register to Wiper Counter Register
Transfer the contents of all four Data Registers pointed to by R1 - R0 to their respective WCR.
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
DR
S
opcode
addresses
A
C
R R
K 0 0 0 1 1 0 0 0
S
A
C
K
S
T
O
P
Global Transfer Wiper Counter Register to Data Register
Transfer the contents of all WCRs to their respective data Registers pointed to by R1 - R0.
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
DR
S
opcode
addresses
A
C
R R
1 0 0 0
0 0
K
1 0
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Increment/Decrement Wiper Counter Register
Enable Increment/decrement of the WCR pointed to by P0.
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
WCR
S
opcode
addresses
A
C
P
K 0 0 1 0 0 0 0 0
increment/decrement
S
(sent by master on SDA)
A
C I/ I/
I/ I/
K D D . . . . D D
S
T
O
P
P0: 0 or 1 only.
7
FN8199.0
March 11, 2005
X9438
REGISTER OPERATION
Both digitally controlled potentiometers share the
serial interface and share a common architecture.
Each potentiometer is associated with a Wiper
Counter Register (WCR), and four Data Registers.
Figure 7 illustrates the control, registers, and system
features of the device.
Figure 7. System Block Diagram
VH (0,1)
(DR0-DR3)0,1
WCR0,1
WP
SCL
SDA
A0
A1
A2
A3
VL (0,1)
VW (0,1)
VINV (0,1)
Interface
and
Control
Circuitry
VNI (0,1)
+
–
VOUT (0,1)
The wiper counter register is a volatile register; that is,
its contents are lost when the X9438 is powered-down.
Although the registers are automatically loaded with the
value in R0 upon power-up, it should be noted this may
be different from the value present at power-down.
Data Registers (DR)
Each potentiometer has four non-volatile data registers
(DR). These can be read or written directly by the host
and data can be transferred between any of the four
data registers and the WCR. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could store system parameters or user preference data.
REGISTER DESCRIPTIONS AND MEMORY MAP
Memory Map
WCRO
WCR1
DR0
DR0
DR1
DR1
DR2
DR2
DR3
DR3
Wiper Counter (WCR) and Analog Control Registers
(ACR)
The X9438 contains two wiper counter registers, one
for each XDCP. The wiper counter register is equivalent to a serial-in, parallel-out counter, with its outputs
decoded to select one of sixty-four switches along its
resistor array. The contents of the wiper counter register can be altered in four ways: it may be written
directly by the host via the write WCR Instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated data registers
(DR) via the XFR data register instruction (parallel
load); it can be modified one step at a time by the
increment/decrement instruction (WCR only). Finally,
it is loaded with the contents of its data register zero
(R0) upon power-up.
8
Wiper Counter Register (WCR)
0
0
WP5 WP4 WP3 WP2 WP1
(volatile)
WP0
(LSB)
WP0-WP5 identify wiper position.
Data Registers (DR, R0 - R3)
Wiper Position or User Data
(Nonvolatile)
FN8199.0
March 11, 2005
X9438
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SDA, SCL or any address
input with respect to VSS ......................... -1V to +7V
Voltage on any V+ (referenced to VSS) ................ +7V
Voltage on any V- (referenced to VSS) .................. -7V
(V+) - (V-) ............................................................. 10V
Any RH ....................................................................V+
Any RL ......................................................................VLead temperature (soldering, 10 seconds) ........ 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Min.
0°C
Max.
+70°C
Device
X9438
Supply Voltage (VCC) Limits
5V ±10%
Industrial
-40°C
+85°C
X9438-2.7
2.7V to 5.5V
POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
RTOTAL
Parameter
End to end resistance
Min.
Typ.
-20
Power rating
IW
Wiper current
RW
Wiper resistance
-3
Max.
Unit
+20
%
50
mW
+3
mA
100
Ω
VCC = 5V, Wiper Current = 3mA
100
250
Ω
VCC = 2.7, Wiper Current = 1mA
V
Voltage on V+ pin
X9438
+4.5
+5.5
X9438-2.7
+2.7
+5.5
Vv-
Voltage on V- pin
X9438
-5.5
-4.5
X9438-2.7
-5.5
-2.7
V-
V+
Voltage on any RH or RL pin
Noise
Resolution (4)
Absolute linearity (1)
Relative
linearity (2)
Temperature coefficient of RTOTAL
Ratiometric temperature coefficient
25°C, each pot
40
Vv+
VTERM
Test Conditions
V
V
-100
dBv
1.6
%
-1
-0.2
Ref: 1V
+1
MI(3)
Vw(n)(actual) - Vw(n)(expected)
+0.2
MI(3)
Vw(n + 1) - [Vw(n) + MI]
±20
ppm/°C
±300
ppm/°C
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (RH - RL)/63, single pot ( = LSB)
(4) Individual array resolutions
9
FN8199.0
March 11, 2005
X9438
AMPLIFIER ELECTRICAL CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Symbol
Parameter
Condition
Industrial
Commercial
Min. Typ. Max.
Min. Typ. Max.
Unit
1
mV
Input offset voltage
V+/V- ±3V to ±5V
1
Input offset voltage temp.
coefficient
V+/V- ±3V to ±5V
-10
-10
µV/°C
Input bias current
V+/V- ±3V to ±5V
50
50
pA
Input offset current
V+/V- ±3V to ±5V
25
25
pA
CMRR
Common mode
rejection ratio
VCM = -1V to +1V
70
70
dB
PSRR
Power supply
rejection ratio
V+/V- ±3V to ±5V
70
70
dB
Input common mode voltage
range
Tj = 25°C
V-
AV
Large signal voltage gain
VO = -1V to + 1V
30
VO
Output voltage swing
VV+
VOS
TCVOS
IB
IOS
VCM
IO
Output current
IS
Supply current
3
V+
50
V30
+0.1
V+
V
50
V/mV
+0.1
-.15
V+/V- = ±5.5V
V+/V- = ±3.3V
2
50
30
V
V
-.15
50
30
mA
mA
V+/V- = ±5.0V
3
3
mA
V+/V- = ±3.0V
1.5
1.5
mA
GB
Gain-bandwidth prod
RL = 100k, CL = 50pf
1.0
1.0
MHz
SR
Slew rate
RL = 100k, CL = 50pf
1.5
1.5
V/µsec
ΦM
Phase margin
RL = 100k, CL = 50pf
80
80
Deg.
V+ and V- (±5V to ±3V) are the amplifier power supplies. The amplifiers are specified with dual power supplies. VCC and VSS
is the logic supply. All ratings are over the temperature range for the Industrial (-40 to + 85°C) and Commercial (0 to 70°C)
versions of the part unless specified differently.
SYSTEM/DIGITAL D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Max.
Unit
400
µA
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
VCC current (standby)
1
µA
SCL = SDA = VCC, Addr. = VSS
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC + 0.5
V
VIL
Input LOW voltage
-0.5
VCC x 0.1
V
VOL
Output LOW voltage
0.4
V
ICC
VCC supply current (active)
ISB
10
Min.
Typ.
Test Conditions
IOL = 3mA
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ENDURANCE AND DATA RETENTION
Parameter
Min.
Unit
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
Years
CAPACITANCE
Symbol
Test
Typical
Unit
Test Conditions
CI/O
Input/output capacitance (SDA)
8
pF
VI/O = 0V
CIN
Input capacitance (A0, A1, A2, A3, and SCL)
6
pF
VIN = 0V
10/10/25
pF
See SPICE Model
CL | CH | CW
Potentiometer capacitance
POWER-UP TIMING AND SEQUENCE
Power-up sequence(1): (1) VCC
(2) V+ and V-
Power-down sequence: no limitation
A.C. TEST CONDITIONS
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
Note:
(1) Applicable to recall and power consumption applications
EQUIVALENT A.C. LOAD CIRCUIT
5V
SPICE Macro Model
RTOTAL
2.7V
RH
1533Ω
CW
CH
CL
RL
SDA Output
100pF
100pF
RW
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TIMING DIAGRAMS
START and STOP Timing
(START)
(STOP)
tF
tR
SCL
tSU:STA
tHD:STA
tSU:STO
tF
tR
SDA
Input Timing
tCYC
tHIGH
SCL
tLOW
SDA
tSU:DAT
tHD:DAT
tBUF
Output Timing
SCL
SDA
tDH
tAA
DCP Timing (for All Load Instructions)
(STOP)
SCL
LSB
SDA
tWRL
VWx
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DCP Timing (for Increment/Decrement Instruction)
SCL
SDA
Wiper Register Address
Inc/Dec
Inc/Dec
tWRID
VWx
Write Protect and Device Address Pins Timing
(START)
SCL
(STOP)
...
(Any Instruction)
...
SDA
...
tSU:WPA
tHD:WPA
WP
A0, A1
A2, A3
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AC TIMING
Symbol
Min.
Max.
Unit
400
kHz
fSCL
Clock frequency
tCYC
Clock cycle time
2500
ns
tHIGH
Clock high time
600
ns
tLOW
Clock low time
1300
ns
tSU:STA
Start setup time
600
ns
tHD:STA
Start hold time
600
ns
tSU:STO
Stop setup time
600
ns
tSU:DAT
SDA data input setup time
100
ns
SDA data input hold time
0/30
ns
tHD:DAT
(4)
tR
SCL and SDA rise time
300
ns
tF
SCL and SDA fall time
300
ns
tAA
SCL low to SDA data output valid time
100
900
ns
tDH
SDA data output hold time
50
ns
TI
Noise suppression time constant at SCL and SDA inputs
50
ns
1300
ns
tBUF
Note:
Parameter
Bus free time (Prior to Any Transmission)
tSU:WPA
WP, A0, A1, A2 and A3 setup time
0
ns
tHD:WPA
WP, A0, A1, A2 and A3 hold time
0
ns
(4) VCC = 5V/2.7V
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
tWR
Parameter
High-voltage write cycle time (store instructions)
Typ.
Max.
Unit
5
10
ms
Min.
Max.
Unit
10
µs
DCP TIMING
Symbol
tWRL
Parameter
Wiper response time after instruction issued (All load instructions)
VCC RAMP (sample tester)
Symbol
trVCC
Parameter
VCC Power-up rate
14
Typ.
Max.
Unit
.2
50
V/ms
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BASIC APPLICATIONS
I to V Converter
Attenuator
R3
R2
R1
R2
R1
–
–
VS
VO
+
VO
+
R3
R4
R1 = R3 = R4
R2 = 2R1
VO/IS = -R3(1 + R2/R1) + R2
V O = G VS
-1/2 ≤ G ≤ +1/2
Phase Shifter
Absolute Value Amplifier with Gain
2R
R1
R1
VS
–
VS
R
R
R1
R
–
–
+
+
A1
+
C
VO
R
A2
VO = |VS|
VO
R1
R
VO/VS = 180° - 2tan-1wRC
Function Generator
R2
–
C
R1
–
+
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
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PACKAGING INFORMATION
24-Lead Plastic Small Outline Gull Wing Package Type S
0.290 (7.37) 0.393 (10.00)
0.299 (7.60) 0.420 (10.65)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050" Typical
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"
Typical
0° - 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
FOOTPRINT
0.030" Typical
24 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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PACKAGING INFORMATION
24-Lead Plastic, TSSOP Package Type V
.026 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
0 - 8°
(4.16) (7.72)
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
Detail A (20X)
(0.42)
(0.65)
.031 (.80)
.041 (1.05)
ALL MEASUREMENTS ARE TYPICAL
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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Ordering Information
X9438
Y
P
T
V
VCC Limits
Blank = 5V ±10%
-2.7 = 2.7 to 5.5V
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Package
P24 = 24-Lead Plastic DIP
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
Potentiometer Organization
Pot 0
Pot 1
W=
10kΩ
10kΩ
Y=
2.5kΩ
2.5kΩ
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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