DATASHEET

X9440
®
Mixed Signal with SPI Interface
Data Sheet
March 28, 2005
Dual Digitally Controlled Potentiometer
(XDCP™) & Voltage Comparator
FN8200.0
DESCRIPTION
The X9440 integrates two non volatile digitally controlled potentiometers (XDCP) and two voltage comparators on a CMOS monolithic microcircuit.
FEATURES
• Two digitally controlled potentiometers and two
voltage comparators in one package
• SPI serial interface
• Register oriented format
—Direct read/write wiper position
—Store as many as four positions per pot
• Fast response comparator
• Enable, latch, or shutdown comparator outputs
through the ACR
• Auto-recall of WCR and ACR data from R0
• Hardware write protection, WP
• Separate analog and digital/system supplies
• Direct write cell
—Endurance–100,000 data changes per bit per
register
—Register data retention–100 years
• 16-bytes of EEPROM memory
• Power saving feature and low noise
• Two 10kΩ or two 2.5kΩ potentiometers
• Resolution: 64 taps each pot
• 24-lead TSSOP and 24-Lead SOIC packages
The X9440 contains two resistor arrays, each composed of 63 resistive elements. Between each element and at either end are tap points accessible to the
wiper elements. The position of the wiper element on
the array is controlled by the user through the SPI
serial bus interface.
Each potentiometer has an associated voltage comparator. The comparator compares the external input
voltage VNI with the wiper voltage VW and sets the output voltage level to a logic high or low.
Each resistor array and comparator has associated
with it a wiper counter register (WCR), analog control
register (ACR), and eight 6 bit data registers that can
be directly written and read by the user. The contents
of the wiper counter register controls the position of
the wiper on the resistor array. The contents of the
analog control register controls the comparator and its
output. The potentiometer is programmed with a SPI
serial interface.
BLOCK DIAGRAM
VH (0,1)
(R0-R3)0,1
WCR0,1
WP
VL (0,1)
VW (0,1)
SCK
S0
SI
A0
A1
CS
Interface
and
Control
Circuitry
VNI (0,1)
+
(R0-R3)0,1
HOLD
1
ACR0,1
–
VOUT (0,1)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9440
Potentiometer Pins
VH (VH0-VH3), VL (VL0-VL3)
The VH and VL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer.
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9440.
Chip Select (CS)
When CS is HIGH, the X9440 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9440, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK
is LOW. If the pause feature is not used, HOLD should
be held HIGH at all times.
VW (VW0-VW1)
The wiper output VW is equivalent to the wiper output
of a mechanical potentiometer and is connected to the
inverting input of the voltage comparator.
Comparator and Device Pins
Voltage Input VNI0, VNI1
VNI0 and VNI1 are the input voltages to the plus (noninverting) inputs of the two comparators.
Buffered Voltage Outputs VOUT0, VOUT1
VOUT0 and VOUT1 are the buffered voltage comparator
outputs controlled by bits in the volatile analog control
register.
Hardware Write Protect Input WP
The WP pin when low prevents non volatile writes to
the wiper counter and analog control registers.
Analog Supplies V+, VThe Analog Supplies V+, V- are the supply voltages for
the XDCP analog section and the voltage comparators.
System Supply VCC and Ground VSS
The system supply, VCC and its reference VSS is used
to bias the interface and control circuits.
Device Address (A0-A1)
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9440. A maximum of 4 devices may share the
same SPI serial bus.
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X9440
PIN CONFIGURATION
PRINCIPLES OF OPERATION
SOIC
VCC
VL0
VH0
VW0
CS
WP
SI
A1
VL1
VH1
VW1
1
2
3
4
5
6
7
8
9
10
11
VSS
12
X9440
24
23
22
21
20
19
18
17
16
15
14
13
V+
VOUT0
VNI0
NC
A0
SO
HOLD
SCK
NC
VNI1
VOUT1
V-
TSSOP
SI
A1
VL1
VH1
VW1
VSS
NC
VVOUT1
VNI1
SCK
HOLD
1
2
3
4
5
6
7
8
9
10
X9440
11
12
24
23
22
21
20
19
18
17
16
15
WP
CS
VW0
VH0
VL0
VCC
NC
V+
VOUT0
14
VNI0
A0
13
S0
PIN NAMES
Symbol
Description
SCK
Serial Clock
S1, SO
Serial Data
A0-A1
Device Address
The X9440 is a highly integrated microcircuit incorporating two resistor arrays, two voltage comparators
and their associated registers and counters; and the
serial interface logic providing direct communication
between the host and the digitally-controlled potentiometers and voltage comparators.
Serial Interface
The X9440 supports the SPI interface hardware conventions. The device is accessed via the SI input with
data clocked in on the rising SCK. CS must be LOW
and the HOLD and WP pins must be HIGH during the
entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9440 is comprised of two resistor arrays and two
voltage comparators. Each array contains 63 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (VH and VL
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(VW) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by a volatile wiper counter register (WCR).
The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
VH0-VH1,
VL0-VL1
Potentiometers (terminal equivalent)
VW0–VW1
Potentiometers (wiper equivalent)
Voltage Comparator
VNI0, VNI1
Comparator Input Voltages
The comparator compares the wiper voltage VW with
the external input voltage VNI. The comparator and its
logic level output are controlled by the shutdown,
latch, and enable bits of the analog control register
(ACR). Enable connects the comparator output to the
VOUT pin, Latch memorizes the output logic state, and
shutdown removes the analog section supply voltages
to save power. The analog control register (ACR) is
programmed using the SPI serial interface.
VOUT0, VOUT1
WP
V+,V-
Buffered Comparator Outputs
Hardware Write Protection
Analog and Voltage Comparator
Supplies
VCC
System Supply Voltage
VSS
System Ground
NC
No Connection
The ACR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the ACR. These data registers and
the ACR may be read and written by the host system.
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X9440
The wiper counter and analog control register are volatile registers; that is, their contents are lost when the
X9440 is powered-down. Although the registers are
automatically loaded with the value in R0 upon powerup, it should be noted this may be different from the
value present at power-down.
REGISTERS
Both digitally-controlled potentiometers and voltage comparators share the serial interface and share a common
architecture. Each potentiometer and voltage comparator
is associated with wiper counter and analog control registers and eight data registers. A detailed discussion of
the register organization and array operation follows.
Programming the ACR is similar to the WCR. However, the 6 bits in the WCR positions the wiper in the
resistor array while 3 bits in the ACR control the comparator and its output.
Wiper Counter (WCR) and Analog Control
Registers (ACR)
The X9440 contains two wiper counter registers: one
for each XDCP potentiometer and two Analog Control
Registers, and one for each of the two voltage comparators. The wiper counter register is equivalent to a
serial-in, parallel-out counter with its outputs decoded
to select one of sixty-four switches along its resistor
array. The contents of the wiper counter register and
analog control register can be altered in four ways: it
may be written directly by the host via the Write WCR
instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated
data registers (DR) via the XFR data register instruction (parallel load); it can be modified one step at a
time by the increment/ decrement instruction (WCR
only). Finally, it is loaded with the contents of its data
register zero (R0) upon power-up.
Data Registers (DR)
Each potentiometer and each voltage comparator has
four non volatile data registers (DR). These can be
read or written directly by the host and data can be
transferred between any of the four data registers and
the WCR or ACR. It should be noted all operations
changing data in one of these registers is a non volatile operation and will take a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer or comparator, these registers can be used as regular memory locations that
could store system parameters or user preference data.
Figure 1. Detailed Potentiometer Block Diagram
(One of Two Arrays)
Serial Data Path
Register 0
Register 1
8
Register 2
If WC = 00[H] VW = VL
If WC = 3F[H] VW = VH
VH
Serial
Bus
Input
From Interface
Circuitry
6
Register 3
UP/DN
Modified SCK
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
C
o
u
n
t
e
r
D
e
c
o
d
e
Inc/Dec
Logic
UP/DN
CLK
VL
VW
4
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X9440
REGISTER BIT DESCRIPTIONS
Wiper Counter Register (WCR)
0
0
WP5 WP4 WP3 WP2 WP1
(volatile)
WP0
(LSB)
WP0-WP5 identify wiper position.
Analog Control Register (ACR)
User- User- UserShut0 bit5 bit4 bit3 Latch Enable down
0
(volatile)
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A0-A1 input pins.
The X9440 compares the serial data stream with the
address input state; a successful compare of both
address bits is required for the X9440 to successfully
continue the command sequence. The A0-A1 inputs
can be actively driven by CMOS input signals or tied to
VCC or VSS.
The remaining two bits in the slave byte must be set to 0.
Figure 2. Identification Byte Format
(LSB)
Device Type
Identifier
Shutdown
“1”
“0”
indicates power is connected to the voltage
comparator.
0
1
0
1
0
0
indicates power is not connected to the voltage
comparator.
A1
A0
Device Address
Enable
Instruction Byte
“1”
indicates the output buffer of the voltage
comparator is enabled.
“0”
indicates the output buffer of the voltage
comparator is disabled.
The byte following the address contains the instruction
and register pointer information. The four most significant bits are the instruction. The next four bits point to
one of the two pots or two voltage comparators and
when applicable they point to one of four associated
registers. The format is shown below in Figure 3.
Latch
“1”
indicates the output of the voltage comparator is
memorized or latched.
“0”
indicates the output of the voltage comparator is
not latched.
Userbits—available for user applications
Data Registers (DR, R0-R3)
Figure 3. Instruction Byte Format
Register
Select
I3
I2
I1
Instructions
I0
R1
R0
P1
P0
Pot Select
Wiper Position or Analog Control Data or User Data
(Nonvolatile)
{Refer to Memory Map, Figure 9}
INSTRUCTIONS AND PROGRAMMING
Identification (ID) Byte
The first byte sent to the X9440 from the host, following a CS going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave
address are a device type identifier, for the X9440 this
is fixed as 0101[B] (refer to Figure 2).
5
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select one
of the four data registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits (P1 and P0) selects which one of the four potentiometers is to be affected by the instruction.
The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four data registers
that is to be acted upon when a register oriented instruction is issued. The last two bits (P1 and P0) select which
one of the two potentiometers or which one of the two
voltage comparators is to be affected by the instruction.
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March 28, 2005
X9440
Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9440; either between the host and
one of the data registers or directly between the host
and the wiper counter and analog control registers.
These instructions are: Read Wiper Counter Register
or Analog Control Register, read the current wiper
position of the selected pot or the comparator control
bits, Write Wiper Counter Register or Analog Control
Register, i.e. change current wiper position of the
selected pot or control the voltage comparator; Read
Data Register, read the contents of the selected non
volatile register; Write Data Register, write a new value
to the selected data register. The bit structures of the
instructions are shown in Figure 9.
Four of the ten instructions end with the transmission
of the instruction byte. The basic sequence is illustrated in Figure 4. These two-byte instructions
exchange data between the wiper counter register or
analog control register and one of the data registers. A
transfer from a data register to a wiper counter register
or analog control register is essentially a write to a
static RAM. The response of the wiper to this action
will be delayed tWRL. A transfer from the wiper counter
register current wiper position to a data register is a
write to non volatile memory and takes a minimum of
tWR to complete. The transfer can occur between one
of the two potentiometers or one of the two voltage
comparators and one of its associated registers; or it
may occur globally, wherein the transfer occurs
between both of the potentiometers and voltage comparators and one of their associated registers.
The sequences of the three byte operations are shown
in Figure 5 and Figure 6.
The bit structures of the instructions and the description of the instructions are shown in Figure 10.
Figure 4. Two-Byte Command Sequence
CS
SCK
SI
0
1
0
1
0
0
A1
A0
I3
I2
I1
I0
R1 R0
P1 P0
Figure 5. Three-Byte Command Sequence (Write)
CS
SCL
SI
0
1
0
1
0
6
0
A1 A0
I3
I2
I1 I0
R1 R0 P1 P0
0
0
D5 D4 D3 D2 D1 D0
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March 28, 2005
X9440
Figure 6. Three-Byte Command Sequence (Read)
CS
SCL
SI
Don’t Care
0
1
0
0
1
0
A1 A0
I3
I2
I1 I0
R1 R0 P1 P0
S0
0
0
D5 D4 D3 D2 D1 D0
Figure 7. Increment/Decrement Command Sequence
CS
SCK
SI
0
1
0
1
0
0
A1 A0
I3
I2
Increment/Decrement
The final command is Increment/Decrement. It is different from the other commands, because it’s length is
indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
capability to the host. For each SCK clock pulse (tHIGH)
while SI is HIGH, the selected wiper will move one
resistor segment towards the VH terminal. Similarly, for
each SCK clock pulse while SI is LOW, the selected
I1
I0
0
0
P1
P0
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
wiper will move one resistor segment towards the VL
terminal. A detailed illustration of the sequence and timing for this operation are shown in Figure 7 and 8.
Write in Process
The contents of the data registers are saved to nonvolatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write operation can be monitored by a write in process bit (WIP).
The WIP bit is read with a read status command.
Figure 8. Increment/Decrement Timing Limits
tWRID
SCK
SI
Voltage Out
VW
INC/DEC CMD Issued
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X9440
Figure 9. Memory Map
WCRO
WCR1
ACR0
ACR1
R0
R0
R0
R0
R1
R1
R1
R1
R2
R2
R2
R2
R3
R3
R3
R3
Figure 10. Instruction Set
Read Wiper Counter Register (WCR) or Analog Control Register (ACR)
Read the contents of the Wiper Counter Register or Analog Control Register pointed to by P1 - P0.
device type
device
instruction WCR/ACR
register data
CS
CS
identifier
addresses
opcode
addresses
(sent by slave on SDA)
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 0 0 1 0 0 P P 0 0 D D D D D D Edge
1 0
1 0
5 4 3 2 1 0
P1 P0: 00 - WCR0, 01 - WCR1
P1 P0: 10 - ACR0, 11 - ACR1
Write Wiper Counter Register (WCR) or Analog Control Register (ACR)
Write new value to the Wiper Counter Register or Analog Control Register pointed to by P1 - P0.
device type
device
instruction WCR/ACR
register data
CS
CS
identifier
addresses
opcode
addresses (sent by master on SDA)
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 0 1 0 0 0 P P 0 0 D D D D D D Edge
1 0
1 0
5 4 3 2 1 0
P1 P0: 00 - WCR0, 01 - WCR1
P1 P0: 10 - ACR0, 11 - ACR1
Read Data Register (DR)
Read the contents of the Register pointed to by P1 - P0 and R1 - R0.
device type
device
instruction WCR/ACR/DR
register data
CS
identifier
addresses
opcode
addresses
(sent by master on SDA) CS
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 0 1 1 R R P P 0 0 D D D D D D Edge
1 0
1 0 1 0
5 4 3 2 1 0
R1 R0: 00 - R0, 10 - R1
01 - R2, 11 - R3
Write Data Register (DR)
Write new value to the Register pointed to by P1 - P0 and R1 - R0.
device type
device
instruction WCR/ACR/DR
register data
CS
CS
identifier
addresses
opcode
addresses
(sent by master on SDA)
Falling
Falling
Edge 0 1 0 1 0 0 A A 1 1 0 0 R R P P 0 0 D D D D D D Edge
1 0
1 0 1 0
5 4 3 2 1 0
8
HIGH-VOLTAGE
WRITE CYCLE
FN8200.0
March 28, 2005
X9440
Transfer Data Register to Wiper Counter Register or Analog Control Register
Transfer the contents of the Register pointed to by R1 - R0 to the WCR or ACR pointed to by P1 - P0.
device type
device
instruction WCR/ACR/DR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 1 0 1 R R P P Edge
1 0
1 0 1 0
Transfer Wiper Counter or Analog Control Register to Data Register
Transfer the contents of the WCR or ACR pointed to by P1 - P0 to the Register pointed to by R1 - R0.
device type
device
instruction WCR/ACR/DR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 1 1 0 R R P P Edge
1 0
1 0 1 0
HIGH-VOLTAGE
WRITE CYCLE
Global Transfer Data Register to Wiper Counter or Analog Control Register
Transfer the contents of all four Data Registers pointed to by R1 - R0 to their respective WCR or ACR.
device type
device
instruction
DR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 0 0 0 1 R R 0 0 Edge
1 0
1 0
Global Transfer Wiper Counter or Analog Control Register to Data Register
Transfer the contents of all WCRs and ACRs to their respective data Registers pointed to by R1 - R0.
device type
device
instruction
DR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 0 0 0 R R 0 0 Edge
1 0
1 0
HIGH-VOLTAGE
WRITE CYCLE
Increment/Decrement Wiper Counter Register
Enable Increment/decrement of the WCR pointed to by P1 - P0.
device type
device
instruction
WCR
increment/decrement
CS
CS
identifier
addresses
opcode
addresses (sent by master on SDA)
Falling
Rising
Edge 0 1 0 1 0 0 A A 0 0 1 0 0 0 P P I/ I/ . . . . I/ I/ Edge
1 0
1 0 D D
D D
P1 P0: 00 or 01 only.
I/D: Increment/Decrement, 1/0
Read Status
device type
device
instruction
wiper
Data Byte
identifier
addresses
opcode
addresses
(sent by X9440 on SO)
CS
CS
Falling
Rising
W
Edge 0 1 0 1 0 0 A A 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 I Edge
1 0
P
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March 28, 2005
X9440
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SCK, SCL or any address input
with respect to VSS .................................. -1V to +7V
Voltage on V+ (referenced to VSS) ........................+7V
Voltage on V- (referenced to VSS) ..........................-7V
(V+) - (V-) .............................................................. 12V
Any VH .....................................................................V+
Any VL ......................................................................VLead temperature (soldering, 10 seconds) ........ 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Min.
0°C
Max.
+70°C
Device
X9440
Supply Voltage (VCC) Limits
5V ±10%
Industrial
-40°C
+85°C
X9440-2.7
2.7V to 5.5V
Military
-55°C
+125°C
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
RTOTAL
Parameter
End to end resistance
Min.
Typ.
Max.
Unit
–20
+20
%
50
mW
–3
+3
mA
40
100
Ω
100
250
Ω
V
Power rating
IW
Wiper current
RW
Wiper resistance
Vv+
VvVTERM
Voltage on V+ pin
Voltage on V- pin
X9440
+4.5
+5.5
X9440-2.7
+2.7
+5.5
X9440
-5.5
-4.5
X9440-2.7
-5.5
-2.7
V-
V+
Voltage on any VH or VL pin
Noise
Resolution (4)
Absolute
linearity (1)
Relative linearity (2)
Temperature coefficient of RTOTAL
Test Conditions
25°C, each pot
VCC = 5V, Wiper Current = 3mA
VCC = 2.7-5V, Wiper Current = 3mA
V
V
-120
dBV
1.6
%
Ref: 1kHz
-1
+1
MI(3)
Vw(n)(actual) - Vw(n)(expected)
-0.2
+0.2
MI(3)
Vw(n + 1 - [Vw(n) + MI]
±300
ppm/°C
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (VH - VL)/63, single pot
(4) Individual array resolutions.
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X9440
COMPARATOR ELECTRICAL CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
VOS
IB
VIR
Parameter
Input offset voltage
Min.
Typ.
-1
-5
Input current
Max.
Unit
1
5
mV
mV
10
Input voltage range
V-
V
tR
Response time
IO
Output current
AV
Voltage gain
300
V/mV
Power supply rejection ratio
60
dB
PSRR
VOR
TCVOS
Output voltage range
200
Input offset voltage drift
ns
1
VSS
V+/V- = ±3V
V+/V- = ±5V
pA
V+
-1
Test Conditions
VCC
note 1
mA
V
6
µV/°C
IS
Supply current (V+ to V-)
1.2
.5
mA
mA
V+/V- = ±5V
V+/V- = ±3V
TON
Comparator enable time
1
µs
note 2
VOL
Output low voltage
V
IO = 1mA
VOH
Output high voltage
V
IO = 1mA
0.4
VCC-0.8
Notes: (1) 100mV step with 100mV overdrive, ZL = 10kΩ || 15pF, 10-90% risetime
(2) Time from leading edge of Enable bit to valid VOUT.
11
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X9440
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
400
µA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ICC1
VCC supply current (active)
ICC2
VCC supply current (nonvolatile
write)
1
mA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ISB
VCC current (standby)
1
µA
SCK = SI = VSS, Addr. = VSS
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC + 0.5
V
VIL
Input LOW voltage
-0.5
VCC x 0.1
V
VOL
Output LOW voltage
0.4
V
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Unit
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
Years
CAPACITANCE
Symbol
Test
Max.
Unit
Test Conditions
CI/O
Output capacitance (SO)
8
pF
VOUT = 0V
CIN
Input capacitance (A0, A1, SI, and SCK)
6
pF
VIN = 0V
10/10/25
pF
CL, CH, CW
Potentiometer capacitance
POWER-UP SEQUENCE
Power-up Sequence(1): (1) VCC
(2) V+ and V-
{V+ ≤ VCC at all times}
Power-down Sequence: no limitation
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
Note:
(1) Applicable to recall and power consumption applications
5V
2.7V
1533Ω
SDA Output
100pF
12
100pF
FN8200.0
March 28, 2005
X9440
AC TIMING
Symbol
Parameter
Min.
Max.
Unit
2.0
MHz
fSCK
SSI/SPI clock frequency
tCYC
SSI/SPI clock cycle time
500
ns
tWH
SSI/SPI clock high time
200
ns
tWL
SSI/SPI clock low time
200
ns
tLEAD
Lead time
250
ns
tLAG
Lag time
250
ns
tSU
SI, SCK, HOLD and CS input setup time
50
ns
tH
SI, SCK, HOLD and CS input hold time
50
ns
tRI
SI, SCK, HOLD and CS input rise time
2
µs
tFI
SI, SCK, HOLD and CS input fall time
2
µs
500
ns
100
ns
tDIS
SO output disable time
tV
SO output valid time
tHO
SO output hold time
tRO
SO output rise time
tFO
SO output fall time
0
0
ns
50
ns
50
ns
tHOLD
HOLD time
400
ns
tHSU
HOLD setup time
100
ns
tHH
HOLD hold time
100
ns
tHZ
HOLD low to output in high Z
100
ns
tLZ
HOLD high to output in low Z
100
ns
TI
Noise suppression time constant at
SI, SCK, HOLD and CS inputs
20
ns
tCS
CS Deselect Time
2
µs
tWPASU
WP, A0 and A1 setup time
0
ns
tWPAH
WP, A0 and A1 hold time
0
ns
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
tWR
Parameter
High-voltage write cycle time (store instructions)
Typ.
Max.
Unit
5
10
ms
XDCP TIMING
Symbol
tWRPO
Parameter
Min. Max. Unit
Wiper response time after the third (last) power supply is stable
10
µs
tWRL
Wiper response time after instruction issued (all load instructions)
10
µs
tWRID
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
450
µs
13
FN8200.0
March 28, 2005
X9440
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
TIMING DIAGRAMS
Input Timing
tCS
CS
tLAG
tCYC
tLEAD
SCK
...
tSU
tH
tWL
...
MSB
SI
tRI
tFI
tWH
LSB
High Impedance
SO
Output Timing
CS
SCK
...
tV
MSB
SO
SI
tHO
tDIS
...
LSB
ADDR
14
FN8200.0
March 28, 2005
X9440
Hold Timing
CS
tHSU
tHH
SCK
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
XDCP Timing (for All Load Instructions)
CS
SCK
...
tWRL
...
MSB
SI
LSB
VWx
SO
High Impedance
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
...
tWRID
...
VWx
ADDR
SI
Inc/Dec
Inc/Dec
...
High Impedance
SO
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
tWPASU
tWPAH
WP
A0
A1
15
FN8200.0
March 28, 2005
X9440
BASIC APPLICATIONS
Programmable Level Detector with Memory (typical bias conditions)
VREF1 (+5V)
+5V
SCL
SCL VCC
SDA
SDA
(+5V)
VH
V+
VW
–
VOUT
VOUT
+
9440
VSS
VL
VNI
V–
VT < VW, VOUT = Low
(-5V)
+
VREF2 (–5V)
VT > VW, VOUT = High
VTRANSDUCER (VT)
–
Programmable Window Detector with Memory
+5V
VOUT0
9440
+
SCL
VW0
SDA
VOUT0
–
VOUT0 = L
VOUT1 = L
VOUT0 = L
VOUT1 = H
VOUT0 = H
VOUT1 = H
+
VOUT1
–
VW1
–5V
VS
VLL
(VW1)
VUL
(VW0)
+
VS
–
For the signal voltage
VS > the upper limit VUL, (VOUT0 = H) • (VOUT1 = H)
VS < the lower limit VLL, (VOUT0 = L) • (VOUT1 = L)
For the window VLL ≤ VS ≤ VUL, (VOUT0 = L) • (VOUT1 = H)
16
FN8200.0
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X9440
BASIC APPLICATION (continued)
Programmable Oscillator with Memory
+5V
VH
SCL
SDA
9440
R
V+
–
VOUT
+
V–
VL VW
R2
C
+5V
R3
R1
Frequency ∝ R, C
Duty Cycle ∝ R1, R2, R3
Programmable Schmitt Trigger with Memory
VR
VH
9440
VW
R
–
V+
VOUT
+
VOUT
V–
VL
VS
VS
R1
R1 + R2
R1
V UL = --------------------- V W – ------- V OUT ( min )
R2
R2
R2
VLL
VUL
R1 + R2
R1
V LL = --------------------- V W – ------- V OUT ( max )
R2
R2
17
FN8200.0
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X9440
BASIC APPLICATION (continued)
Programmable Level Detector (alternate technique)
+
VS
VOUT
R1 {
–
R2 {
VOUT
+
VSS=
VS
-R1
V
R2 R
+
VR
VCC
R1
V OUT = High for V S < – ------- V R
R2
R1
V OUT = Low for V S > – ------- V R
R2
R 1 + R 2 = R POT
Programmable Time Delay with Memory
+5V
VH
VOUT
VW
+5v
–
VOUT
+
t
VS
VW
VNI
VL
+5v
t
VNI
+5v
VOUT
VS
t
Dt
R
C
5V
∆t = RC ln  -----------------------
 5V – V 
W
18
FN8200.0
March 28, 2005
X9440
PACKAGING INFORMATION
24-Lead Plastic Small Outline Gull Wing Package Type S
0.290 (7.37) 0.393 (10.00)
0.299 (7.60) 0.420 (10.65)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050" Typical
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"
Typical
0° - 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
FOOTPRINT
0.030" Typical
24 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
19
FN8200.0
March 28, 2005
X9440
PACKAGING INFORMATION
24-Lead Plastic, TSSOP Package Type V
.026 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
0° - 8°
(4.16) (7.72)
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
Detail A (20X)
(0.42)
(0.65)
.031 (.80)
.041 (1.05)
ALL MEASUREMENTS ARE TYPICAL
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
20
FN8200.0
March 28, 2005
X9440
Ordering Information
X9440
Y
P
T
V
VCC Limits
Blank = 5V ±10%
-2.7 = 2.7 to 5.5V
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Package
P24 = 24-Lead Plastic DIP
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
Potentiometer Organization
Pot 0
Pot 1
W=
10kΩ
10kΩ
Y=
2.5kΩ
2.5kΩ
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
21
FN8200.0
March 28, 2005
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