DATASHEET

X93255
®
Data Sheet
February 4, 2008
Dual Digitally Controlled Potentiometers
(XDCPs™)
FN8187.1
Features
• Dual solid-state potentiometers
The Intersil X93255 is a dual digitally controlled
potentiometer (XDCP). The device consists of two resistor
arrays, wiper switches, a control section, and nonvolatile
memory. The wiper positions are controlled by individual
Up/Down interfaces.
• Independent Up/Down interfaces
• 32 wiper tap points per potentiometer
- Wiper position stored in nonvolatile memory and
recalled on power-up
• 31 resistive elements per potentiometer
- Temperature compensated
- Maximum resistance tolerance ± 25%
- Terminal voltage, 0 to VCC
A potentiometer is implemented by a resistor array
composed of 31 resistive elements and a wiper switching
network. The position of each wiper element is controlled by
a set of independent CS, U/D, and INC inputs. The position
of the wiper can be stored in nonvolatile memory and then
be recalled upon a subsequent power-up operation.
• Low power CMOS
- VCC = 5V ± 10%
- Active current, 200µA typ.
- Standby current, 4µA max
Each potentiometer is connected as a two-terminal variable
resistor and can be used in a wide variety of applications
including:
• High reliability
- Endurance 200,000 data changes per bit
- Register data retention, 100 years
• Bias and gain control
• LCD Contrast Adjustment
• RTOTAL value = 50kΩ
Pinout
• Package
- 14 Ld TSSOP
X93255
(14 LD TSSOP)
TOP VIEW
DNC*
1
14
RH1
RL1
2
13
U/D1
CS1
3
12
INC1
INC2
4
11
VCC
U/D2
5
10
CS2
RH2
6
9
RL2
VSS
7
8
DNC*
*Do not connect.
Ordering Information
PART NUMBER
PART MARKING VCC LIMITS (V)
RTOTAL (kΩ)
TEMP
RANGE (°C)
PACKAGE
PKG DWG. #
X93255UV14I
X9325 5UVI
5 ±10%
50
-40 to +85
14 Ld TSSOP
M14.173
X93255UV14IT1*
X9325 5UVI
5 ±10%
50
-40 to +85
14 Ld TSSOP
M14.173
* Please refer to TB347 for details on reel specifications.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X93255
Block Diagram
VCC (SUPPLY VOLTAGE)
RH1
30kΩ
30kΩ
UP/DOWN
(U/D1)
CONTROL
AND
MEMORY
INCREMENT
(INC1)
RL1
RH2
DEVICE SELECT
(CS1)
UP/DOWN
(U/D2)
RL2
CONTROL
AND
MEMORY
INCREMENT
(INC2)
DEVICE SELECT
(CS2)
VSS (GROUND)
Pin Descriptions
TSSOP
SYMBOL
1
DNC
Do Not Connect
2
RL1
Low Terminal 1
3
CS1
Chip Select 1
4
INC2
Increment 2
5
U/D2
Up/Down 2
6
RH2
High Terminal 2
7
VSS
Ground
8
DNC
Do Not Connect
9
RL2
Low Terminal 2
10
CS2
Chip Select 2
11
VCC
Supply Voltage
12
INC1
Increment 1
13
U/D1
Up/Down 1
14
RH1
High Terminal 1
2
DESCRIPTION
FN8187.1
February 4, 2008
X93255
Absolute Maximum Ratings
Thermal Information
Voltage on CS, INC, U/D, RH, RL and VCC
with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +6.5V
Maximum resistor current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2mA
Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . +300°C
Maximum reflow temperature (40s) . . . . . . . . . . . . . . . . . . . . +240°C
Recommended Operating Conditions
Temperature Range
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10% (Note 6)
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Absolute linearity is utilized to determine actual wiper resistance vs expected resistance = (RH(n)(actual) - RH(n)(expected)) =
±1 Ml Maximum. n = 1 .. 29 only
2. Relative linearity is a measure of the error in step size between taps = RH(n+1) - [RH(n) + Ml] = ±0.5 Ml, n = 1 .. 29 only.
3. 1 Ml = Minimum Increment = RTOT/31.
4. Typical values are for TA = +25°C and nominal supply voltage.
5. Limits established by characterization and are not production tested.
6. When performing multiple write operations, VCC must not decrease by more than 150mV from its initial value.
7. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
Potentiometer Characteristics
SYMBOL
RTOT
VR
Over recommended operating conditions, unless otherwise specified.
PARAMETER
TEST CONDITIONS/NOTES
End-to-End Resistance
RH, RL Terminal Voltages
MIN
(Note 7)
TYP
(Note 4)
MAX
(Note 7)
UNIT
37.5
50
62.5
kΩ
VCC
V
1
mΩ
(Note 6)
0
Power Rating
RTOTAL = 50kΩ (Note 5)
Noise
Ref: 1kHz (Note 5)
RW
Wiper Resistance
(Note 5)
1000
Ω
IW
Wiper Current
(Note 5)
0.6
mA
Resolution
CH/CL/CW
-120
dBV
(Note 6)
3
Absolute Linearity (Note 1)
RH(n)(actual) - RH(n)(expected)
Relative Linearity (Note 2)
RH(n+1 - [RH(n)+MI]
RTOTAL Temperature Coefficient
(Notes 5)
Potentiometer Capacitances
See “Circuit #2 SPICE Macro Model”
on page 4
3
%
±1
MI
(Note 3)
±0.5
MI
(Note 3)
±35
ppm/°C
10/10/25
pF
FN8187.1
February 4, 2008
X93255
DC Operating Specifications
SYMBOL
Over recommended operating conditions unless otherwise specified.
PARAMETER
MIN
(Note 7)
TEST CONDITIONS
TYP
(Note 4)
MAX
(Note 7)
UNIT
200
300
µA
1400
µA
ICC1
VCC Active Current (Increment) per DCP CS = VIL, U/D = VIL or VIH and
INC = 0.4V @ max. tCYC
ICC2
VCC Active Current (Store)
(EEPROM Store) per DCP
CS = VIH, U/D = VIL or VIH and
INC = VIH @ max. tWR
ISB
Standby Supply Current
CS = VCC - 0.3V, U/D and
INC = VSS or VCC - 0.3V
4
µA
ILI
CS
VCS = VCC
±1
µA
ILI
CS
VCC = 5V, CS = 0
250
µA
ILI
INC, U/D Input Leakage Current
VIN = VSS to VCC
±1
µA
VIH
CS, INC, U/D Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VIL
CS, INC, U/D Input LOW Voltage
-0.5
VCC x 0.1
V
CIN
(Note 6)
CS, INC, U/D Input Capacitance
10
pF
200
VCC = 5V, VIN = VSS, TA = +25°C,
f = 1MHz (Note 5)
Endurance and Data Retention
AC Conditions of Test
PARAMETER
MIN
UNIT
Minimum endurance
200,000
Data changes per bit
Data retention
100
Years
Test Circuit #1
120
Input pulse levels
0V to 5V
Input rise and fall times
10ns
Input reference levels
1.5V
Circuit #2 SPICE Macro Model
TEST POINT
RTOTAL
VH/RH
RH
CH
CL
CW
RL
10pF
25pF
10pF
AC Operating Characteristics Over recommended operating conditions unless otherwise specified. In the table, CS, INC, U/D, RH and
RL are used to refer to either CS1 or CS2, etc.
SYMBOL
PARAMETER
MIN
(Note 7)
TYP
(Note 4)
MAX
(Note 7)
UNIT
tCl
CS to INC Setup
100
ns
tlD
INC HIGH to U/D Change
100
ns
tDI
U/D to INC Setup
100
ns
tlL
INC LOW Period
1
µs
tlH
INC HIGH Period
1
µs
tlC
INC Inactive to CS Inactive
1
µs
tCPH
CS Deselect Time (No store)
250
ns
tCPH
CS Deselect Time (Store)
10
ms
INC Cycle Time
2
tCYC
tR, tF
(Note 5)
INC Input Rise and Fall Time
tR VCC
(Note 5)
VCC Power-up Rate
tWR
Store cycle
µs
1
5
4
500
µs
50
V/ms
10
ms
FN8187.1
February 4, 2008
X93255
AC Timing
CS
tCYC
tCI
tIL
tIH
tIC
(STORE)
tCPH
90%
INC
90%
10%
tID
tDI
tF
tR
U/D
Note: CS, INC, U/D, RH and RL are used to refer
to either CS1 or CS2, etc.
Power-up and Power-down Requirements
Principles of Operation
There are no restrictions on the power-up or power-down
conditions of VCC and the voltages applied to the
potentiometer pins provided that VCC is always more
positive than or equal to VH and VL, i.e., VCC ≥ VH,VL. The
VCC ramp rate specification is always in effect.
There are multiple sections for each potentiometer in the
X93255: an input control, a counter and decode section; the
nonvolatile memory; and a resistor array. Each input control
section operates just like an up/down counter. The output of
this counter is decoded to turn on a single electronic switch
connecting a point on the resistor array to the wiper output.
Under the proper conditions, the contents of the counter can
be stored in nonvolatile memory and retained for future use.
Each resistor array is comprised of 31 individual resistors
connected in series. At either end of the array and between
each resistor is an electronic switch that transfers the
connection at that point to the wiper. The wiper is connected
to the RL terminal, forming a variable resistor from RH to RL.
Pin Descriptions
RH and RL
The RH and RL pins of the X93255 are equivalent to the end
terminals of a variable resistor. The minimum voltage is VSS
and the maximum is VCC. The terminology of RH and RL
references the relative position of the terminal in relation to
wiper movement direction selected by the U/D input per
potentiometer.
Up/Down (U/D)
The U/D input controls the direction of a single
potentiometer’s wiper movement and whether the counter is
incremented or decremented.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the
pertaining potentiometer’s counter in the direction indicated
by the logic level on the pertaining potentiometer’s U/D
input.
Chip Select (CS)
Each wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
If the wiper is moved several positions, multiple taps are
connected to the wiper for up to 10µs. The 2-terminal
resistance value for the device can temporarily change by a
significant amount if the wiper is moved several positions.
When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory for each
potentiometer. When power is restored, the contents of the
memory are recalled and each wiper is set to the value last
stored.
A potentiometer is selected when the pertaining CS input is
LOW. Its current counter value is stored in nonvolatile
memory when the pertaining CS is returned HIGH while the
pertaining INC input is also HIGH. After the store operation
is complete, the affected potentiometer will be placed in the
low power standby mode until the potentiometer is selected
once again.
5
FN8187.1
February 4, 2008
X93255
Instructions and Programming
The INC, U/D and CS inputs control the movement of the
pertaining wiper along the resistor array. With CS set LOW,
the pertaining potentiometer is selected and enabled to
respond to the U/D and INC inputs. HIGH to LOW transitions
on INC will increment or decrement (depending on the state
of the U/D input) a 5-bit counter. The output of this counter is
decoded to select one of thirty two wiper positions along the
resistive array.
The value of the counter is stored in nonvolatile memory
whenever each CS transitions HIGH while the pertaining
INC input is also HIGH. In order to avoid an accidental store
during power-up, each CS must go HIGH with VCC during
initial power-up. When left open, each CS pin is internally
pulled up to VCC by an internal 30k resistor.
The system may select the X93255, move any wiper and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as previously described and once the new
position is reached, the system must keep INC LOW while
taking CS HIGH. The new wiper position will be maintained
until changed by the system or until a power-up/down cycle
recalled the previously stored data. In order to recall the
stored position of the wiper on power-up, the CS pin must be
held HIGH.
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation minor adjustments could be made. The
adjustments might be based on user preference, system
parameter changes due to temperature drift, or other system
trim requirements.
Mode Selection
CS
INC
U/D
MODE
L
H
Wiper Up
L
L
Wiper Down
H
X
Store Wiper Position
X
X
Standby Current
L
X
No Store, Return to Standby
L
H
Wiper Up (not recommended)
L
L
Wiper Down (not recommended)
H
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
The state of U/D may be changed while CS remains LOW.
This allows the host system to enable the device and then
move each wiper up and down until the proper trim is
attained.
6
FN8187.1
February 4, 2008
X93255
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
SYMBOL
3
0.05(0.002)
-A-
INCHES
GAUGE
PLANE
-B1
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
B M
0.25
0.010
SEATING PLANE
L
A
D
-C-
e
α
A1
b
A2
c
0.10(0.004)
0.10(0.004) M
C A M
B S
MIN
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
MILLIMETERS
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.041
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.195
0.199
4.95
5.05
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
NOTES:
MAX
α
14
0o
14
7
8o
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
7
FN8187.1
February 4, 2008
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